These are the bulk pinctrl changes for kernel v3.7:
- Add subdrivers for the DB8540 and NHK8815 Nomadik-type ASICs,
provide platform config for the Nomadik.
- Add a driver for the i.MX35.
- Add a driver for the BCM2835, an advanced GPIO expander.
- Various fixes and clean-ups and minor improvements for the core,
Nomadik, pinctr-single, sirf drivers.
- Some platform config for the ux500.
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Merge tag 'pinctrl-for-v3.7' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl
Pull pinctrl changes from Linus Walleij:
"Some of this stuff is hitting arch/arm/* and have been ACKed by the
ARM SoC folks, or it's device tree bindings pertaining to the specific
driver.
These are the bulk pinctrl changes for kernel v3.7:
- Add subdrivers for the DB8540 and NHK8815 Nomadik-type ASICs,
provide platform config for the Nomadik.
- Add a driver for the i.MX35.
- Add a driver for the BCM2835, an advanced GPIO expander.
- Various fixes and clean-ups and minor improvements for the core,
Nomadik, pinctr-single, sirf drivers.
- Some platform config for the ux500."
* tag 'pinctrl-for-v3.7' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl: (27 commits)
pinctrl: add bcm2835 driver
pinctrl: clarify idle vs sleep states
pinctrl/nomadik: use irq_find_mapping()
pinctrl: sirf: add lost chained_irq_enter and exit in sirfsoc_gpio_handle_irq
pinctrl: sirf: initialize the irq_chip pointer of pinctrl_gpio_range
pinctrl: sirf: fix spinlock deadlock in sirfsoc_gpio_set_input
pinctrl: sirf: add missing pins to pinctrl list
pinctrl: sirf: fix a typo in sirfsoc_gpio_probe
pinctrl: pinctrl-single: add debugfs pin h/w state info
ARM: ux500: 8500: update I2C sleep states pinctrl
pinctrl: Fix potential memory leak in pinctrl_register_one_pin()
ARM: ux500: tidy up pin sleep modes
ARM: ux500: fix spi2 pin group
pinctrl: imx: remove duplicated const
pinctrl: document semantics vs GPIO
ARM: ux500: 8500: use hsit_a_2 group for HSI
pinctrl: use kasprintf() in pinmux_request_gpio()
pinctrl: pinctrl-single: Add pinctrl-single,bits type of mux
pinctrl/nomadik : add MC1_a_2 pin MC1 function group list
pinctrl: pinctrl-single: Make sure we do not change bits outside of mask
...
This commit is contained in:
Linus Torvalds
commit
06fe918e9f
26 changed files with 5868 additions and 516 deletions
|
|
@ -0,0 +1,74 @@
|
|||
Broadcom BCM2835 GPIO (and pinmux) controller
|
||||
|
||||
The BCM2835 GPIO module is a combined GPIO controller, (GPIO) interrupt
|
||||
controller, and pinmux/control device.
|
||||
|
||||
Required properties:
|
||||
- compatible: "brcm,bcm2835-gpio"
|
||||
- reg: Should contain the physical address of the GPIO module's registes.
|
||||
- gpio-controller: Marks the device node as a GPIO controller.
|
||||
- #gpio-cells : Should be two. The first cell is the pin number and the
|
||||
second cell is used to specify optional parameters:
|
||||
- bit 0 specifies polarity (0 for normal, 1 for inverted)
|
||||
- interrupts : The interrupt outputs from the controller. One interrupt per
|
||||
individual bank followed by the "all banks" interrupt.
|
||||
- interrupt-controller: Marks the device node as an interrupt controller.
|
||||
- #interrupt-cells : Should be 2.
|
||||
The first cell is the GPIO number.
|
||||
The second cell is used to specify flags:
|
||||
bits[3:0] trigger type and level flags:
|
||||
1 = low-to-high edge triggered.
|
||||
2 = high-to-low edge triggered.
|
||||
4 = active high level-sensitive.
|
||||
8 = active low level-sensitive.
|
||||
Valid combinations are 1, 2, 3, 4, 8.
|
||||
|
||||
Please refer to ../gpio/gpio.txt for a general description of GPIO bindings.
|
||||
|
||||
Please refer to pinctrl-bindings.txt in this directory for details of the
|
||||
common pinctrl bindings used by client devices, including the meaning of the
|
||||
phrase "pin configuration node".
|
||||
|
||||
Each pin configuration node lists the pin(s) to which it applies, and one or
|
||||
more of the mux function to select on those pin(s), and pull-up/down
|
||||
configuration. Each subnode only affects those parameters that are explicitly
|
||||
listed. In other words, a subnode that lists only a mux function implies no
|
||||
information about any pull configuration. Similarly, a subnode that lists only
|
||||
a pul parameter implies no information about the mux function.
|
||||
|
||||
Required subnode-properties:
|
||||
- brcm,pins: An array of cells. Each cell contains the ID of a pin. Valid IDs
|
||||
are the integer GPIO IDs; 0==GPIO0, 1==GPIO1, ... 53==GPIO53.
|
||||
|
||||
Optional subnode-properties:
|
||||
- brcm,function: Integer, containing the function to mux to the pin(s):
|
||||
0: GPIO in
|
||||
1: GPIO out
|
||||
2: alt5
|
||||
3: alt4
|
||||
4: alt0
|
||||
5: alt1
|
||||
6: alt2
|
||||
7: alt3
|
||||
- brcm,pull: Integer, representing the pull-down/up to apply to the pin(s):
|
||||
0: none
|
||||
1: down
|
||||
2: up
|
||||
|
||||
Each of brcm,function and brcm,pull may contain either a single value which
|
||||
will be applied to all pins in brcm,pins, or 1 value for each entry in
|
||||
brcm,pins.
|
||||
|
||||
Example:
|
||||
|
||||
gpio: gpio {
|
||||
compatible = "brcm,bcm2835-gpio";
|
||||
reg = <0x2200000 0xb4>;
|
||||
interrupts = <2 17>, <2 19>, <2 18>, <2 20>;
|
||||
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
};
|
||||
984
Documentation/devicetree/bindings/pinctrl/fsl,imx35-pinctrl.txt
Normal file
984
Documentation/devicetree/bindings/pinctrl/fsl,imx35-pinctrl.txt
Normal file
|
|
@ -0,0 +1,984 @@
|
|||
* Freescale IMX35 IOMUX Controller
|
||||
|
||||
Please refer to fsl,imx-pinctrl.txt in this directory for common binding part
|
||||
and usage.
|
||||
|
||||
Required properties:
|
||||
- compatible: "fsl,imx35-iomuxc"
|
||||
- fsl,pins: two integers array, represents a group of pins mux and config
|
||||
setting. The format is fsl,pins = <PIN_FUNC_ID CONFIG>, PIN_FUNC_ID is a
|
||||
pin working on a specific function, CONFIG is the pad setting value like
|
||||
pull-up for this pin. Please refer to imx35 datasheet for the valid pad
|
||||
config settings.
|
||||
|
||||
CONFIG bits definition:
|
||||
PAD_CTL_DRIVE_VOLAGAGE_18 (1 << 13)
|
||||
PAD_CTL_DRIVE_VOLAGAGE_33 (0 << 13)
|
||||
PAD_CTL_HYS (1 << 8)
|
||||
PAD_CTL_PKE (1 << 7)
|
||||
PAD_CTL_PUE (1 << 6)
|
||||
PAD_CTL_PUS_100K_DOWN (0 << 4)
|
||||
PAD_CTL_PUS_47K_UP (1 << 4)
|
||||
PAD_CTL_PUS_100K_UP (2 << 4)
|
||||
PAD_CTL_PUS_22K_UP (3 << 4)
|
||||
PAD_CTL_ODE_CMOS (0 << 3)
|
||||
PAD_CTL_ODE_OPENDRAIN (1 << 3)
|
||||
PAD_CTL_DSE_NOMINAL (0 << 1)
|
||||
PAD_CTL_DSE_HIGH (1 << 1)
|
||||
PAD_CTL_DSE_MAX (2 << 1)
|
||||
PAD_CTL_SRE_FAST (1 << 0)
|
||||
PAD_CTL_SRE_SLOW (0 << 0)
|
||||
|
||||
See below for available PIN_FUNC_ID for imx35:
|
||||
0 MX35_PAD_CAPTURE__GPT_CAPIN1
|
||||
1 MX35_PAD_CAPTURE__GPT_CMPOUT2
|
||||
2 MX35_PAD_CAPTURE__CSPI2_SS1
|
||||
3 MX35_PAD_CAPTURE__EPIT1_EPITO
|
||||
4 MX35_PAD_CAPTURE__CCM_CLK32K
|
||||
5 MX35_PAD_CAPTURE__GPIO1_4
|
||||
6 MX35_PAD_COMPARE__GPT_CMPOUT1
|
||||
7 MX35_PAD_COMPARE__GPT_CAPIN2
|
||||
8 MX35_PAD_COMPARE__GPT_CMPOUT3
|
||||
9 MX35_PAD_COMPARE__EPIT2_EPITO
|
||||
10 MX35_PAD_COMPARE__GPIO1_5
|
||||
11 MX35_PAD_COMPARE__SDMA_EXTDMA_2
|
||||
12 MX35_PAD_WDOG_RST__WDOG_WDOG_B
|
||||
13 MX35_PAD_WDOG_RST__IPU_FLASH_STROBE
|
||||
14 MX35_PAD_WDOG_RST__GPIO1_6
|
||||
15 MX35_PAD_GPIO1_0__GPIO1_0
|
||||
16 MX35_PAD_GPIO1_0__CCM_PMIC_RDY
|
||||
17 MX35_PAD_GPIO1_0__OWIRE_LINE
|
||||
18 MX35_PAD_GPIO1_0__SDMA_EXTDMA_0
|
||||
19 MX35_PAD_GPIO1_1__GPIO1_1
|
||||
20 MX35_PAD_GPIO1_1__PWM_PWMO
|
||||
21 MX35_PAD_GPIO1_1__CSPI1_SS2
|
||||
22 MX35_PAD_GPIO1_1__SCC_TAMPER_DETECT
|
||||
23 MX35_PAD_GPIO1_1__SDMA_EXTDMA_1
|
||||
24 MX35_PAD_GPIO2_0__GPIO2_0
|
||||
25 MX35_PAD_GPIO2_0__USB_TOP_USBOTG_CLK
|
||||
26 MX35_PAD_GPIO3_0__GPIO3_0
|
||||
27 MX35_PAD_GPIO3_0__USB_TOP_USBH2_CLK
|
||||
28 MX35_PAD_RESET_IN_B__CCM_RESET_IN_B
|
||||
29 MX35_PAD_POR_B__CCM_POR_B
|
||||
30 MX35_PAD_CLKO__CCM_CLKO
|
||||
31 MX35_PAD_CLKO__GPIO1_8
|
||||
32 MX35_PAD_BOOT_MODE0__CCM_BOOT_MODE_0
|
||||
33 MX35_PAD_BOOT_MODE1__CCM_BOOT_MODE_1
|
||||
34 MX35_PAD_CLK_MODE0__CCM_CLK_MODE_0
|
||||
35 MX35_PAD_CLK_MODE1__CCM_CLK_MODE_1
|
||||
36 MX35_PAD_POWER_FAIL__CCM_DSM_WAKEUP_INT_26
|
||||
37 MX35_PAD_VSTBY__CCM_VSTBY
|
||||
38 MX35_PAD_VSTBY__GPIO1_7
|
||||
39 MX35_PAD_A0__EMI_EIM_DA_L_0
|
||||
40 MX35_PAD_A1__EMI_EIM_DA_L_1
|
||||
41 MX35_PAD_A2__EMI_EIM_DA_L_2
|
||||
42 MX35_PAD_A3__EMI_EIM_DA_L_3
|
||||
43 MX35_PAD_A4__EMI_EIM_DA_L_4
|
||||
44 MX35_PAD_A5__EMI_EIM_DA_L_5
|
||||
45 MX35_PAD_A6__EMI_EIM_DA_L_6
|
||||
46 MX35_PAD_A7__EMI_EIM_DA_L_7
|
||||
47 MX35_PAD_A8__EMI_EIM_DA_H_8
|
||||
48 MX35_PAD_A9__EMI_EIM_DA_H_9
|
||||
49 MX35_PAD_A10__EMI_EIM_DA_H_10
|
||||
50 MX35_PAD_MA10__EMI_MA10
|
||||
51 MX35_PAD_A11__EMI_EIM_DA_H_11
|
||||
52 MX35_PAD_A12__EMI_EIM_DA_H_12
|
||||
53 MX35_PAD_A13__EMI_EIM_DA_H_13
|
||||
54 MX35_PAD_A14__EMI_EIM_DA_H2_14
|
||||
55 MX35_PAD_A15__EMI_EIM_DA_H2_15
|
||||
56 MX35_PAD_A16__EMI_EIM_A_16
|
||||
57 MX35_PAD_A17__EMI_EIM_A_17
|
||||
58 MX35_PAD_A18__EMI_EIM_A_18
|
||||
59 MX35_PAD_A19__EMI_EIM_A_19
|
||||
60 MX35_PAD_A20__EMI_EIM_A_20
|
||||
61 MX35_PAD_A21__EMI_EIM_A_21
|
||||
62 MX35_PAD_A22__EMI_EIM_A_22
|
||||
63 MX35_PAD_A23__EMI_EIM_A_23
|
||||
64 MX35_PAD_A24__EMI_EIM_A_24
|
||||
65 MX35_PAD_A25__EMI_EIM_A_25
|
||||
66 MX35_PAD_SDBA1__EMI_EIM_SDBA1
|
||||
67 MX35_PAD_SDBA0__EMI_EIM_SDBA0
|
||||
68 MX35_PAD_SD0__EMI_DRAM_D_0
|
||||
69 MX35_PAD_SD1__EMI_DRAM_D_1
|
||||
70 MX35_PAD_SD2__EMI_DRAM_D_2
|
||||
71 MX35_PAD_SD3__EMI_DRAM_D_3
|
||||
72 MX35_PAD_SD4__EMI_DRAM_D_4
|
||||
73 MX35_PAD_SD5__EMI_DRAM_D_5
|
||||
74 MX35_PAD_SD6__EMI_DRAM_D_6
|
||||
75 MX35_PAD_SD7__EMI_DRAM_D_7
|
||||
76 MX35_PAD_SD8__EMI_DRAM_D_8
|
||||
77 MX35_PAD_SD9__EMI_DRAM_D_9
|
||||
78 MX35_PAD_SD10__EMI_DRAM_D_10
|
||||
79 MX35_PAD_SD11__EMI_DRAM_D_11
|
||||
80 MX35_PAD_SD12__EMI_DRAM_D_12
|
||||
81 MX35_PAD_SD13__EMI_DRAM_D_13
|
||||
82 MX35_PAD_SD14__EMI_DRAM_D_14
|
||||
83 MX35_PAD_SD15__EMI_DRAM_D_15
|
||||
84 MX35_PAD_SD16__EMI_DRAM_D_16
|
||||
85 MX35_PAD_SD17__EMI_DRAM_D_17
|
||||
86 MX35_PAD_SD18__EMI_DRAM_D_18
|
||||
87 MX35_PAD_SD19__EMI_DRAM_D_19
|
||||
88 MX35_PAD_SD20__EMI_DRAM_D_20
|
||||
89 MX35_PAD_SD21__EMI_DRAM_D_21
|
||||
90 MX35_PAD_SD22__EMI_DRAM_D_22
|
||||
91 MX35_PAD_SD23__EMI_DRAM_D_23
|
||||
92 MX35_PAD_SD24__EMI_DRAM_D_24
|
||||
93 MX35_PAD_SD25__EMI_DRAM_D_25
|
||||
94 MX35_PAD_SD26__EMI_DRAM_D_26
|
||||
95 MX35_PAD_SD27__EMI_DRAM_D_27
|
||||
96 MX35_PAD_SD28__EMI_DRAM_D_28
|
||||
97 MX35_PAD_SD29__EMI_DRAM_D_29
|
||||
98 MX35_PAD_SD30__EMI_DRAM_D_30
|
||||
99 MX35_PAD_SD31__EMI_DRAM_D_31
|
||||
100 MX35_PAD_DQM0__EMI_DRAM_DQM_0
|
||||
101 MX35_PAD_DQM1__EMI_DRAM_DQM_1
|
||||
102 MX35_PAD_DQM2__EMI_DRAM_DQM_2
|
||||
103 MX35_PAD_DQM3__EMI_DRAM_DQM_3
|
||||
104 MX35_PAD_EB0__EMI_EIM_EB0_B
|
||||
105 MX35_PAD_EB1__EMI_EIM_EB1_B
|
||||
106 MX35_PAD_OE__EMI_EIM_OE
|
||||
107 MX35_PAD_CS0__EMI_EIM_CS0
|
||||
108 MX35_PAD_CS1__EMI_EIM_CS1
|
||||
109 MX35_PAD_CS1__EMI_NANDF_CE3
|
||||
110 MX35_PAD_CS2__EMI_EIM_CS2
|
||||
111 MX35_PAD_CS3__EMI_EIM_CS3
|
||||
112 MX35_PAD_CS4__EMI_EIM_CS4
|
||||
113 MX35_PAD_CS4__EMI_DTACK_B
|
||||
114 MX35_PAD_CS4__EMI_NANDF_CE1
|
||||
115 MX35_PAD_CS4__GPIO1_20
|
||||
116 MX35_PAD_CS5__EMI_EIM_CS5
|
||||
117 MX35_PAD_CS5__CSPI2_SS2
|
||||
118 MX35_PAD_CS5__CSPI1_SS2
|
||||
119 MX35_PAD_CS5__EMI_NANDF_CE2
|
||||
120 MX35_PAD_CS5__GPIO1_21
|
||||
121 MX35_PAD_NF_CE0__EMI_NANDF_CE0
|
||||
122 MX35_PAD_NF_CE0__GPIO1_22
|
||||
123 MX35_PAD_ECB__EMI_EIM_ECB
|
||||
124 MX35_PAD_LBA__EMI_EIM_LBA
|
||||
125 MX35_PAD_BCLK__EMI_EIM_BCLK
|
||||
126 MX35_PAD_RW__EMI_EIM_RW
|
||||
127 MX35_PAD_RAS__EMI_DRAM_RAS
|
||||
128 MX35_PAD_CAS__EMI_DRAM_CAS
|
||||
129 MX35_PAD_SDWE__EMI_DRAM_SDWE
|
||||
130 MX35_PAD_SDCKE0__EMI_DRAM_SDCKE_0
|
||||
131 MX35_PAD_SDCKE1__EMI_DRAM_SDCKE_1
|
||||
132 MX35_PAD_SDCLK__EMI_DRAM_SDCLK
|
||||
133 MX35_PAD_SDQS0__EMI_DRAM_SDQS_0
|
||||
134 MX35_PAD_SDQS1__EMI_DRAM_SDQS_1
|
||||
135 MX35_PAD_SDQS2__EMI_DRAM_SDQS_2
|
||||
136 MX35_PAD_SDQS3__EMI_DRAM_SDQS_3
|
||||
137 MX35_PAD_NFWE_B__EMI_NANDF_WE_B
|
||||
138 MX35_PAD_NFWE_B__USB_TOP_USBH2_DATA_3
|
||||
139 MX35_PAD_NFWE_B__IPU_DISPB_D0_VSYNC
|
||||
140 MX35_PAD_NFWE_B__GPIO2_18
|
||||
141 MX35_PAD_NFWE_B__ARM11P_TOP_TRACE_0
|
||||
142 MX35_PAD_NFRE_B__EMI_NANDF_RE_B
|
||||
143 MX35_PAD_NFRE_B__USB_TOP_USBH2_DIR
|
||||
144 MX35_PAD_NFRE_B__IPU_DISPB_BCLK
|
||||
145 MX35_PAD_NFRE_B__GPIO2_19
|
||||
146 MX35_PAD_NFRE_B__ARM11P_TOP_TRACE_1
|
||||
147 MX35_PAD_NFALE__EMI_NANDF_ALE
|
||||
148 MX35_PAD_NFALE__USB_TOP_USBH2_STP
|
||||
149 MX35_PAD_NFALE__IPU_DISPB_CS0
|
||||
150 MX35_PAD_NFALE__GPIO2_20
|
||||
151 MX35_PAD_NFALE__ARM11P_TOP_TRACE_2
|
||||
152 MX35_PAD_NFCLE__EMI_NANDF_CLE
|
||||
153 MX35_PAD_NFCLE__USB_TOP_USBH2_NXT
|
||||
154 MX35_PAD_NFCLE__IPU_DISPB_PAR_RS
|
||||
155 MX35_PAD_NFCLE__GPIO2_21
|
||||
156 MX35_PAD_NFCLE__ARM11P_TOP_TRACE_3
|
||||
157 MX35_PAD_NFWP_B__EMI_NANDF_WP_B
|
||||
158 MX35_PAD_NFWP_B__USB_TOP_USBH2_DATA_7
|
||||
159 MX35_PAD_NFWP_B__IPU_DISPB_WR
|
||||
160 MX35_PAD_NFWP_B__GPIO2_22
|
||||
161 MX35_PAD_NFWP_B__ARM11P_TOP_TRCTL
|
||||
162 MX35_PAD_NFRB__EMI_NANDF_RB
|
||||
163 MX35_PAD_NFRB__IPU_DISPB_RD
|
||||
164 MX35_PAD_NFRB__GPIO2_23
|
||||
165 MX35_PAD_NFRB__ARM11P_TOP_TRCLK
|
||||
166 MX35_PAD_D15__EMI_EIM_D_15
|
||||
167 MX35_PAD_D14__EMI_EIM_D_14
|
||||
168 MX35_PAD_D13__EMI_EIM_D_13
|
||||
169 MX35_PAD_D12__EMI_EIM_D_12
|
||||
170 MX35_PAD_D11__EMI_EIM_D_11
|
||||
171 MX35_PAD_D10__EMI_EIM_D_10
|
||||
172 MX35_PAD_D9__EMI_EIM_D_9
|
||||
173 MX35_PAD_D8__EMI_EIM_D_8
|
||||
174 MX35_PAD_D7__EMI_EIM_D_7
|
||||
175 MX35_PAD_D6__EMI_EIM_D_6
|
||||
176 MX35_PAD_D5__EMI_EIM_D_5
|
||||
177 MX35_PAD_D4__EMI_EIM_D_4
|
||||
178 MX35_PAD_D3__EMI_EIM_D_3
|
||||
179 MX35_PAD_D2__EMI_EIM_D_2
|
||||
180 MX35_PAD_D1__EMI_EIM_D_1
|
||||
181 MX35_PAD_D0__EMI_EIM_D_0
|
||||
182 MX35_PAD_CSI_D8__IPU_CSI_D_8
|
||||
183 MX35_PAD_CSI_D8__KPP_COL_0
|
||||
184 MX35_PAD_CSI_D8__GPIO1_20
|
||||
185 MX35_PAD_CSI_D8__ARM11P_TOP_EVNTBUS_13
|
||||
186 MX35_PAD_CSI_D9__IPU_CSI_D_9
|
||||
187 MX35_PAD_CSI_D9__KPP_COL_1
|
||||
188 MX35_PAD_CSI_D9__GPIO1_21
|
||||
189 MX35_PAD_CSI_D9__ARM11P_TOP_EVNTBUS_14
|
||||
190 MX35_PAD_CSI_D10__IPU_CSI_D_10
|
||||
191 MX35_PAD_CSI_D10__KPP_COL_2
|
||||
192 MX35_PAD_CSI_D10__GPIO1_22
|
||||
193 MX35_PAD_CSI_D10__ARM11P_TOP_EVNTBUS_15
|
||||
194 MX35_PAD_CSI_D11__IPU_CSI_D_11
|
||||
195 MX35_PAD_CSI_D11__KPP_COL_3
|
||||
196 MX35_PAD_CSI_D11__GPIO1_23
|
||||
197 MX35_PAD_CSI_D12__IPU_CSI_D_12
|
||||
198 MX35_PAD_CSI_D12__KPP_ROW_0
|
||||
199 MX35_PAD_CSI_D12__GPIO1_24
|
||||
200 MX35_PAD_CSI_D13__IPU_CSI_D_13
|
||||
201 MX35_PAD_CSI_D13__KPP_ROW_1
|
||||
202 MX35_PAD_CSI_D13__GPIO1_25
|
||||
203 MX35_PAD_CSI_D14__IPU_CSI_D_14
|
||||
204 MX35_PAD_CSI_D14__KPP_ROW_2
|
||||
205 MX35_PAD_CSI_D14__GPIO1_26
|
||||
206 MX35_PAD_CSI_D15__IPU_CSI_D_15
|
||||
207 MX35_PAD_CSI_D15__KPP_ROW_3
|
||||
208 MX35_PAD_CSI_D15__GPIO1_27
|
||||
209 MX35_PAD_CSI_MCLK__IPU_CSI_MCLK
|
||||
210 MX35_PAD_CSI_MCLK__GPIO1_28
|
||||
211 MX35_PAD_CSI_VSYNC__IPU_CSI_VSYNC
|
||||
212 MX35_PAD_CSI_VSYNC__GPIO1_29
|
||||
213 MX35_PAD_CSI_HSYNC__IPU_CSI_HSYNC
|
||||
214 MX35_PAD_CSI_HSYNC__GPIO1_30
|
||||
215 MX35_PAD_CSI_PIXCLK__IPU_CSI_PIXCLK
|
||||
216 MX35_PAD_CSI_PIXCLK__GPIO1_31
|
||||
217 MX35_PAD_I2C1_CLK__I2C1_SCL
|
||||
218 MX35_PAD_I2C1_CLK__GPIO2_24
|
||||
219 MX35_PAD_I2C1_CLK__CCM_USB_BYP_CLK
|
||||
220 MX35_PAD_I2C1_DAT__I2C1_SDA
|
||||
221 MX35_PAD_I2C1_DAT__GPIO2_25
|
||||
222 MX35_PAD_I2C2_CLK__I2C2_SCL
|
||||
223 MX35_PAD_I2C2_CLK__CAN1_TXCAN
|
||||
224 MX35_PAD_I2C2_CLK__USB_TOP_USBH2_PWR
|
||||
225 MX35_PAD_I2C2_CLK__GPIO2_26
|
||||
226 MX35_PAD_I2C2_CLK__SDMA_DEBUG_BUS_DEVICE_2
|
||||
227 MX35_PAD_I2C2_DAT__I2C2_SDA
|
||||
228 MX35_PAD_I2C2_DAT__CAN1_RXCAN
|
||||
229 MX35_PAD_I2C2_DAT__USB_TOP_USBH2_OC
|
||||
230 MX35_PAD_I2C2_DAT__GPIO2_27
|
||||
231 MX35_PAD_I2C2_DAT__SDMA_DEBUG_BUS_DEVICE_3
|
||||
232 MX35_PAD_STXD4__AUDMUX_AUD4_TXD
|
||||
233 MX35_PAD_STXD4__GPIO2_28
|
||||
234 MX35_PAD_STXD4__ARM11P_TOP_ARM_COREASID0
|
||||
235 MX35_PAD_SRXD4__AUDMUX_AUD4_RXD
|
||||
236 MX35_PAD_SRXD4__GPIO2_29
|
||||
237 MX35_PAD_SRXD4__ARM11P_TOP_ARM_COREASID1
|
||||
238 MX35_PAD_SCK4__AUDMUX_AUD4_TXC
|
||||
239 MX35_PAD_SCK4__GPIO2_30
|
||||
240 MX35_PAD_SCK4__ARM11P_TOP_ARM_COREASID2
|
||||
241 MX35_PAD_STXFS4__AUDMUX_AUD4_TXFS
|
||||
242 MX35_PAD_STXFS4__GPIO2_31
|
||||
243 MX35_PAD_STXFS4__ARM11P_TOP_ARM_COREASID3
|
||||
244 MX35_PAD_STXD5__AUDMUX_AUD5_TXD
|
||||
245 MX35_PAD_STXD5__SPDIF_SPDIF_OUT1
|
||||
246 MX35_PAD_STXD5__CSPI2_MOSI
|
||||
247 MX35_PAD_STXD5__GPIO1_0
|
||||
248 MX35_PAD_STXD5__ARM11P_TOP_ARM_COREASID4
|
||||
249 MX35_PAD_SRXD5__AUDMUX_AUD5_RXD
|
||||
250 MX35_PAD_SRXD5__SPDIF_SPDIF_IN1
|
||||
251 MX35_PAD_SRXD5__CSPI2_MISO
|
||||
252 MX35_PAD_SRXD5__GPIO1_1
|
||||
253 MX35_PAD_SRXD5__ARM11P_TOP_ARM_COREASID5
|
||||
254 MX35_PAD_SCK5__AUDMUX_AUD5_TXC
|
||||
255 MX35_PAD_SCK5__SPDIF_SPDIF_EXTCLK
|
||||
256 MX35_PAD_SCK5__CSPI2_SCLK
|
||||
257 MX35_PAD_SCK5__GPIO1_2
|
||||
258 MX35_PAD_SCK5__ARM11P_TOP_ARM_COREASID6
|
||||
259 MX35_PAD_STXFS5__AUDMUX_AUD5_TXFS
|
||||
260 MX35_PAD_STXFS5__CSPI2_RDY
|
||||
261 MX35_PAD_STXFS5__GPIO1_3
|
||||
262 MX35_PAD_STXFS5__ARM11P_TOP_ARM_COREASID7
|
||||
263 MX35_PAD_SCKR__ESAI_SCKR
|
||||
264 MX35_PAD_SCKR__GPIO1_4
|
||||
265 MX35_PAD_SCKR__ARM11P_TOP_EVNTBUS_10
|
||||
266 MX35_PAD_FSR__ESAI_FSR
|
||||
267 MX35_PAD_FSR__GPIO1_5
|
||||
268 MX35_PAD_FSR__ARM11P_TOP_EVNTBUS_11
|
||||
269 MX35_PAD_HCKR__ESAI_HCKR
|
||||
270 MX35_PAD_HCKR__AUDMUX_AUD5_RXFS
|
||||
271 MX35_PAD_HCKR__CSPI2_SS0
|
||||
272 MX35_PAD_HCKR__IPU_FLASH_STROBE
|
||||
273 MX35_PAD_HCKR__GPIO1_6
|
||||
274 MX35_PAD_HCKR__ARM11P_TOP_EVNTBUS_12
|
||||
275 MX35_PAD_SCKT__ESAI_SCKT
|
||||
276 MX35_PAD_SCKT__GPIO1_7
|
||||
277 MX35_PAD_SCKT__IPU_CSI_D_0
|
||||
278 MX35_PAD_SCKT__KPP_ROW_2
|
||||
279 MX35_PAD_FST__ESAI_FST
|
||||
280 MX35_PAD_FST__GPIO1_8
|
||||
281 MX35_PAD_FST__IPU_CSI_D_1
|
||||
282 MX35_PAD_FST__KPP_ROW_3
|
||||
283 MX35_PAD_HCKT__ESAI_HCKT
|
||||
284 MX35_PAD_HCKT__AUDMUX_AUD5_RXC
|
||||
285 MX35_PAD_HCKT__GPIO1_9
|
||||
286 MX35_PAD_HCKT__IPU_CSI_D_2
|
||||
287 MX35_PAD_HCKT__KPP_COL_3
|
||||
288 MX35_PAD_TX5_RX0__ESAI_TX5_RX0
|
||||
289 MX35_PAD_TX5_RX0__AUDMUX_AUD4_RXC
|
||||
290 MX35_PAD_TX5_RX0__CSPI2_SS2
|
||||
291 MX35_PAD_TX5_RX0__CAN2_TXCAN
|
||||
292 MX35_PAD_TX5_RX0__UART2_DTR
|
||||
293 MX35_PAD_TX5_RX0__GPIO1_10
|
||||
294 MX35_PAD_TX5_RX0__EMI_M3IF_CHOSEN_MASTER_0
|
||||
295 MX35_PAD_TX4_RX1__ESAI_TX4_RX1
|
||||
296 MX35_PAD_TX4_RX1__AUDMUX_AUD4_RXFS
|
||||
297 MX35_PAD_TX4_RX1__CSPI2_SS3
|
||||
298 MX35_PAD_TX4_RX1__CAN2_RXCAN
|
||||
299 MX35_PAD_TX4_RX1__UART2_DSR
|
||||
300 MX35_PAD_TX4_RX1__GPIO1_11
|
||||
301 MX35_PAD_TX4_RX1__IPU_CSI_D_3
|
||||
302 MX35_PAD_TX4_RX1__KPP_ROW_0
|
||||
303 MX35_PAD_TX3_RX2__ESAI_TX3_RX2
|
||||
304 MX35_PAD_TX3_RX2__I2C3_SCL
|
||||
305 MX35_PAD_TX3_RX2__EMI_NANDF_CE1
|
||||
306 MX35_PAD_TX3_RX2__GPIO1_12
|
||||
307 MX35_PAD_TX3_RX2__IPU_CSI_D_4
|
||||
308 MX35_PAD_TX3_RX2__KPP_ROW_1
|
||||
309 MX35_PAD_TX2_RX3__ESAI_TX2_RX3
|
||||
310 MX35_PAD_TX2_RX3__I2C3_SDA
|
||||
311 MX35_PAD_TX2_RX3__EMI_NANDF_CE2
|
||||
312 MX35_PAD_TX2_RX3__GPIO1_13
|
||||
313 MX35_PAD_TX2_RX3__IPU_CSI_D_5
|
||||
314 MX35_PAD_TX2_RX3__KPP_COL_0
|
||||
315 MX35_PAD_TX1__ESAI_TX1
|
||||
316 MX35_PAD_TX1__CCM_PMIC_RDY
|
||||
317 MX35_PAD_TX1__CSPI1_SS2
|
||||
318 MX35_PAD_TX1__EMI_NANDF_CE3
|
||||
319 MX35_PAD_TX1__UART2_RI
|
||||
320 MX35_PAD_TX1__GPIO1_14
|
||||
321 MX35_PAD_TX1__IPU_CSI_D_6
|
||||
322 MX35_PAD_TX1__KPP_COL_1
|
||||
323 MX35_PAD_TX0__ESAI_TX0
|
||||
324 MX35_PAD_TX0__SPDIF_SPDIF_EXTCLK
|
||||
325 MX35_PAD_TX0__CSPI1_SS3
|
||||
326 MX35_PAD_TX0__EMI_DTACK_B
|
||||
327 MX35_PAD_TX0__UART2_DCD
|
||||
328 MX35_PAD_TX0__GPIO1_15
|
||||
329 MX35_PAD_TX0__IPU_CSI_D_7
|
||||
330 MX35_PAD_TX0__KPP_COL_2
|
||||
331 MX35_PAD_CSPI1_MOSI__CSPI1_MOSI
|
||||
332 MX35_PAD_CSPI1_MOSI__GPIO1_16
|
||||
333 MX35_PAD_CSPI1_MOSI__ECT_CTI_TRIG_OUT1_2
|
||||
334 MX35_PAD_CSPI1_MISO__CSPI1_MISO
|
||||
335 MX35_PAD_CSPI1_MISO__GPIO1_17
|
||||
336 MX35_PAD_CSPI1_MISO__ECT_CTI_TRIG_OUT1_3
|
||||
337 MX35_PAD_CSPI1_SS0__CSPI1_SS0
|
||||
338 MX35_PAD_CSPI1_SS0__OWIRE_LINE
|
||||
339 MX35_PAD_CSPI1_SS0__CSPI2_SS3
|
||||
340 MX35_PAD_CSPI1_SS0__GPIO1_18
|
||||
341 MX35_PAD_CSPI1_SS0__ECT_CTI_TRIG_OUT1_4
|
||||
342 MX35_PAD_CSPI1_SS1__CSPI1_SS1
|
||||
343 MX35_PAD_CSPI1_SS1__PWM_PWMO
|
||||
344 MX35_PAD_CSPI1_SS1__CCM_CLK32K
|
||||
345 MX35_PAD_CSPI1_SS1__GPIO1_19
|
||||
346 MX35_PAD_CSPI1_SS1__IPU_DIAGB_29
|
||||
347 MX35_PAD_CSPI1_SS1__ECT_CTI_TRIG_OUT1_5
|
||||
348 MX35_PAD_CSPI1_SCLK__CSPI1_SCLK
|
||||
349 MX35_PAD_CSPI1_SCLK__GPIO3_4
|
||||
350 MX35_PAD_CSPI1_SCLK__IPU_DIAGB_30
|
||||
351 MX35_PAD_CSPI1_SCLK__EMI_M3IF_CHOSEN_MASTER_1
|
||||
352 MX35_PAD_CSPI1_SPI_RDY__CSPI1_RDY
|
||||
353 MX35_PAD_CSPI1_SPI_RDY__GPIO3_5
|
||||
354 MX35_PAD_CSPI1_SPI_RDY__IPU_DIAGB_31
|
||||
355 MX35_PAD_CSPI1_SPI_RDY__EMI_M3IF_CHOSEN_MASTER_2
|
||||
356 MX35_PAD_RXD1__UART1_RXD_MUX
|
||||
357 MX35_PAD_RXD1__CSPI2_MOSI
|
||||
358 MX35_PAD_RXD1__KPP_COL_4
|
||||
359 MX35_PAD_RXD1__GPIO3_6
|
||||
360 MX35_PAD_RXD1__ARM11P_TOP_EVNTBUS_16
|
||||
361 MX35_PAD_TXD1__UART1_TXD_MUX
|
||||
362 MX35_PAD_TXD1__CSPI2_MISO
|
||||
363 MX35_PAD_TXD1__KPP_COL_5
|
||||
364 MX35_PAD_TXD1__GPIO3_7
|
||||
365 MX35_PAD_TXD1__ARM11P_TOP_EVNTBUS_17
|
||||
366 MX35_PAD_RTS1__UART1_RTS
|
||||
367 MX35_PAD_RTS1__CSPI2_SCLK
|
||||
368 MX35_PAD_RTS1__I2C3_SCL
|
||||
369 MX35_PAD_RTS1__IPU_CSI_D_0
|
||||
370 MX35_PAD_RTS1__KPP_COL_6
|
||||
371 MX35_PAD_RTS1__GPIO3_8
|
||||
372 MX35_PAD_RTS1__EMI_NANDF_CE1
|
||||
373 MX35_PAD_RTS1__ARM11P_TOP_EVNTBUS_18
|
||||
374 MX35_PAD_CTS1__UART1_CTS
|
||||
375 MX35_PAD_CTS1__CSPI2_RDY
|
||||
376 MX35_PAD_CTS1__I2C3_SDA
|
||||
377 MX35_PAD_CTS1__IPU_CSI_D_1
|
||||
378 MX35_PAD_CTS1__KPP_COL_7
|
||||
379 MX35_PAD_CTS1__GPIO3_9
|
||||
380 MX35_PAD_CTS1__EMI_NANDF_CE2
|
||||
381 MX35_PAD_CTS1__ARM11P_TOP_EVNTBUS_19
|
||||
382 MX35_PAD_RXD2__UART2_RXD_MUX
|
||||
383 MX35_PAD_RXD2__KPP_ROW_4
|
||||
384 MX35_PAD_RXD2__GPIO3_10
|
||||
385 MX35_PAD_TXD2__UART2_TXD_MUX
|
||||
386 MX35_PAD_TXD2__SPDIF_SPDIF_EXTCLK
|
||||
387 MX35_PAD_TXD2__KPP_ROW_5
|
||||
388 MX35_PAD_TXD2__GPIO3_11
|
||||
389 MX35_PAD_RTS2__UART2_RTS
|
||||
390 MX35_PAD_RTS2__SPDIF_SPDIF_IN1
|
||||
391 MX35_PAD_RTS2__CAN2_RXCAN
|
||||
392 MX35_PAD_RTS2__IPU_CSI_D_2
|
||||
393 MX35_PAD_RTS2__KPP_ROW_6
|
||||
394 MX35_PAD_RTS2__GPIO3_12
|
||||
395 MX35_PAD_RTS2__AUDMUX_AUD5_RXC
|
||||
396 MX35_PAD_RTS2__UART3_RXD_MUX
|
||||
397 MX35_PAD_CTS2__UART2_CTS
|
||||
398 MX35_PAD_CTS2__SPDIF_SPDIF_OUT1
|
||||
399 MX35_PAD_CTS2__CAN2_TXCAN
|
||||
400 MX35_PAD_CTS2__IPU_CSI_D_3
|
||||
401 MX35_PAD_CTS2__KPP_ROW_7
|
||||
402 MX35_PAD_CTS2__GPIO3_13
|
||||
403 MX35_PAD_CTS2__AUDMUX_AUD5_RXFS
|
||||
404 MX35_PAD_CTS2__UART3_TXD_MUX
|
||||
405 MX35_PAD_RTCK__ARM11P_TOP_RTCK
|
||||
406 MX35_PAD_TCK__SJC_TCK
|
||||
407 MX35_PAD_TMS__SJC_TMS
|
||||
408 MX35_PAD_TDI__SJC_TDI
|
||||
409 MX35_PAD_TDO__SJC_TDO
|
||||
410 MX35_PAD_TRSTB__SJC_TRSTB
|
||||
411 MX35_PAD_DE_B__SJC_DE_B
|
||||
412 MX35_PAD_SJC_MOD__SJC_MOD
|
||||
413 MX35_PAD_USBOTG_PWR__USB_TOP_USBOTG_PWR
|
||||
414 MX35_PAD_USBOTG_PWR__USB_TOP_USBH2_PWR
|
||||
415 MX35_PAD_USBOTG_PWR__GPIO3_14
|
||||
416 MX35_PAD_USBOTG_OC__USB_TOP_USBOTG_OC
|
||||
417 MX35_PAD_USBOTG_OC__USB_TOP_USBH2_OC
|
||||
418 MX35_PAD_USBOTG_OC__GPIO3_15
|
||||
419 MX35_PAD_LD0__IPU_DISPB_DAT_0
|
||||
420 MX35_PAD_LD0__GPIO2_0
|
||||
421 MX35_PAD_LD0__SDMA_SDMA_DEBUG_PC_0
|
||||
422 MX35_PAD_LD1__IPU_DISPB_DAT_1
|
||||
423 MX35_PAD_LD1__GPIO2_1
|
||||
424 MX35_PAD_LD1__SDMA_SDMA_DEBUG_PC_1
|
||||
425 MX35_PAD_LD2__IPU_DISPB_DAT_2
|
||||
426 MX35_PAD_LD2__GPIO2_2
|
||||
427 MX35_PAD_LD2__SDMA_SDMA_DEBUG_PC_2
|
||||
428 MX35_PAD_LD3__IPU_DISPB_DAT_3
|
||||
429 MX35_PAD_LD3__GPIO2_3
|
||||
430 MX35_PAD_LD3__SDMA_SDMA_DEBUG_PC_3
|
||||
431 MX35_PAD_LD4__IPU_DISPB_DAT_4
|
||||
432 MX35_PAD_LD4__GPIO2_4
|
||||
433 MX35_PAD_LD4__SDMA_SDMA_DEBUG_PC_4
|
||||
434 MX35_PAD_LD5__IPU_DISPB_DAT_5
|
||||
435 MX35_PAD_LD5__GPIO2_5
|
||||
436 MX35_PAD_LD5__SDMA_SDMA_DEBUG_PC_5
|
||||
437 MX35_PAD_LD6__IPU_DISPB_DAT_6
|
||||
438 MX35_PAD_LD6__GPIO2_6
|
||||
439 MX35_PAD_LD6__SDMA_SDMA_DEBUG_PC_6
|
||||
440 MX35_PAD_LD7__IPU_DISPB_DAT_7
|
||||
441 MX35_PAD_LD7__GPIO2_7
|
||||
442 MX35_PAD_LD7__SDMA_SDMA_DEBUG_PC_7
|
||||
443 MX35_PAD_LD8__IPU_DISPB_DAT_8
|
||||
444 MX35_PAD_LD8__GPIO2_8
|
||||
445 MX35_PAD_LD8__SDMA_SDMA_DEBUG_PC_8
|
||||
446 MX35_PAD_LD9__IPU_DISPB_DAT_9
|
||||
447 MX35_PAD_LD9__GPIO2_9
|
||||
448 MX35_PAD_LD9__SDMA_SDMA_DEBUG_PC_9
|
||||
449 MX35_PAD_LD10__IPU_DISPB_DAT_10
|
||||
450 MX35_PAD_LD10__GPIO2_10
|
||||
451 MX35_PAD_LD10__SDMA_SDMA_DEBUG_PC_10
|
||||
452 MX35_PAD_LD11__IPU_DISPB_DAT_11
|
||||
453 MX35_PAD_LD11__GPIO2_11
|
||||
454 MX35_PAD_LD11__SDMA_SDMA_DEBUG_PC_11
|
||||
455 MX35_PAD_LD11__ARM11P_TOP_TRACE_4
|
||||
456 MX35_PAD_LD12__IPU_DISPB_DAT_12
|
||||
457 MX35_PAD_LD12__GPIO2_12
|
||||
458 MX35_PAD_LD12__SDMA_SDMA_DEBUG_PC_12
|
||||
459 MX35_PAD_LD12__ARM11P_TOP_TRACE_5
|
||||
460 MX35_PAD_LD13__IPU_DISPB_DAT_13
|
||||
461 MX35_PAD_LD13__GPIO2_13
|
||||
462 MX35_PAD_LD13__SDMA_SDMA_DEBUG_PC_13
|
||||
463 MX35_PAD_LD13__ARM11P_TOP_TRACE_6
|
||||
464 MX35_PAD_LD14__IPU_DISPB_DAT_14
|
||||
465 MX35_PAD_LD14__GPIO2_14
|
||||
466 MX35_PAD_LD14__SDMA_SDMA_DEBUG_EVENT_CHANNEL_0
|
||||
467 MX35_PAD_LD14__ARM11P_TOP_TRACE_7
|
||||
468 MX35_PAD_LD15__IPU_DISPB_DAT_15
|
||||
469 MX35_PAD_LD15__GPIO2_15
|
||||
470 MX35_PAD_LD15__SDMA_SDMA_DEBUG_EVENT_CHANNEL_1
|
||||
471 MX35_PAD_LD15__ARM11P_TOP_TRACE_8
|
||||
472 MX35_PAD_LD16__IPU_DISPB_DAT_16
|
||||
473 MX35_PAD_LD16__IPU_DISPB_D12_VSYNC
|
||||
474 MX35_PAD_LD16__GPIO2_16
|
||||
475 MX35_PAD_LD16__SDMA_SDMA_DEBUG_EVENT_CHANNEL_2
|
||||
476 MX35_PAD_LD16__ARM11P_TOP_TRACE_9
|
||||
477 MX35_PAD_LD17__IPU_DISPB_DAT_17
|
||||
478 MX35_PAD_LD17__IPU_DISPB_CS2
|
||||
479 MX35_PAD_LD17__GPIO2_17
|
||||
480 MX35_PAD_LD17__SDMA_SDMA_DEBUG_EVENT_CHANNEL_3
|
||||
481 MX35_PAD_LD17__ARM11P_TOP_TRACE_10
|
||||
482 MX35_PAD_LD18__IPU_DISPB_DAT_18
|
||||
483 MX35_PAD_LD18__IPU_DISPB_D0_VSYNC
|
||||
484 MX35_PAD_LD18__IPU_DISPB_D12_VSYNC
|
||||
485 MX35_PAD_LD18__ESDHC3_CMD
|
||||
486 MX35_PAD_LD18__USB_TOP_USBOTG_DATA_3
|
||||
487 MX35_PAD_LD18__GPIO3_24
|
||||
488 MX35_PAD_LD18__SDMA_SDMA_DEBUG_EVENT_CHANNEL_4
|
||||
489 MX35_PAD_LD18__ARM11P_TOP_TRACE_11
|
||||
490 MX35_PAD_LD19__IPU_DISPB_DAT_19
|
||||
491 MX35_PAD_LD19__IPU_DISPB_BCLK
|
||||
492 MX35_PAD_LD19__IPU_DISPB_CS1
|
||||
493 MX35_PAD_LD19__ESDHC3_CLK
|
||||
494 MX35_PAD_LD19__USB_TOP_USBOTG_DIR
|
||||
495 MX35_PAD_LD19__GPIO3_25
|
||||
496 MX35_PAD_LD19__SDMA_SDMA_DEBUG_EVENT_CHANNEL_5
|
||||
497 MX35_PAD_LD19__ARM11P_TOP_TRACE_12
|
||||
498 MX35_PAD_LD20__IPU_DISPB_DAT_20
|
||||
499 MX35_PAD_LD20__IPU_DISPB_CS0
|
||||
500 MX35_PAD_LD20__IPU_DISPB_SD_CLK
|
||||
501 MX35_PAD_LD20__ESDHC3_DAT0
|
||||
502 MX35_PAD_LD20__GPIO3_26
|
||||
503 MX35_PAD_LD20__SDMA_SDMA_DEBUG_CORE_STATUS_3
|
||||
504 MX35_PAD_LD20__ARM11P_TOP_TRACE_13
|
||||
505 MX35_PAD_LD21__IPU_DISPB_DAT_21
|
||||
506 MX35_PAD_LD21__IPU_DISPB_PAR_RS
|
||||
507 MX35_PAD_LD21__IPU_DISPB_SER_RS
|
||||
508 MX35_PAD_LD21__ESDHC3_DAT1
|
||||
509 MX35_PAD_LD21__USB_TOP_USBOTG_STP
|
||||
510 MX35_PAD_LD21__GPIO3_27
|
||||
511 MX35_PAD_LD21__SDMA_DEBUG_EVENT_CHANNEL_SEL
|
||||
512 MX35_PAD_LD21__ARM11P_TOP_TRACE_14
|
||||
513 MX35_PAD_LD22__IPU_DISPB_DAT_22
|
||||
514 MX35_PAD_LD22__IPU_DISPB_WR
|
||||
515 MX35_PAD_LD22__IPU_DISPB_SD_D_I
|
||||
516 MX35_PAD_LD22__ESDHC3_DAT2
|
||||
517 MX35_PAD_LD22__USB_TOP_USBOTG_NXT
|
||||
518 MX35_PAD_LD22__GPIO3_28
|
||||
519 MX35_PAD_LD22__SDMA_DEBUG_BUS_ERROR
|
||||
520 MX35_PAD_LD22__ARM11P_TOP_TRCTL
|
||||
521 MX35_PAD_LD23__IPU_DISPB_DAT_23
|
||||
522 MX35_PAD_LD23__IPU_DISPB_RD
|
||||
523 MX35_PAD_LD23__IPU_DISPB_SD_D_IO
|
||||
524 MX35_PAD_LD23__ESDHC3_DAT3
|
||||
525 MX35_PAD_LD23__USB_TOP_USBOTG_DATA_7
|
||||
526 MX35_PAD_LD23__GPIO3_29
|
||||
527 MX35_PAD_LD23__SDMA_DEBUG_MATCHED_DMBUS
|
||||
528 MX35_PAD_LD23__ARM11P_TOP_TRCLK
|
||||
529 MX35_PAD_D3_HSYNC__IPU_DISPB_D3_HSYNC
|
||||
530 MX35_PAD_D3_HSYNC__IPU_DISPB_SD_D_IO
|
||||
531 MX35_PAD_D3_HSYNC__GPIO3_30
|
||||
532 MX35_PAD_D3_HSYNC__SDMA_DEBUG_RTBUFFER_WRITE
|
||||
533 MX35_PAD_D3_HSYNC__ARM11P_TOP_TRACE_15
|
||||
534 MX35_PAD_D3_FPSHIFT__IPU_DISPB_D3_CLK
|
||||
535 MX35_PAD_D3_FPSHIFT__IPU_DISPB_SD_CLK
|
||||
536 MX35_PAD_D3_FPSHIFT__GPIO3_31
|
||||
537 MX35_PAD_D3_FPSHIFT__SDMA_SDMA_DEBUG_CORE_STATUS_0
|
||||
538 MX35_PAD_D3_FPSHIFT__ARM11P_TOP_TRACE_16
|
||||
539 MX35_PAD_D3_DRDY__IPU_DISPB_D3_DRDY
|
||||
540 MX35_PAD_D3_DRDY__IPU_DISPB_SD_D_O
|
||||
541 MX35_PAD_D3_DRDY__GPIO1_0
|
||||
542 MX35_PAD_D3_DRDY__SDMA_SDMA_DEBUG_CORE_STATUS_1
|
||||
543 MX35_PAD_D3_DRDY__ARM11P_TOP_TRACE_17
|
||||
544 MX35_PAD_CONTRAST__IPU_DISPB_CONTR
|
||||
545 MX35_PAD_CONTRAST__GPIO1_1
|
||||
546 MX35_PAD_CONTRAST__SDMA_SDMA_DEBUG_CORE_STATUS_2
|
||||
547 MX35_PAD_CONTRAST__ARM11P_TOP_TRACE_18
|
||||
548 MX35_PAD_D3_VSYNC__IPU_DISPB_D3_VSYNC
|
||||
549 MX35_PAD_D3_VSYNC__IPU_DISPB_CS1
|
||||
550 MX35_PAD_D3_VSYNC__GPIO1_2
|
||||
551 MX35_PAD_D3_VSYNC__SDMA_DEBUG_YIELD
|
||||
552 MX35_PAD_D3_VSYNC__ARM11P_TOP_TRACE_19
|
||||
553 MX35_PAD_D3_REV__IPU_DISPB_D3_REV
|
||||
554 MX35_PAD_D3_REV__IPU_DISPB_SER_RS
|
||||
555 MX35_PAD_D3_REV__GPIO1_3
|
||||
556 MX35_PAD_D3_REV__SDMA_DEBUG_BUS_RWB
|
||||
557 MX35_PAD_D3_REV__ARM11P_TOP_TRACE_20
|
||||
558 MX35_PAD_D3_CLS__IPU_DISPB_D3_CLS
|
||||
559 MX35_PAD_D3_CLS__IPU_DISPB_CS2
|
||||
560 MX35_PAD_D3_CLS__GPIO1_4
|
||||
561 MX35_PAD_D3_CLS__SDMA_DEBUG_BUS_DEVICE_0
|
||||
562 MX35_PAD_D3_CLS__ARM11P_TOP_TRACE_21
|
||||
563 MX35_PAD_D3_SPL__IPU_DISPB_D3_SPL
|
||||
564 MX35_PAD_D3_SPL__IPU_DISPB_D12_VSYNC
|
||||
565 MX35_PAD_D3_SPL__GPIO1_5
|
||||
566 MX35_PAD_D3_SPL__SDMA_DEBUG_BUS_DEVICE_1
|
||||
567 MX35_PAD_D3_SPL__ARM11P_TOP_TRACE_22
|
||||
568 MX35_PAD_SD1_CMD__ESDHC1_CMD
|
||||
569 MX35_PAD_SD1_CMD__MSHC_SCLK
|
||||
570 MX35_PAD_SD1_CMD__IPU_DISPB_D0_VSYNC
|
||||
571 MX35_PAD_SD1_CMD__USB_TOP_USBOTG_DATA_4
|
||||
572 MX35_PAD_SD1_CMD__GPIO1_6
|
||||
573 MX35_PAD_SD1_CMD__ARM11P_TOP_TRCTL
|
||||
574 MX35_PAD_SD1_CLK__ESDHC1_CLK
|
||||
575 MX35_PAD_SD1_CLK__MSHC_BS
|
||||
576 MX35_PAD_SD1_CLK__IPU_DISPB_BCLK
|
||||
577 MX35_PAD_SD1_CLK__USB_TOP_USBOTG_DATA_5
|
||||
578 MX35_PAD_SD1_CLK__GPIO1_7
|
||||
579 MX35_PAD_SD1_CLK__ARM11P_TOP_TRCLK
|
||||
580 MX35_PAD_SD1_DATA0__ESDHC1_DAT0
|
||||
581 MX35_PAD_SD1_DATA0__MSHC_DATA_0
|
||||
582 MX35_PAD_SD1_DATA0__IPU_DISPB_CS0
|
||||
583 MX35_PAD_SD1_DATA0__USB_TOP_USBOTG_DATA_6
|
||||
584 MX35_PAD_SD1_DATA0__GPIO1_8
|
||||
585 MX35_PAD_SD1_DATA0__ARM11P_TOP_TRACE_23
|
||||
586 MX35_PAD_SD1_DATA1__ESDHC1_DAT1
|
||||
587 MX35_PAD_SD1_DATA1__MSHC_DATA_1
|
||||
588 MX35_PAD_SD1_DATA1__IPU_DISPB_PAR_RS
|
||||
589 MX35_PAD_SD1_DATA1__USB_TOP_USBOTG_DATA_0
|
||||
590 MX35_PAD_SD1_DATA1__GPIO1_9
|
||||
591 MX35_PAD_SD1_DATA1__ARM11P_TOP_TRACE_24
|
||||
592 MX35_PAD_SD1_DATA2__ESDHC1_DAT2
|
||||
593 MX35_PAD_SD1_DATA2__MSHC_DATA_2
|
||||
594 MX35_PAD_SD1_DATA2__IPU_DISPB_WR
|
||||
595 MX35_PAD_SD1_DATA2__USB_TOP_USBOTG_DATA_1
|
||||
596 MX35_PAD_SD1_DATA2__GPIO1_10
|
||||
597 MX35_PAD_SD1_DATA2__ARM11P_TOP_TRACE_25
|
||||
598 MX35_PAD_SD1_DATA3__ESDHC1_DAT3
|
||||
599 MX35_PAD_SD1_DATA3__MSHC_DATA_3
|
||||
600 MX35_PAD_SD1_DATA3__IPU_DISPB_RD
|
||||
601 MX35_PAD_SD1_DATA3__USB_TOP_USBOTG_DATA_2
|
||||
602 MX35_PAD_SD1_DATA3__GPIO1_11
|
||||
603 MX35_PAD_SD1_DATA3__ARM11P_TOP_TRACE_26
|
||||
604 MX35_PAD_SD2_CMD__ESDHC2_CMD
|
||||
605 MX35_PAD_SD2_CMD__I2C3_SCL
|
||||
606 MX35_PAD_SD2_CMD__ESDHC1_DAT4
|
||||
607 MX35_PAD_SD2_CMD__IPU_CSI_D_2
|
||||
608 MX35_PAD_SD2_CMD__USB_TOP_USBH2_DATA_4
|
||||
609 MX35_PAD_SD2_CMD__GPIO2_0
|
||||
610 MX35_PAD_SD2_CMD__SPDIF_SPDIF_OUT1
|
||||
611 MX35_PAD_SD2_CMD__IPU_DISPB_D12_VSYNC
|
||||
612 MX35_PAD_SD2_CLK__ESDHC2_CLK
|
||||
613 MX35_PAD_SD2_CLK__I2C3_SDA
|
||||
614 MX35_PAD_SD2_CLK__ESDHC1_DAT5
|
||||
615 MX35_PAD_SD2_CLK__IPU_CSI_D_3
|
||||
616 MX35_PAD_SD2_CLK__USB_TOP_USBH2_DATA_5
|
||||
617 MX35_PAD_SD2_CLK__GPIO2_1
|
||||
618 MX35_PAD_SD2_CLK__SPDIF_SPDIF_IN1
|
||||
619 MX35_PAD_SD2_CLK__IPU_DISPB_CS2
|
||||
620 MX35_PAD_SD2_DATA0__ESDHC2_DAT0
|
||||
621 MX35_PAD_SD2_DATA0__UART3_RXD_MUX
|
||||
622 MX35_PAD_SD2_DATA0__ESDHC1_DAT6
|
||||
623 MX35_PAD_SD2_DATA0__IPU_CSI_D_4
|
||||
624 MX35_PAD_SD2_DATA0__USB_TOP_USBH2_DATA_6
|
||||
625 MX35_PAD_SD2_DATA0__GPIO2_2
|
||||
626 MX35_PAD_SD2_DATA0__SPDIF_SPDIF_EXTCLK
|
||||
627 MX35_PAD_SD2_DATA1__ESDHC2_DAT1
|
||||
628 MX35_PAD_SD2_DATA1__UART3_TXD_MUX
|
||||
629 MX35_PAD_SD2_DATA1__ESDHC1_DAT7
|
||||
630 MX35_PAD_SD2_DATA1__IPU_CSI_D_5
|
||||
631 MX35_PAD_SD2_DATA1__USB_TOP_USBH2_DATA_0
|
||||
632 MX35_PAD_SD2_DATA1__GPIO2_3
|
||||
633 MX35_PAD_SD2_DATA2__ESDHC2_DAT2
|
||||
634 MX35_PAD_SD2_DATA2__UART3_RTS
|
||||
635 MX35_PAD_SD2_DATA2__CAN1_RXCAN
|
||||
636 MX35_PAD_SD2_DATA2__IPU_CSI_D_6
|
||||
637 MX35_PAD_SD2_DATA2__USB_TOP_USBH2_DATA_1
|
||||
638 MX35_PAD_SD2_DATA2__GPIO2_4
|
||||
639 MX35_PAD_SD2_DATA3__ESDHC2_DAT3
|
||||
640 MX35_PAD_SD2_DATA3__UART3_CTS
|
||||
641 MX35_PAD_SD2_DATA3__CAN1_TXCAN
|
||||
642 MX35_PAD_SD2_DATA3__IPU_CSI_D_7
|
||||
643 MX35_PAD_SD2_DATA3__USB_TOP_USBH2_DATA_2
|
||||
644 MX35_PAD_SD2_DATA3__GPIO2_5
|
||||
645 MX35_PAD_ATA_CS0__ATA_CS0
|
||||
646 MX35_PAD_ATA_CS0__CSPI1_SS3
|
||||
647 MX35_PAD_ATA_CS0__IPU_DISPB_CS1
|
||||
648 MX35_PAD_ATA_CS0__GPIO2_6
|
||||
649 MX35_PAD_ATA_CS0__IPU_DIAGB_0
|
||||
650 MX35_PAD_ATA_CS0__ARM11P_TOP_MAX1_HMASTER_0
|
||||
651 MX35_PAD_ATA_CS1__ATA_CS1
|
||||
652 MX35_PAD_ATA_CS1__IPU_DISPB_CS2
|
||||
653 MX35_PAD_ATA_CS1__CSPI2_SS0
|
||||
654 MX35_PAD_ATA_CS1__GPIO2_7
|
||||
655 MX35_PAD_ATA_CS1__IPU_DIAGB_1
|
||||
656 MX35_PAD_ATA_CS1__ARM11P_TOP_MAX1_HMASTER_1
|
||||
657 MX35_PAD_ATA_DIOR__ATA_DIOR
|
||||
658 MX35_PAD_ATA_DIOR__ESDHC3_DAT0
|
||||
659 MX35_PAD_ATA_DIOR__USB_TOP_USBOTG_DIR
|
||||
660 MX35_PAD_ATA_DIOR__IPU_DISPB_BE0
|
||||
661 MX35_PAD_ATA_DIOR__CSPI2_SS1
|
||||
662 MX35_PAD_ATA_DIOR__GPIO2_8
|
||||
663 MX35_PAD_ATA_DIOR__IPU_DIAGB_2
|
||||
664 MX35_PAD_ATA_DIOR__ARM11P_TOP_MAX1_HMASTER_2
|
||||
665 MX35_PAD_ATA_DIOW__ATA_DIOW
|
||||
666 MX35_PAD_ATA_DIOW__ESDHC3_DAT1
|
||||
667 MX35_PAD_ATA_DIOW__USB_TOP_USBOTG_STP
|
||||
668 MX35_PAD_ATA_DIOW__IPU_DISPB_BE1
|
||||
669 MX35_PAD_ATA_DIOW__CSPI2_MOSI
|
||||
670 MX35_PAD_ATA_DIOW__GPIO2_9
|
||||
671 MX35_PAD_ATA_DIOW__IPU_DIAGB_3
|
||||
672 MX35_PAD_ATA_DIOW__ARM11P_TOP_MAX1_HMASTER_3
|
||||
673 MX35_PAD_ATA_DMACK__ATA_DMACK
|
||||
674 MX35_PAD_ATA_DMACK__ESDHC3_DAT2
|
||||
675 MX35_PAD_ATA_DMACK__USB_TOP_USBOTG_NXT
|
||||
676 MX35_PAD_ATA_DMACK__CSPI2_MISO
|
||||
677 MX35_PAD_ATA_DMACK__GPIO2_10
|
||||
678 MX35_PAD_ATA_DMACK__IPU_DIAGB_4
|
||||
679 MX35_PAD_ATA_DMACK__ARM11P_TOP_MAX0_HMASTER_0
|
||||
680 MX35_PAD_ATA_RESET_B__ATA_RESET_B
|
||||
681 MX35_PAD_ATA_RESET_B__ESDHC3_DAT3
|
||||
682 MX35_PAD_ATA_RESET_B__USB_TOP_USBOTG_DATA_0
|
||||
683 MX35_PAD_ATA_RESET_B__IPU_DISPB_SD_D_O
|
||||
684 MX35_PAD_ATA_RESET_B__CSPI2_RDY
|
||||
685 MX35_PAD_ATA_RESET_B__GPIO2_11
|
||||
686 MX35_PAD_ATA_RESET_B__IPU_DIAGB_5
|
||||
687 MX35_PAD_ATA_RESET_B__ARM11P_TOP_MAX0_HMASTER_1
|
||||
688 MX35_PAD_ATA_IORDY__ATA_IORDY
|
||||
689 MX35_PAD_ATA_IORDY__ESDHC3_DAT4
|
||||
690 MX35_PAD_ATA_IORDY__USB_TOP_USBOTG_DATA_1
|
||||
691 MX35_PAD_ATA_IORDY__IPU_DISPB_SD_D_IO
|
||||
692 MX35_PAD_ATA_IORDY__ESDHC2_DAT4
|
||||
693 MX35_PAD_ATA_IORDY__GPIO2_12
|
||||
694 MX35_PAD_ATA_IORDY__IPU_DIAGB_6
|
||||
695 MX35_PAD_ATA_IORDY__ARM11P_TOP_MAX0_HMASTER_2
|
||||
696 MX35_PAD_ATA_DATA0__ATA_DATA_0
|
||||
697 MX35_PAD_ATA_DATA0__ESDHC3_DAT5
|
||||
698 MX35_PAD_ATA_DATA0__USB_TOP_USBOTG_DATA_2
|
||||
699 MX35_PAD_ATA_DATA0__IPU_DISPB_D12_VSYNC
|
||||
700 MX35_PAD_ATA_DATA0__ESDHC2_DAT5
|
||||
701 MX35_PAD_ATA_DATA0__GPIO2_13
|
||||
702 MX35_PAD_ATA_DATA0__IPU_DIAGB_7
|
||||
703 MX35_PAD_ATA_DATA0__ARM11P_TOP_MAX0_HMASTER_3
|
||||
704 MX35_PAD_ATA_DATA1__ATA_DATA_1
|
||||
705 MX35_PAD_ATA_DATA1__ESDHC3_DAT6
|
||||
706 MX35_PAD_ATA_DATA1__USB_TOP_USBOTG_DATA_3
|
||||
707 MX35_PAD_ATA_DATA1__IPU_DISPB_SD_CLK
|
||||
708 MX35_PAD_ATA_DATA1__ESDHC2_DAT6
|
||||
709 MX35_PAD_ATA_DATA1__GPIO2_14
|
||||
710 MX35_PAD_ATA_DATA1__IPU_DIAGB_8
|
||||
711 MX35_PAD_ATA_DATA1__ARM11P_TOP_TRACE_27
|
||||
712 MX35_PAD_ATA_DATA2__ATA_DATA_2
|
||||
713 MX35_PAD_ATA_DATA2__ESDHC3_DAT7
|
||||
714 MX35_PAD_ATA_DATA2__USB_TOP_USBOTG_DATA_4
|
||||
715 MX35_PAD_ATA_DATA2__IPU_DISPB_SER_RS
|
||||
716 MX35_PAD_ATA_DATA2__ESDHC2_DAT7
|
||||
717 MX35_PAD_ATA_DATA2__GPIO2_15
|
||||
718 MX35_PAD_ATA_DATA2__IPU_DIAGB_9
|
||||
719 MX35_PAD_ATA_DATA2__ARM11P_TOP_TRACE_28
|
||||
720 MX35_PAD_ATA_DATA3__ATA_DATA_3
|
||||
721 MX35_PAD_ATA_DATA3__ESDHC3_CLK
|
||||
722 MX35_PAD_ATA_DATA3__USB_TOP_USBOTG_DATA_5
|
||||
723 MX35_PAD_ATA_DATA3__CSPI2_SCLK
|
||||
724 MX35_PAD_ATA_DATA3__GPIO2_16
|
||||
725 MX35_PAD_ATA_DATA3__IPU_DIAGB_10
|
||||
726 MX35_PAD_ATA_DATA3__ARM11P_TOP_TRACE_29
|
||||
727 MX35_PAD_ATA_DATA4__ATA_DATA_4
|
||||
728 MX35_PAD_ATA_DATA4__ESDHC3_CMD
|
||||
729 MX35_PAD_ATA_DATA4__USB_TOP_USBOTG_DATA_6
|
||||
730 MX35_PAD_ATA_DATA4__GPIO2_17
|
||||
731 MX35_PAD_ATA_DATA4__IPU_DIAGB_11
|
||||
732 MX35_PAD_ATA_DATA4__ARM11P_TOP_TRACE_30
|
||||
733 MX35_PAD_ATA_DATA5__ATA_DATA_5
|
||||
734 MX35_PAD_ATA_DATA5__USB_TOP_USBOTG_DATA_7
|
||||
735 MX35_PAD_ATA_DATA5__GPIO2_18
|
||||
736 MX35_PAD_ATA_DATA5__IPU_DIAGB_12
|
||||
737 MX35_PAD_ATA_DATA5__ARM11P_TOP_TRACE_31
|
||||
738 MX35_PAD_ATA_DATA6__ATA_DATA_6
|
||||
739 MX35_PAD_ATA_DATA6__CAN1_TXCAN
|
||||
740 MX35_PAD_ATA_DATA6__UART1_DTR
|
||||
741 MX35_PAD_ATA_DATA6__AUDMUX_AUD6_TXD
|
||||
742 MX35_PAD_ATA_DATA6__GPIO2_19
|
||||
743 MX35_PAD_ATA_DATA6__IPU_DIAGB_13
|
||||
744 MX35_PAD_ATA_DATA7__ATA_DATA_7
|
||||
745 MX35_PAD_ATA_DATA7__CAN1_RXCAN
|
||||
746 MX35_PAD_ATA_DATA7__UART1_DSR
|
||||
747 MX35_PAD_ATA_DATA7__AUDMUX_AUD6_RXD
|
||||
748 MX35_PAD_ATA_DATA7__GPIO2_20
|
||||
749 MX35_PAD_ATA_DATA7__IPU_DIAGB_14
|
||||
750 MX35_PAD_ATA_DATA8__ATA_DATA_8
|
||||
751 MX35_PAD_ATA_DATA8__UART3_RTS
|
||||
752 MX35_PAD_ATA_DATA8__UART1_RI
|
||||
753 MX35_PAD_ATA_DATA8__AUDMUX_AUD6_TXC
|
||||
754 MX35_PAD_ATA_DATA8__GPIO2_21
|
||||
755 MX35_PAD_ATA_DATA8__IPU_DIAGB_15
|
||||
756 MX35_PAD_ATA_DATA9__ATA_DATA_9
|
||||
757 MX35_PAD_ATA_DATA9__UART3_CTS
|
||||
758 MX35_PAD_ATA_DATA9__UART1_DCD
|
||||
759 MX35_PAD_ATA_DATA9__AUDMUX_AUD6_TXFS
|
||||
760 MX35_PAD_ATA_DATA9__GPIO2_22
|
||||
761 MX35_PAD_ATA_DATA9__IPU_DIAGB_16
|
||||
762 MX35_PAD_ATA_DATA10__ATA_DATA_10
|
||||
763 MX35_PAD_ATA_DATA10__UART3_RXD_MUX
|
||||
764 MX35_PAD_ATA_DATA10__AUDMUX_AUD6_RXC
|
||||
765 MX35_PAD_ATA_DATA10__GPIO2_23
|
||||
766 MX35_PAD_ATA_DATA10__IPU_DIAGB_17
|
||||
767 MX35_PAD_ATA_DATA11__ATA_DATA_11
|
||||
768 MX35_PAD_ATA_DATA11__UART3_TXD_MUX
|
||||
769 MX35_PAD_ATA_DATA11__AUDMUX_AUD6_RXFS
|
||||
770 MX35_PAD_ATA_DATA11__GPIO2_24
|
||||
771 MX35_PAD_ATA_DATA11__IPU_DIAGB_18
|
||||
772 MX35_PAD_ATA_DATA12__ATA_DATA_12
|
||||
773 MX35_PAD_ATA_DATA12__I2C3_SCL
|
||||
774 MX35_PAD_ATA_DATA12__GPIO2_25
|
||||
775 MX35_PAD_ATA_DATA12__IPU_DIAGB_19
|
||||
776 MX35_PAD_ATA_DATA13__ATA_DATA_13
|
||||
777 MX35_PAD_ATA_DATA13__I2C3_SDA
|
||||
778 MX35_PAD_ATA_DATA13__GPIO2_26
|
||||
779 MX35_PAD_ATA_DATA13__IPU_DIAGB_20
|
||||
780 MX35_PAD_ATA_DATA14__ATA_DATA_14
|
||||
781 MX35_PAD_ATA_DATA14__IPU_CSI_D_0
|
||||
782 MX35_PAD_ATA_DATA14__KPP_ROW_0
|
||||
783 MX35_PAD_ATA_DATA14__GPIO2_27
|
||||
784 MX35_PAD_ATA_DATA14__IPU_DIAGB_21
|
||||
785 MX35_PAD_ATA_DATA15__ATA_DATA_15
|
||||
786 MX35_PAD_ATA_DATA15__IPU_CSI_D_1
|
||||
787 MX35_PAD_ATA_DATA15__KPP_ROW_1
|
||||
788 MX35_PAD_ATA_DATA15__GPIO2_28
|
||||
789 MX35_PAD_ATA_DATA15__IPU_DIAGB_22
|
||||
790 MX35_PAD_ATA_INTRQ__ATA_INTRQ
|
||||
791 MX35_PAD_ATA_INTRQ__IPU_CSI_D_2
|
||||
792 MX35_PAD_ATA_INTRQ__KPP_ROW_2
|
||||
793 MX35_PAD_ATA_INTRQ__GPIO2_29
|
||||
794 MX35_PAD_ATA_INTRQ__IPU_DIAGB_23
|
||||
795 MX35_PAD_ATA_BUFF_EN__ATA_BUFFER_EN
|
||||
796 MX35_PAD_ATA_BUFF_EN__IPU_CSI_D_3
|
||||
797 MX35_PAD_ATA_BUFF_EN__KPP_ROW_3
|
||||
798 MX35_PAD_ATA_BUFF_EN__GPIO2_30
|
||||
799 MX35_PAD_ATA_BUFF_EN__IPU_DIAGB_24
|
||||
800 MX35_PAD_ATA_DMARQ__ATA_DMARQ
|
||||
801 MX35_PAD_ATA_DMARQ__IPU_CSI_D_4
|
||||
802 MX35_PAD_ATA_DMARQ__KPP_COL_0
|
||||
803 MX35_PAD_ATA_DMARQ__GPIO2_31
|
||||
804 MX35_PAD_ATA_DMARQ__IPU_DIAGB_25
|
||||
805 MX35_PAD_ATA_DMARQ__ECT_CTI_TRIG_IN1_4
|
||||
806 MX35_PAD_ATA_DA0__ATA_DA_0
|
||||
807 MX35_PAD_ATA_DA0__IPU_CSI_D_5
|
||||
808 MX35_PAD_ATA_DA0__KPP_COL_1
|
||||
809 MX35_PAD_ATA_DA0__GPIO3_0
|
||||
810 MX35_PAD_ATA_DA0__IPU_DIAGB_26
|
||||
811 MX35_PAD_ATA_DA0__ECT_CTI_TRIG_IN1_5
|
||||
812 MX35_PAD_ATA_DA1__ATA_DA_1
|
||||
813 MX35_PAD_ATA_DA1__IPU_CSI_D_6
|
||||
814 MX35_PAD_ATA_DA1__KPP_COL_2
|
||||
815 MX35_PAD_ATA_DA1__GPIO3_1
|
||||
816 MX35_PAD_ATA_DA1__IPU_DIAGB_27
|
||||
817 MX35_PAD_ATA_DA1__ECT_CTI_TRIG_IN1_6
|
||||
818 MX35_PAD_ATA_DA2__ATA_DA_2
|
||||
819 MX35_PAD_ATA_DA2__IPU_CSI_D_7
|
||||
820 MX35_PAD_ATA_DA2__KPP_COL_3
|
||||
821 MX35_PAD_ATA_DA2__GPIO3_2
|
||||
822 MX35_PAD_ATA_DA2__IPU_DIAGB_28
|
||||
823 MX35_PAD_ATA_DA2__ECT_CTI_TRIG_IN1_7
|
||||
824 MX35_PAD_MLB_CLK__MLB_MLBCLK
|
||||
825 MX35_PAD_MLB_CLK__GPIO3_3
|
||||
826 MX35_PAD_MLB_DAT__MLB_MLBDAT
|
||||
827 MX35_PAD_MLB_DAT__GPIO3_4
|
||||
828 MX35_PAD_MLB_SIG__MLB_MLBSIG
|
||||
829 MX35_PAD_MLB_SIG__GPIO3_5
|
||||
830 MX35_PAD_FEC_TX_CLK__FEC_TX_CLK
|
||||
831 MX35_PAD_FEC_TX_CLK__ESDHC1_DAT4
|
||||
832 MX35_PAD_FEC_TX_CLK__UART3_RXD_MUX
|
||||
833 MX35_PAD_FEC_TX_CLK__USB_TOP_USBH2_DIR
|
||||
834 MX35_PAD_FEC_TX_CLK__CSPI2_MOSI
|
||||
835 MX35_PAD_FEC_TX_CLK__GPIO3_6
|
||||
836 MX35_PAD_FEC_TX_CLK__IPU_DISPB_D12_VSYNC
|
||||
837 MX35_PAD_FEC_TX_CLK__ARM11P_TOP_EVNTBUS_0
|
||||
838 MX35_PAD_FEC_RX_CLK__FEC_RX_CLK
|
||||
839 MX35_PAD_FEC_RX_CLK__ESDHC1_DAT5
|
||||
840 MX35_PAD_FEC_RX_CLK__UART3_TXD_MUX
|
||||
841 MX35_PAD_FEC_RX_CLK__USB_TOP_USBH2_STP
|
||||
842 MX35_PAD_FEC_RX_CLK__CSPI2_MISO
|
||||
843 MX35_PAD_FEC_RX_CLK__GPIO3_7
|
||||
844 MX35_PAD_FEC_RX_CLK__IPU_DISPB_SD_D_I
|
||||
845 MX35_PAD_FEC_RX_CLK__ARM11P_TOP_EVNTBUS_1
|
||||
846 MX35_PAD_FEC_RX_DV__FEC_RX_DV
|
||||
847 MX35_PAD_FEC_RX_DV__ESDHC1_DAT6
|
||||
848 MX35_PAD_FEC_RX_DV__UART3_RTS
|
||||
849 MX35_PAD_FEC_RX_DV__USB_TOP_USBH2_NXT
|
||||
850 MX35_PAD_FEC_RX_DV__CSPI2_SCLK
|
||||
851 MX35_PAD_FEC_RX_DV__GPIO3_8
|
||||
852 MX35_PAD_FEC_RX_DV__IPU_DISPB_SD_CLK
|
||||
853 MX35_PAD_FEC_RX_DV__ARM11P_TOP_EVNTBUS_2
|
||||
854 MX35_PAD_FEC_COL__FEC_COL
|
||||
855 MX35_PAD_FEC_COL__ESDHC1_DAT7
|
||||
856 MX35_PAD_FEC_COL__UART3_CTS
|
||||
857 MX35_PAD_FEC_COL__USB_TOP_USBH2_DATA_0
|
||||
858 MX35_PAD_FEC_COL__CSPI2_RDY
|
||||
859 MX35_PAD_FEC_COL__GPIO3_9
|
||||
860 MX35_PAD_FEC_COL__IPU_DISPB_SER_RS
|
||||
861 MX35_PAD_FEC_COL__ARM11P_TOP_EVNTBUS_3
|
||||
862 MX35_PAD_FEC_RDATA0__FEC_RDATA_0
|
||||
863 MX35_PAD_FEC_RDATA0__PWM_PWMO
|
||||
864 MX35_PAD_FEC_RDATA0__UART3_DTR
|
||||
865 MX35_PAD_FEC_RDATA0__USB_TOP_USBH2_DATA_1
|
||||
866 MX35_PAD_FEC_RDATA0__CSPI2_SS0
|
||||
867 MX35_PAD_FEC_RDATA0__GPIO3_10
|
||||
868 MX35_PAD_FEC_RDATA0__IPU_DISPB_CS1
|
||||
869 MX35_PAD_FEC_RDATA0__ARM11P_TOP_EVNTBUS_4
|
||||
870 MX35_PAD_FEC_TDATA0__FEC_TDATA_0
|
||||
871 MX35_PAD_FEC_TDATA0__SPDIF_SPDIF_OUT1
|
||||
872 MX35_PAD_FEC_TDATA0__UART3_DSR
|
||||
873 MX35_PAD_FEC_TDATA0__USB_TOP_USBH2_DATA_2
|
||||
874 MX35_PAD_FEC_TDATA0__CSPI2_SS1
|
||||
875 MX35_PAD_FEC_TDATA0__GPIO3_11
|
||||
876 MX35_PAD_FEC_TDATA0__IPU_DISPB_CS0
|
||||
877 MX35_PAD_FEC_TDATA0__ARM11P_TOP_EVNTBUS_5
|
||||
878 MX35_PAD_FEC_TX_EN__FEC_TX_EN
|
||||
879 MX35_PAD_FEC_TX_EN__SPDIF_SPDIF_IN1
|
||||
880 MX35_PAD_FEC_TX_EN__UART3_RI
|
||||
881 MX35_PAD_FEC_TX_EN__USB_TOP_USBH2_DATA_3
|
||||
882 MX35_PAD_FEC_TX_EN__GPIO3_12
|
||||
883 MX35_PAD_FEC_TX_EN__IPU_DISPB_PAR_RS
|
||||
884 MX35_PAD_FEC_TX_EN__ARM11P_TOP_EVNTBUS_6
|
||||
885 MX35_PAD_FEC_MDC__FEC_MDC
|
||||
886 MX35_PAD_FEC_MDC__CAN2_TXCAN
|
||||
887 MX35_PAD_FEC_MDC__UART3_DCD
|
||||
888 MX35_PAD_FEC_MDC__USB_TOP_USBH2_DATA_4
|
||||
889 MX35_PAD_FEC_MDC__GPIO3_13
|
||||
890 MX35_PAD_FEC_MDC__IPU_DISPB_WR
|
||||
891 MX35_PAD_FEC_MDC__ARM11P_TOP_EVNTBUS_7
|
||||
892 MX35_PAD_FEC_MDIO__FEC_MDIO
|
||||
893 MX35_PAD_FEC_MDIO__CAN2_RXCAN
|
||||
894 MX35_PAD_FEC_MDIO__USB_TOP_USBH2_DATA_5
|
||||
895 MX35_PAD_FEC_MDIO__GPIO3_14
|
||||
896 MX35_PAD_FEC_MDIO__IPU_DISPB_RD
|
||||
897 MX35_PAD_FEC_MDIO__ARM11P_TOP_EVNTBUS_8
|
||||
898 MX35_PAD_FEC_TX_ERR__FEC_TX_ERR
|
||||
899 MX35_PAD_FEC_TX_ERR__OWIRE_LINE
|
||||
900 MX35_PAD_FEC_TX_ERR__SPDIF_SPDIF_EXTCLK
|
||||
901 MX35_PAD_FEC_TX_ERR__USB_TOP_USBH2_DATA_6
|
||||
902 MX35_PAD_FEC_TX_ERR__GPIO3_15
|
||||
903 MX35_PAD_FEC_TX_ERR__IPU_DISPB_D0_VSYNC
|
||||
904 MX35_PAD_FEC_TX_ERR__ARM11P_TOP_EVNTBUS_9
|
||||
905 MX35_PAD_FEC_RX_ERR__FEC_RX_ERR
|
||||
906 MX35_PAD_FEC_RX_ERR__IPU_CSI_D_0
|
||||
907 MX35_PAD_FEC_RX_ERR__USB_TOP_USBH2_DATA_7
|
||||
908 MX35_PAD_FEC_RX_ERR__KPP_COL_4
|
||||
909 MX35_PAD_FEC_RX_ERR__GPIO3_16
|
||||
910 MX35_PAD_FEC_RX_ERR__IPU_DISPB_SD_D_IO
|
||||
911 MX35_PAD_FEC_CRS__FEC_CRS
|
||||
912 MX35_PAD_FEC_CRS__IPU_CSI_D_1
|
||||
913 MX35_PAD_FEC_CRS__USB_TOP_USBH2_PWR
|
||||
914 MX35_PAD_FEC_CRS__KPP_COL_5
|
||||
915 MX35_PAD_FEC_CRS__GPIO3_17
|
||||
916 MX35_PAD_FEC_CRS__IPU_FLASH_STROBE
|
||||
917 MX35_PAD_FEC_RDATA1__FEC_RDATA_1
|
||||
918 MX35_PAD_FEC_RDATA1__IPU_CSI_D_2
|
||||
919 MX35_PAD_FEC_RDATA1__AUDMUX_AUD6_RXC
|
||||
920 MX35_PAD_FEC_RDATA1__USB_TOP_USBH2_OC
|
||||
921 MX35_PAD_FEC_RDATA1__KPP_COL_6
|
||||
922 MX35_PAD_FEC_RDATA1__GPIO3_18
|
||||
923 MX35_PAD_FEC_RDATA1__IPU_DISPB_BE0
|
||||
924 MX35_PAD_FEC_TDATA1__FEC_TDATA_1
|
||||
925 MX35_PAD_FEC_TDATA1__IPU_CSI_D_3
|
||||
926 MX35_PAD_FEC_TDATA1__AUDMUX_AUD6_RXFS
|
||||
927 MX35_PAD_FEC_TDATA1__KPP_COL_7
|
||||
928 MX35_PAD_FEC_TDATA1__GPIO3_19
|
||||
929 MX35_PAD_FEC_TDATA1__IPU_DISPB_BE1
|
||||
930 MX35_PAD_FEC_RDATA2__FEC_RDATA_2
|
||||
931 MX35_PAD_FEC_RDATA2__IPU_CSI_D_4
|
||||
932 MX35_PAD_FEC_RDATA2__AUDMUX_AUD6_TXD
|
||||
933 MX35_PAD_FEC_RDATA2__KPP_ROW_4
|
||||
934 MX35_PAD_FEC_RDATA2__GPIO3_20
|
||||
935 MX35_PAD_FEC_TDATA2__FEC_TDATA_2
|
||||
936 MX35_PAD_FEC_TDATA2__IPU_CSI_D_5
|
||||
937 MX35_PAD_FEC_TDATA2__AUDMUX_AUD6_RXD
|
||||
938 MX35_PAD_FEC_TDATA2__KPP_ROW_5
|
||||
939 MX35_PAD_FEC_TDATA2__GPIO3_21
|
||||
940 MX35_PAD_FEC_RDATA3__FEC_RDATA_3
|
||||
941 MX35_PAD_FEC_RDATA3__IPU_CSI_D_6
|
||||
942 MX35_PAD_FEC_RDATA3__AUDMUX_AUD6_TXC
|
||||
943 MX35_PAD_FEC_RDATA3__KPP_ROW_6
|
||||
944 MX35_PAD_FEC_RDATA3__GPIO3_22
|
||||
945 MX35_PAD_FEC_TDATA3__FEC_TDATA_3
|
||||
946 MX35_PAD_FEC_TDATA3__IPU_CSI_D_7
|
||||
947 MX35_PAD_FEC_TDATA3__AUDMUX_AUD6_TXFS
|
||||
948 MX35_PAD_FEC_TDATA3__KPP_ROW_7
|
||||
949 MX35_PAD_FEC_TDATA3__GPIO3_23
|
||||
950 MX35_PAD_EXT_ARMCLK__CCM_EXT_ARMCLK
|
||||
951 MX35_PAD_TEST_MODE__TCU_TEST_MODE
|
||||
|
|
@ -14,10 +14,12 @@ Optional properties:
|
|||
- pinctrl-single,function-off : function off mode for disabled state if
|
||||
available and same for all registers; if not specified, disabling of
|
||||
pin functions is ignored
|
||||
- pinctrl-single,bit-per-mux : boolean to indicate that one register controls
|
||||
more than one pin
|
||||
|
||||
This driver assumes that there is only one register for each pin,
|
||||
and uses the common pinctrl bindings as specified in the pinctrl-bindings.txt
|
||||
document in this directory.
|
||||
This driver assumes that there is only one register for each pin (unless the
|
||||
pinctrl-single,bit-per-mux is set), and uses the common pinctrl bindings as
|
||||
specified in the pinctrl-bindings.txt document in this directory.
|
||||
|
||||
The pin configuration nodes for pinctrl-single are specified as pinctrl
|
||||
register offset and value pairs using pinctrl-single,pins. Only the bits
|
||||
|
|
@ -31,6 +33,15 @@ device pinctrl register, and 0x118 contains the desired value of the
|
|||
pinctrl register. See the device example and static board pins example
|
||||
below for more information.
|
||||
|
||||
In case when one register changes more than one pin's mux the
|
||||
pinctrl-single,bits need to be used which takes three parameters:
|
||||
|
||||
pinctrl-single,bits = <0xdc 0x18, 0xff>;
|
||||
|
||||
Where 0xdc is the offset from the pinctrl register base address for the
|
||||
device pinctrl register, 0x18 is the desired value, and 0xff is the sub mask to
|
||||
be used when applying this change to the register.
|
||||
|
||||
Example:
|
||||
|
||||
/* SoC common file */
|
||||
|
|
@ -55,6 +66,15 @@ pmx_wkup: pinmux@4a31e040 {
|
|||
pinctrl-single,function-mask = <0xffff>;
|
||||
};
|
||||
|
||||
control_devconf0: pinmux@48002274 {
|
||||
compatible = "pinctrl-single";
|
||||
reg = <0x48002274 4>; /* Single register */
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
pinctrl-single,bit-per-mux;
|
||||
pinctrl-single,register-width = <32>;
|
||||
pinctrl-single,function-mask = <0x5F>;
|
||||
};
|
||||
|
||||
/* board specific .dts file */
|
||||
|
||||
|
|
@ -87,6 +107,21 @@ pmx_wkup: pinmux@4a31e040 {
|
|||
};
|
||||
};
|
||||
|
||||
&control_devconf0 {
|
||||
mcbsp1_pins: pinmux_mcbsp1_pins {
|
||||
pinctrl-single,bits = <
|
||||
0x00 0x18 0x18 /* FSR/CLKR signal from FSX/CLKX pin */
|
||||
>;
|
||||
};
|
||||
|
||||
mcbsp2_clks_pins: pinmux_mcbsp2_clks_pins {
|
||||
pinctrl-single,bits = <
|
||||
0x00 0x40 0x40 /* McBSP2 CLKS from McBSP_CLKS pin */
|
||||
>;
|
||||
};
|
||||
|
||||
};
|
||||
|
||||
&uart2 {
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&uart2_pins>;
|
||||
|
|
|
|||
|
|
@ -289,6 +289,11 @@ Interaction with the GPIO subsystem
|
|||
The GPIO drivers may want to perform operations of various types on the same
|
||||
physical pins that are also registered as pin controller pins.
|
||||
|
||||
First and foremost, the two subsystems can be used as completely orthogonal,
|
||||
see the section named "pin control requests from drivers" and
|
||||
"drivers needing both pin control and GPIOs" below for details. But in some
|
||||
situations a cross-subsystem mapping between pins and GPIOs is needed.
|
||||
|
||||
Since the pin controller subsystem have its pinspace local to the pin
|
||||
controller we need a mapping so that the pin control subsystem can figure out
|
||||
which pin controller handles control of a certain GPIO pin. Since a single
|
||||
|
|
@ -359,6 +364,7 @@ will get an pin number into its handled number range. Further it is also passed
|
|||
the range ID value, so that the pin controller knows which range it should
|
||||
deal with.
|
||||
|
||||
|
||||
PINMUX interfaces
|
||||
=================
|
||||
|
||||
|
|
@ -960,8 +966,8 @@ all get selected, and they all get enabled and disable simultaneously by the
|
|||
pinmux core.
|
||||
|
||||
|
||||
Pinmux requests from drivers
|
||||
============================
|
||||
Pin control requests from drivers
|
||||
=================================
|
||||
|
||||
Generally it is discouraged to let individual drivers get and enable pin
|
||||
control. So if possible, handle the pin control in platform code or some other
|
||||
|
|
@ -969,6 +975,11 @@ place where you have access to all the affected struct device * pointers. In
|
|||
some cases where a driver needs to e.g. switch between different mux mappings
|
||||
at runtime this is not possible.
|
||||
|
||||
A typical case is if a driver needs to switch bias of pins from normal
|
||||
operation and going to sleep, moving from the PINCTRL_STATE_DEFAULT to
|
||||
PINCTRL_STATE_SLEEP at runtime, re-biasing or even re-muxing pins to save
|
||||
current in sleep mode.
|
||||
|
||||
A driver may request a certain control state to be activated, usually just the
|
||||
default state like this:
|
||||
|
||||
|
|
@ -1058,6 +1069,51 @@ registered. Thus make sure that the error path in your driver gracefully
|
|||
cleans up and is ready to retry the probing later in the startup process.
|
||||
|
||||
|
||||
Drivers needing both pin control and GPIOs
|
||||
==========================================
|
||||
|
||||
Again, it is discouraged to let drivers lookup and select pin control states
|
||||
themselves, but again sometimes this is unavoidable.
|
||||
|
||||
So say that your driver is fetching its resources like this:
|
||||
|
||||
#include <linux/pinctrl/consumer.h>
|
||||
#include <linux/gpio.h>
|
||||
|
||||
struct pinctrl *pinctrl;
|
||||
int gpio;
|
||||
|
||||
pinctrl = devm_pinctrl_get_select_default(&dev);
|
||||
gpio = devm_gpio_request(&dev, 14, "foo");
|
||||
|
||||
Here we first request a certain pin state and then request GPIO 14 to be
|
||||
used. If you're using the subsystems orthogonally like this, you should
|
||||
nominally always get your pinctrl handle and select the desired pinctrl
|
||||
state BEFORE requesting the GPIO. This is a semantic convention to avoid
|
||||
situations that can be electrically unpleasant, you will certainly want to
|
||||
mux in and bias pins in a certain way before the GPIO subsystems starts to
|
||||
deal with them.
|
||||
|
||||
The above can be hidden: using pinctrl hogs, the pin control driver may be
|
||||
setting up the config and muxing for the pins when it is probing,
|
||||
nevertheless orthogonal to the GPIO subsystem.
|
||||
|
||||
But there are also situations where it makes sense for the GPIO subsystem
|
||||
to communicate directly with with the pinctrl subsystem, using the latter
|
||||
as a back-end. This is when the GPIO driver may call out to the functions
|
||||
described in the section "Pin control interaction with the GPIO subsystem"
|
||||
above. This only involves per-pin multiplexing, and will be completely
|
||||
hidden behind the gpio_*() function namespace. In this case, the driver
|
||||
need not interact with the pin control subsystem at all.
|
||||
|
||||
If a pin control driver and a GPIO driver is dealing with the same pins
|
||||
and the use cases involve multiplexing, you MUST implement the pin controller
|
||||
as a back-end for the GPIO driver like this, unless your hardware design
|
||||
is such that the GPIO controller can override the pin controller's
|
||||
multiplexing state through hardware without the need to interact with the
|
||||
pin control system.
|
||||
|
||||
|
||||
System pin control hogging
|
||||
==========================
|
||||
|
||||
|
|
|
|||
|
|
@ -891,6 +891,7 @@ config ARCH_NOMADIK
|
|||
select COMMON_CLK
|
||||
select GENERIC_CLOCKEVENTS
|
||||
select PINCTRL
|
||||
select PINCTRL_STN8815
|
||||
select MIGHT_HAVE_CACHE_L2X0
|
||||
select ARCH_REQUIRE_GPIOLIB
|
||||
help
|
||||
|
|
|
|||
|
|
@ -23,6 +23,7 @@
|
|||
#include <linux/mtd/partitions.h>
|
||||
#include <linux/i2c.h>
|
||||
#include <linux/io.h>
|
||||
#include <linux/pinctrl/machine.h>
|
||||
#include <asm/hardware/vic.h>
|
||||
#include <asm/sizes.h>
|
||||
#include <asm/mach-types.h>
|
||||
|
|
@ -33,6 +34,7 @@
|
|||
|
||||
#include <plat/gpio-nomadik.h>
|
||||
#include <plat/mtu.h>
|
||||
#include <plat/pincfg.h>
|
||||
|
||||
#include <linux/platform_data/mtd-nomadik-nand.h>
|
||||
#include <mach/fsmc.h>
|
||||
|
|
@ -290,8 +292,42 @@ static struct i2c_board_info __initdata nhk8815_i2c2_devices[] = {
|
|||
},
|
||||
};
|
||||
|
||||
static unsigned long out_low[] = { PIN_OUTPUT_LOW };
|
||||
static unsigned long out_high[] = { PIN_OUTPUT_HIGH };
|
||||
static unsigned long in_nopull[] = { PIN_INPUT_NOPULL };
|
||||
static unsigned long in_pullup[] = { PIN_INPUT_PULLUP };
|
||||
|
||||
static struct pinctrl_map __initdata nhk8815_pinmap[] = {
|
||||
PIN_MAP_MUX_GROUP_DEFAULT("uart0", "pinctrl-stn8815", "u0_a_1", "u0"),
|
||||
PIN_MAP_MUX_GROUP_DEFAULT("uart1", "pinctrl-stn8815", "u1_a_1", "u1"),
|
||||
/* Hog in MMC/SD card mux */
|
||||
PIN_MAP_MUX_GROUP_HOG_DEFAULT("pinctrl-stn8815", "mmcsd_a_1", "mmcsd"),
|
||||
/* MCCLK */
|
||||
PIN_MAP_CONFIGS_PIN_HOG_DEFAULT("pinctrl-stn8815", "GPIO8_B10", out_low),
|
||||
/* MCCMD */
|
||||
PIN_MAP_CONFIGS_PIN_HOG_DEFAULT("pinctrl-stn8815", "GPIO9_A10", in_pullup),
|
||||
/* MCCMDDIR */
|
||||
PIN_MAP_CONFIGS_PIN_HOG_DEFAULT("pinctrl-stn8815", "GPIO10_C11", out_high),
|
||||
/* MCDAT3-0 */
|
||||
PIN_MAP_CONFIGS_PIN_HOG_DEFAULT("pinctrl-stn8815", "GPIO11_B11", in_pullup),
|
||||
PIN_MAP_CONFIGS_PIN_HOG_DEFAULT("pinctrl-stn8815", "GPIO12_A11", in_pullup),
|
||||
PIN_MAP_CONFIGS_PIN_HOG_DEFAULT("pinctrl-stn8815", "GPIO13_C12", in_pullup),
|
||||
PIN_MAP_CONFIGS_PIN_HOG_DEFAULT("pinctrl-stn8815", "GPIO14_B12", in_pullup),
|
||||
/* MCDAT0DIR */
|
||||
PIN_MAP_CONFIGS_PIN_HOG_DEFAULT("pinctrl-stn8815", "GPIO15_A12", out_high),
|
||||
/* MCDAT31DIR */
|
||||
PIN_MAP_CONFIGS_PIN_HOG_DEFAULT("pinctrl-stn8815", "GPIO16_C13", out_high),
|
||||
/* MCMSFBCLK */
|
||||
PIN_MAP_CONFIGS_PIN_HOG_DEFAULT("pinctrl-stn8815", "GPIO24_C15", in_pullup),
|
||||
/* CD input GPIO */
|
||||
PIN_MAP_CONFIGS_PIN_HOG_DEFAULT("pinctrl-stn8815", "GPIO111_H21", in_nopull),
|
||||
/* CD bias drive */
|
||||
PIN_MAP_CONFIGS_PIN_HOG_DEFAULT("pinctrl-stn8815", "GPIO112_J21", out_low),
|
||||
};
|
||||
|
||||
static void __init nhk8815_platform_init(void)
|
||||
{
|
||||
pinctrl_register_mappings(nhk8815_pinmap, ARRAY_SIZE(nhk8815_pinmap));
|
||||
cpu8815_platform_init();
|
||||
nhk8815_onenand_init();
|
||||
platform_add_devices(nhk8815_platform_devices,
|
||||
|
|
|
|||
|
|
@ -83,6 +83,18 @@ void cpu8815_add_gpios(resource_size_t *base, int num, int irq,
|
|||
}
|
||||
}
|
||||
|
||||
static inline void
|
||||
cpu8815_add_pinctrl(struct device *parent, const char *name)
|
||||
{
|
||||
struct platform_device_info pdevinfo = {
|
||||
.parent = parent,
|
||||
.name = name,
|
||||
.id = -1,
|
||||
};
|
||||
|
||||
platform_device_register_full(&pdevinfo);
|
||||
}
|
||||
|
||||
static int __init cpu8815_init(void)
|
||||
{
|
||||
struct nmk_gpio_platform_data pdata = {
|
||||
|
|
@ -91,6 +103,7 @@ static int __init cpu8815_init(void)
|
|||
|
||||
cpu8815_add_gpios(cpu8815_gpio_base, ARRAY_SIZE(cpu8815_gpio_base),
|
||||
IRQ_GPIO0, &pdata);
|
||||
cpu8815_add_pinctrl(NULL, "pinctrl-stn8815");
|
||||
amba_apb_device_add(NULL, "rng", NOMADIK_RNG_BASE, SZ_4K, 0, 0, NULL, 0);
|
||||
amba_apb_device_add(NULL, "rtc-pl031", NOMADIK_RTC_BASE, SZ_4K, IRQ_RTC_RTT, 0, NULL, 0);
|
||||
return 0;
|
||||
|
|
|
|||
|
|
@ -30,16 +30,15 @@ static enum custom_pin_cfg_t pinsfor;
|
|||
#define BIAS(a,b) static unsigned long a[] = { b }
|
||||
|
||||
BIAS(pd, PIN_PULL_DOWN);
|
||||
BIAS(slpm_gpio_nopull, PIN_SLPM_GPIO|PIN_SLPM_INPUT_NOPULL);
|
||||
BIAS(in_nopull, PIN_INPUT_NOPULL);
|
||||
BIAS(in_nopull_sleep_nowkup, PIN_INPUT_NOPULL|PIN_SLPM_WAKEUP_DISABLE);
|
||||
BIAS(in_nopull_slpm_nowkup, PIN_INPUT_NOPULL|PIN_SLPM_WAKEUP_DISABLE);
|
||||
BIAS(in_pu, PIN_INPUT_PULLUP);
|
||||
BIAS(in_pd, PIN_INPUT_PULLDOWN);
|
||||
BIAS(in_pd_slpm_in_pu, PIN_INPUT_PULLDOWN|PIN_SLPM_INPUT_PULLUP);
|
||||
BIAS(in_pu_slpm_out_lo, PIN_INPUT_PULLUP|PIN_SLPM_OUTPUT_LOW);
|
||||
BIAS(out_hi, PIN_OUTPUT_HIGH);
|
||||
BIAS(out_lo, PIN_OUTPUT_LOW);
|
||||
BIAS(out_lo_sleep_nowkup, PIN_OUTPUT_LOW|PIN_SLPM_WAKEUP_DISABLE);
|
||||
BIAS(out_lo_slpm_nowkup, PIN_OUTPUT_LOW|PIN_SLPM_WAKEUP_DISABLE);
|
||||
/* These also force them into GPIO mode */
|
||||
BIAS(gpio_in_pu, PIN_INPUT_PULLUP|PIN_GPIOMODE_ENABLED);
|
||||
BIAS(gpio_in_pd, PIN_INPUT_PULLDOWN|PIN_GPIOMODE_ENABLED);
|
||||
|
|
@ -48,23 +47,32 @@ BIAS(gpio_in_pd_slpm_gpio_nopull, PIN_INPUT_PULLDOWN|PIN_GPIOMODE_ENABLED|PIN_SL
|
|||
BIAS(gpio_out_hi, PIN_OUTPUT_HIGH|PIN_GPIOMODE_ENABLED);
|
||||
BIAS(gpio_out_lo, PIN_OUTPUT_LOW|PIN_GPIOMODE_ENABLED);
|
||||
/* Sleep modes */
|
||||
BIAS(sleep_in_wkup_pdis, PIN_SLPM_DIR_INPUT|PIN_SLPM_WAKEUP_ENABLE|PIN_SLPM_PDIS_DISABLED);
|
||||
BIAS(sleep_in_nopull_wkup, PIN_INPUT_NOPULL|PIN_SLPM_WAKEUP_ENABLE);
|
||||
BIAS(sleep_out_hi_wkup_pdis, PIN_SLPM_OUTPUT_HIGH|PIN_SLPM_WAKEUP_ENABLE|PIN_SLPM_PDIS_DISABLED);
|
||||
BIAS(sleep_out_lo_wkup, PIN_OUTPUT_LOW|PIN_SLPM_WAKEUP_ENABLE);
|
||||
BIAS(sleep_out_wkup_pdis, PIN_SLPM_DIR_OUTPUT|PIN_SLPM_WAKEUP_ENABLE|PIN_SLPM_PDIS_DISABLED);
|
||||
BIAS(slpm_in_wkup_pdis, PIN_SLEEPMODE_ENABLED|PIN_SLPM_DIR_INPUT|PIN_SLPM_WAKEUP_ENABLE|PIN_SLPM_PDIS_DISABLED);
|
||||
BIAS(slpm_in_nopull_wkup, PIN_SLEEPMODE_ENABLED|PIN_SLPM_DIR_INPUT|PIN_SLPM_PULL_NONE|PIN_SLPM_WAKEUP_ENABLE);
|
||||
BIAS(slpm_wkup_pdis, PIN_SLEEPMODE_ENABLED|PIN_SLPM_WAKEUP_ENABLE|PIN_SLPM_PDIS_DISABLED);
|
||||
BIAS(slpm_out_hi_wkup_pdis, PIN_SLEEPMODE_ENABLED|PIN_SLPM_OUTPUT_HIGH|PIN_SLPM_WAKEUP_ENABLE|PIN_SLPM_PDIS_DISABLED);
|
||||
BIAS(slpm_out_wkup_pdis, PIN_SLEEPMODE_ENABLED|PIN_SLPM_WAKEUP_ENABLE|PIN_SLPM_PDIS_DISABLED);
|
||||
BIAS(slpm_out_lo_wkup, PIN_SLEEPMODE_ENABLED|PIN_SLPM_OUTPUT_LOW|PIN_SLPM_WAKEUP_ENABLE);
|
||||
BIAS(slpm_out_lo_wkup_pdis, PIN_SLEEPMODE_ENABLED|PIN_SLPM_OUTPUT_LOW|PIN_SLPM_WAKEUP_ENABLE|PIN_SLPM_PDIS_DISABLED);
|
||||
BIAS(slpm_in_nopull_wkup_pdis, PIN_SLEEPMODE_ENABLED|PIN_SLPM_INPUT_NOPULL|PIN_SLPM_WAKEUP_ENABLE|PIN_SLPM_PDIS_DISABLED);
|
||||
|
||||
/* We use these to define hog settings that are always done on boot */
|
||||
#define DB8500_MUX_HOG(group,func) \
|
||||
PIN_MAP_MUX_GROUP_HOG_DEFAULT("pinctrl-db8500", group, func)
|
||||
#define DB8500_PIN_HOG(pin,conf) \
|
||||
PIN_MAP_CONFIGS_PIN_HOG_DEFAULT("pinctrl-db8500", pin, conf)
|
||||
#define DB8500_PIN_SLEEP(pin, conf, dev) \
|
||||
PIN_MAP_CONFIGS_PIN(dev, PINCTRL_STATE_SLEEP, "pinctrl-db8500", \
|
||||
pin, conf)
|
||||
|
||||
/* These are default states associated with device and changed runtime */
|
||||
#define DB8500_MUX(group,func,dev) \
|
||||
PIN_MAP_MUX_GROUP_DEFAULT(dev, "pinctrl-db8500", group, func)
|
||||
#define DB8500_PIN(pin,conf,dev) \
|
||||
PIN_MAP_CONFIGS_PIN_DEFAULT(dev, "pinctrl-db8500", pin, conf)
|
||||
#define DB8500_PIN_SLEEP(pin, conf, dev) \
|
||||
PIN_MAP_CONFIGS_PIN(dev, PINCTRL_STATE_SLEEP, "pinctrl-db8500", \
|
||||
pin, conf)
|
||||
|
||||
#define DB8500_PIN_SLEEP(pin,conf,dev) \
|
||||
PIN_MAP_CONFIGS_PIN(dev, PINCTRL_STATE_SLEEP, "pinctrl-db8500", \
|
||||
|
|
@ -134,40 +142,47 @@ static struct pinctrl_map __initdata mop500_family_pinmap[] = {
|
|||
DB8500_PIN("GPIO2_AH4", in_pu, "uart0"), /* RXD */
|
||||
DB8500_PIN("GPIO3_AH3", out_hi, "uart0"), /* TXD */
|
||||
/* UART0 sleep state */
|
||||
DB8500_PIN_SLEEP("GPIO0_AJ5", sleep_in_wkup_pdis, "uart0"),
|
||||
DB8500_PIN_SLEEP("GPIO1_AJ3", sleep_out_hi_wkup_pdis, "uart0"),
|
||||
DB8500_PIN_SLEEP("GPIO2_AH4", sleep_in_wkup_pdis, "uart0"),
|
||||
DB8500_PIN_SLEEP("GPIO3_AH3", sleep_out_wkup_pdis, "uart0"),
|
||||
DB8500_PIN_SLEEP("GPIO0_AJ5", slpm_in_wkup_pdis, "uart0"),
|
||||
DB8500_PIN_SLEEP("GPIO1_AJ3", slpm_out_hi_wkup_pdis, "uart0"),
|
||||
DB8500_PIN_SLEEP("GPIO2_AH4", slpm_in_wkup_pdis, "uart0"),
|
||||
DB8500_PIN_SLEEP("GPIO3_AH3", slpm_out_wkup_pdis, "uart0"),
|
||||
/* MSP1 for ALSA codec */
|
||||
DB8500_MUX("msp1txrx_a_1", "msp1", "ux500-msp-i2s.1"),
|
||||
DB8500_MUX("msp1_a_1", "msp1", "ux500-msp-i2s.1"),
|
||||
DB8500_PIN("GPIO33_AF2", out_lo_sleep_nowkup, "ux500-msp-i2s.1"),
|
||||
DB8500_PIN("GPIO34_AE1", in_nopull_sleep_nowkup, "ux500-msp-i2s.1"),
|
||||
DB8500_PIN("GPIO35_AE2", in_nopull_sleep_nowkup, "ux500-msp-i2s.1"),
|
||||
DB8500_PIN("GPIO36_AG2", in_nopull_sleep_nowkup, "ux500-msp-i2s.1"),
|
||||
DB8500_PIN("GPIO33_AF2", out_lo_slpm_nowkup, "ux500-msp-i2s.1"),
|
||||
DB8500_PIN("GPIO34_AE1", in_nopull_slpm_nowkup, "ux500-msp-i2s.1"),
|
||||
DB8500_PIN("GPIO35_AE2", in_nopull_slpm_nowkup, "ux500-msp-i2s.1"),
|
||||
DB8500_PIN("GPIO36_AG2", in_nopull_slpm_nowkup, "ux500-msp-i2s.1"),
|
||||
/* MSP1 sleep state */
|
||||
DB8500_PIN_SLEEP("GPIO33_AF2", sleep_out_lo_wkup, "ux500-msp-i2s.1"),
|
||||
DB8500_PIN_SLEEP("GPIO34_AE1", sleep_in_nopull_wkup, "ux500-msp-i2s.1"),
|
||||
DB8500_PIN_SLEEP("GPIO35_AE2", sleep_in_nopull_wkup, "ux500-msp-i2s.1"),
|
||||
DB8500_PIN_SLEEP("GPIO36_AG2", sleep_in_nopull_wkup, "ux500-msp-i2s.1"),
|
||||
DB8500_PIN_SLEEP("GPIO33_AF2", slpm_out_lo_wkup, "ux500-msp-i2s.1"),
|
||||
DB8500_PIN_SLEEP("GPIO34_AE1", slpm_in_nopull_wkup, "ux500-msp-i2s.1"),
|
||||
DB8500_PIN_SLEEP("GPIO35_AE2", slpm_in_nopull_wkup, "ux500-msp-i2s.1"),
|
||||
DB8500_PIN_SLEEP("GPIO36_AG2", slpm_in_nopull_wkup, "ux500-msp-i2s.1"),
|
||||
/* Mux in LCD data lines 8 thru 11 and LCDA CLK for MCDE TVOUT */
|
||||
DB8500_MUX("lcd_d8_d11_a_1", "lcd", "mcde-tvout"),
|
||||
DB8500_MUX("lcdaclk_b_1", "lcda", "mcde-tvout"),
|
||||
/* Mux in LCD VSI1 and pull it up for MCDE HDMI output */
|
||||
DB8500_MUX("lcdvsi1_a_1", "lcd", "av8100-hdmi"),
|
||||
/* Mux in I2C blocks, put pins into GPIO in sleepmode no pull-up */
|
||||
/* Mux in i2c0 block, default state */
|
||||
DB8500_MUX("i2c0_a_1", "i2c0", "nmk-i2c.0"),
|
||||
DB8500_PIN("GPIO147_C15", slpm_gpio_nopull, "nmk-i2c.0"),
|
||||
DB8500_PIN("GPIO148_B16", slpm_gpio_nopull, "nmk-i2c.0"),
|
||||
/* i2c0 sleep state */
|
||||
DB8500_PIN_SLEEP("GPIO147_C15", slpm_in_nopull_wkup_pdis, "nmk-i2c.0"), /* SDA */
|
||||
DB8500_PIN_SLEEP("GPIO148_B16", slpm_in_nopull_wkup_pdis, "nmk-i2c.0"), /* SCL */
|
||||
/* Mux in i2c1 block, default state */
|
||||
DB8500_MUX("i2c1_b_2", "i2c1", "nmk-i2c.1"),
|
||||
DB8500_PIN("GPIO16_AD3", slpm_gpio_nopull, "nmk-i2c.1"),
|
||||
DB8500_PIN("GPIO17_AD4", slpm_gpio_nopull, "nmk-i2c.1"),
|
||||
/* i2c1 sleep state */
|
||||
DB8500_PIN_SLEEP("GPIO16_AD3", slpm_in_nopull_wkup_pdis, "nmk-i2c.1"), /* SDA */
|
||||
DB8500_PIN_SLEEP("GPIO17_AD4", slpm_in_nopull_wkup_pdis, "nmk-i2c.1"), /* SCL */
|
||||
/* Mux in i2c2 block, default state */
|
||||
DB8500_MUX("i2c2_b_2", "i2c2", "nmk-i2c.2"),
|
||||
DB8500_PIN("GPIO10_AF5", slpm_gpio_nopull, "nmk-i2c.2"),
|
||||
DB8500_PIN("GPIO11_AG4", slpm_gpio_nopull, "nmk-i2c.2"),
|
||||
/* i2c2 sleep state */
|
||||
DB8500_PIN_SLEEP("GPIO10_AF5", slpm_in_nopull_wkup_pdis, "nmk-i2c.2"), /* SDA */
|
||||
DB8500_PIN_SLEEP("GPIO11_AG4", slpm_in_nopull_wkup_pdis, "nmk-i2c.2"), /* SCL */
|
||||
/* Mux in i2c3 block, default state */
|
||||
DB8500_MUX("i2c3_c_2", "i2c3", "nmk-i2c.3"),
|
||||
DB8500_PIN("GPIO229_AG7", slpm_gpio_nopull, "nmk-i2c.3"),
|
||||
DB8500_PIN("GPIO230_AF7", slpm_gpio_nopull, "nmk-i2c.3"),
|
||||
/* i2c3 sleep state */
|
||||
DB8500_PIN_SLEEP("GPIO229_AG7", slpm_in_nopull_wkup_pdis, "nmk-i2c.3"), /* SDA */
|
||||
DB8500_PIN_SLEEP("GPIO230_AF7", slpm_in_nopull_wkup_pdis, "nmk-i2c.3"), /* SCL */
|
||||
/* Mux in SDI0 (here called MC0) used for removable MMC/SD/SDIO cards */
|
||||
DB8500_MUX("mc0_a_1", "mc0", "sdi0"),
|
||||
DB8500_PIN("GPIO18_AC2", out_hi, "sdi0"), /* CMDDIR */
|
||||
|
|
@ -219,11 +234,15 @@ static struct pinctrl_map __initdata mop500_family_pinmap[] = {
|
|||
DB8500_MUX("usb_a_1", "usb", "musb-ux500.0"),
|
||||
DB8500_PIN("GPIO257_AE29", out_hi, "musb-ux500.0"), /* STP */
|
||||
/* Mux in SPI2 pins on the "other C1" altfunction */
|
||||
DB8500_MUX("spi2_oc1_1", "spi2", "spi2"),
|
||||
DB8500_MUX("spi2_oc1_2", "spi2", "spi2"),
|
||||
DB8500_PIN("GPIO216_AG12", gpio_out_hi, "spi2"), /* FRM */
|
||||
DB8500_PIN("GPIO218_AH11", in_pd, "spi2"), /* RXD */
|
||||
DB8500_PIN("GPIO215_AH13", out_lo, "spi2"), /* TXD */
|
||||
DB8500_PIN("GPIO217_AH12", out_lo, "spi2"), /* CLK */
|
||||
/* SPI2 sleep state */
|
||||
DB8500_PIN_SLEEP("GPIO218_AH11", slpm_in_wkup_pdis, "spi2"), /* RXD */
|
||||
DB8500_PIN_SLEEP("GPIO215_AH13", slpm_out_lo_wkup_pdis, "spi2"), /* TXD */
|
||||
DB8500_PIN_SLEEP("GPIO217_AH12", slpm_wkup_pdis, "spi2"), /* CLK */
|
||||
};
|
||||
|
||||
/*
|
||||
|
|
@ -410,7 +429,7 @@ static struct pinctrl_map __initdata u9500_pinmap[] = {
|
|||
DB8500_PIN_HOG("GPIO144_B13", gpio_in_pu),
|
||||
/* HSI */
|
||||
DB8500_MUX_HOG("hsir_a_1", "hsi"),
|
||||
DB8500_MUX_HOG("hsit_a_1", "hsi"),
|
||||
DB8500_MUX_HOG("hsit_a_2", "hsi"),
|
||||
DB8500_PIN_HOG("GPIO219_AG10", in_pd), /* RX FLA0 */
|
||||
DB8500_PIN_HOG("GPIO220_AH10", in_pd), /* RX DAT0 */
|
||||
DB8500_PIN_HOG("GPIO221_AJ11", out_lo), /* RX RDY0 */
|
||||
|
|
@ -418,7 +437,7 @@ static struct pinctrl_map __initdata u9500_pinmap[] = {
|
|||
DB8500_PIN_HOG("GPIO223_AH9", out_lo), /* TX DAT0 */
|
||||
DB8500_PIN_HOG("GPIO224_AG9", in_pd), /* TX RDY0 */
|
||||
DB8500_PIN_HOG("GPIO225_AG8", in_pd), /* CAWAKE0 */
|
||||
DB8500_PIN_HOG("GPIO226_AF8", out_hi), /* ACWAKE0 */
|
||||
DB8500_PIN_HOG("GPIO226_AF8", gpio_out_hi), /* ACWAKE0 */
|
||||
};
|
||||
|
||||
static struct pinctrl_map __initdata u8500_pinmap[] = {
|
||||
|
|
|
|||
|
|
@ -26,11 +26,24 @@ config DEBUG_PINCTRL
|
|||
help
|
||||
Say Y here to add some extra checks and diagnostics to PINCTRL calls.
|
||||
|
||||
config PINCTRL_BCM2835
|
||||
bool
|
||||
select PINMUX
|
||||
select PINCONF
|
||||
|
||||
config PINCTRL_IMX
|
||||
bool
|
||||
select PINMUX
|
||||
select PINCONF
|
||||
|
||||
config PINCTRL_IMX35
|
||||
bool "IMX35 pinctrl driver"
|
||||
depends on OF
|
||||
depends on SOC_IMX35
|
||||
select PINCTRL_IMX
|
||||
help
|
||||
Say Y here to enable the imx35 pinctrl driver
|
||||
|
||||
config PINCTRL_IMX51
|
||||
bool "IMX51 pinctrl driver"
|
||||
depends on OF
|
||||
|
|
@ -86,10 +99,18 @@ config PINCTRL_NOMADIK
|
|||
select PINMUX
|
||||
select PINCONF
|
||||
|
||||
config PINCTRL_STN8815
|
||||
bool "STN8815 pin controller driver"
|
||||
depends on PINCTRL_NOMADIK && ARCH_NOMADIK
|
||||
|
||||
config PINCTRL_DB8500
|
||||
bool "DB8500 pin controller driver"
|
||||
depends on PINCTRL_NOMADIK && ARCH_U8500
|
||||
|
||||
config PINCTRL_DB8540
|
||||
bool "DB8540 pin controller driver"
|
||||
depends on PINCTRL_NOMADIK && ARCH_U8500
|
||||
|
||||
config PINCTRL_PXA168
|
||||
bool "PXA168 pin controller driver"
|
||||
depends on ARCH_MMP
|
||||
|
|
|
|||
|
|
@ -9,7 +9,9 @@ ifeq ($(CONFIG_OF),y)
|
|||
obj-$(CONFIG_PINCTRL) += devicetree.o
|
||||
endif
|
||||
obj-$(CONFIG_GENERIC_PINCONF) += pinconf-generic.o
|
||||
obj-$(CONFIG_PINCTRL_BCM2835) += pinctrl-bcm2835.o
|
||||
obj-$(CONFIG_PINCTRL_IMX) += pinctrl-imx.o
|
||||
obj-$(CONFIG_PINCTRL_IMX35) += pinctrl-imx35.o
|
||||
obj-$(CONFIG_PINCTRL_IMX51) += pinctrl-imx51.o
|
||||
obj-$(CONFIG_PINCTRL_IMX53) += pinctrl-imx53.o
|
||||
obj-$(CONFIG_PINCTRL_IMX6Q) += pinctrl-imx6q.o
|
||||
|
|
@ -19,7 +21,9 @@ obj-$(CONFIG_PINCTRL_MXS) += pinctrl-mxs.o
|
|||
obj-$(CONFIG_PINCTRL_IMX23) += pinctrl-imx23.o
|
||||
obj-$(CONFIG_PINCTRL_IMX28) += pinctrl-imx28.o
|
||||
obj-$(CONFIG_PINCTRL_NOMADIK) += pinctrl-nomadik.o
|
||||
obj-$(CONFIG_PINCTRL_STN8815) += pinctrl-nomadik-stn8815.o
|
||||
obj-$(CONFIG_PINCTRL_DB8500) += pinctrl-nomadik-db8500.o
|
||||
obj-$(CONFIG_PINCTRL_DB8540) += pinctrl-nomadik-db8540.o
|
||||
obj-$(CONFIG_PINCTRL_PXA168) += pinctrl-pxa168.o
|
||||
obj-$(CONFIG_PINCTRL_PXA910) += pinctrl-pxa910.o
|
||||
obj-$(CONFIG_PINCTRL_SINGLE) += pinctrl-single.o
|
||||
|
|
|
|||
|
|
@ -230,8 +230,10 @@ static int pinctrl_register_one_pin(struct pinctrl_dev *pctldev,
|
|||
pindesc->name = name;
|
||||
} else {
|
||||
pindesc->name = kasprintf(GFP_KERNEL, "PIN%u", number);
|
||||
if (pindesc->name == NULL)
|
||||
if (pindesc->name == NULL) {
|
||||
kfree(pindesc);
|
||||
return -ENOMEM;
|
||||
}
|
||||
pindesc->dynamic_name = true;
|
||||
}
|
||||
|
||||
|
|
|
|||
1075
drivers/pinctrl/pinctrl-bcm2835.c
Normal file
1075
drivers/pinctrl/pinctrl-bcm2835.c
Normal file
File diff suppressed because it is too large
Load diff
|
|
@ -432,7 +432,7 @@ static int __devinit imx_pinctrl_parse_groups(struct device_node *np,
|
|||
{
|
||||
unsigned int pin_func_id;
|
||||
int ret, size;
|
||||
const const __be32 *list;
|
||||
const __be32 *list;
|
||||
int i, j;
|
||||
u32 config;
|
||||
|
||||
|
|
|
|||
1595
drivers/pinctrl/pinctrl-imx35.c
Normal file
1595
drivers/pinctrl/pinctrl-imx35.c
Normal file
File diff suppressed because it is too large
Load diff
|
|
@ -23,251 +23,251 @@
|
|||
#include "pinctrl-imx.h"
|
||||
|
||||
enum imx51_pads {
|
||||
MX51_PAD_EIM_D16 = 1,
|
||||
MX51_PAD_EIM_D17 = 2,
|
||||
MX51_PAD_EIM_D18 = 3,
|
||||
MX51_PAD_EIM_D19 = 4,
|
||||
MX51_PAD_EIM_D20 = 5,
|
||||
MX51_PAD_EIM_D21 = 6,
|
||||
MX51_PAD_EIM_D22 = 7,
|
||||
MX51_PAD_EIM_D23 = 8,
|
||||
MX51_PAD_EIM_D24 = 9,
|
||||
MX51_PAD_EIM_D25 = 10,
|
||||
MX51_PAD_EIM_D26 = 11,
|
||||
MX51_PAD_EIM_D27 = 12,
|
||||
MX51_PAD_EIM_D28 = 13,
|
||||
MX51_PAD_EIM_D29 = 14,
|
||||
MX51_PAD_EIM_D30 = 15,
|
||||
MX51_PAD_EIM_D31 = 16,
|
||||
MX51_PAD_EIM_A16 = 17,
|
||||
MX51_PAD_EIM_A17 = 18,
|
||||
MX51_PAD_EIM_A18 = 19,
|
||||
MX51_PAD_EIM_A19 = 20,
|
||||
MX51_PAD_EIM_A20 = 21,
|
||||
MX51_PAD_EIM_A21 = 22,
|
||||
MX51_PAD_EIM_A22 = 23,
|
||||
MX51_PAD_EIM_A23 = 24,
|
||||
MX51_PAD_EIM_A24 = 25,
|
||||
MX51_PAD_EIM_A25 = 26,
|
||||
MX51_PAD_EIM_A26 = 27,
|
||||
MX51_PAD_EIM_A27 = 28,
|
||||
MX51_PAD_EIM_EB0 = 29,
|
||||
MX51_PAD_EIM_EB1 = 30,
|
||||
MX51_PAD_EIM_EB2 = 31,
|
||||
MX51_PAD_EIM_EB3 = 32,
|
||||
MX51_PAD_EIM_OE = 33,
|
||||
MX51_PAD_EIM_CS0 = 34,
|
||||
MX51_PAD_EIM_CS1 = 35,
|
||||
MX51_PAD_EIM_CS2 = 36,
|
||||
MX51_PAD_EIM_CS3 = 37,
|
||||
MX51_PAD_EIM_CS4 = 38,
|
||||
MX51_PAD_EIM_CS5 = 39,
|
||||
MX51_PAD_EIM_DTACK = 40,
|
||||
MX51_PAD_EIM_LBA = 41,
|
||||
MX51_PAD_EIM_CRE = 42,
|
||||
MX51_PAD_DRAM_CS1 = 43,
|
||||
MX51_PAD_NANDF_WE_B = 44,
|
||||
MX51_PAD_NANDF_RE_B = 45,
|
||||
MX51_PAD_NANDF_ALE = 46,
|
||||
MX51_PAD_NANDF_CLE = 47,
|
||||
MX51_PAD_NANDF_WP_B = 48,
|
||||
MX51_PAD_NANDF_RB0 = 49,
|
||||
MX51_PAD_NANDF_RB1 = 50,
|
||||
MX51_PAD_NANDF_RB2 = 51,
|
||||
MX51_PAD_NANDF_RB3 = 52,
|
||||
MX51_PAD_GPIO_NAND = 53,
|
||||
MX51_PAD_NANDF_CS0 = 54,
|
||||
MX51_PAD_NANDF_CS1 = 55,
|
||||
MX51_PAD_NANDF_CS2 = 56,
|
||||
MX51_PAD_NANDF_CS3 = 57,
|
||||
MX51_PAD_NANDF_CS4 = 58,
|
||||
MX51_PAD_NANDF_CS5 = 59,
|
||||
MX51_PAD_NANDF_CS6 = 60,
|
||||
MX51_PAD_NANDF_CS7 = 61,
|
||||
MX51_PAD_NANDF_RDY_INT = 62,
|
||||
MX51_PAD_NANDF_D15 = 63,
|
||||
MX51_PAD_NANDF_D14 = 64,
|
||||
MX51_PAD_NANDF_D13 = 65,
|
||||
MX51_PAD_NANDF_D12 = 66,
|
||||
MX51_PAD_NANDF_D11 = 67,
|
||||
MX51_PAD_NANDF_D10 = 68,
|
||||
MX51_PAD_NANDF_D9 = 69,
|
||||
MX51_PAD_NANDF_D8 = 70,
|
||||
MX51_PAD_NANDF_D7 = 71,
|
||||
MX51_PAD_NANDF_D6 = 72,
|
||||
MX51_PAD_NANDF_D5 = 73,
|
||||
MX51_PAD_NANDF_D4 = 74,
|
||||
MX51_PAD_NANDF_D3 = 75,
|
||||
MX51_PAD_NANDF_D2 = 76,
|
||||
MX51_PAD_NANDF_D1 = 77,
|
||||
MX51_PAD_NANDF_D0 = 78,
|
||||
MX51_PAD_CSI1_D8 = 79,
|
||||
MX51_PAD_CSI1_D9 = 80,
|
||||
MX51_PAD_CSI1_D10 = 81,
|
||||
MX51_PAD_CSI1_D11 = 82,
|
||||
MX51_PAD_CSI1_D12 = 83,
|
||||
MX51_PAD_CSI1_D13 = 84,
|
||||
MX51_PAD_CSI1_D14 = 85,
|
||||
MX51_PAD_CSI1_D15 = 86,
|
||||
MX51_PAD_CSI1_D16 = 87,
|
||||
MX51_PAD_CSI1_D17 = 88,
|
||||
MX51_PAD_CSI1_D18 = 89,
|
||||
MX51_PAD_CSI1_D19 = 90,
|
||||
MX51_PAD_CSI1_VSYNC = 91,
|
||||
MX51_PAD_CSI1_HSYNC = 92,
|
||||
MX51_PAD_CSI1_PIXCLK = 93,
|
||||
MX51_PAD_CSI1_MCLK = 94,
|
||||
MX51_PAD_CSI2_D12 = 95,
|
||||
MX51_PAD_CSI2_D13 = 96,
|
||||
MX51_PAD_CSI2_D14 = 97,
|
||||
MX51_PAD_CSI2_D15 = 98,
|
||||
MX51_PAD_CSI2_D16 = 99,
|
||||
MX51_PAD_CSI2_D17 = 100,
|
||||
MX51_PAD_CSI2_D18 = 101,
|
||||
MX51_PAD_CSI2_D19 = 102,
|
||||
MX51_PAD_CSI2_VSYNC = 103,
|
||||
MX51_PAD_CSI2_HSYNC = 104,
|
||||
MX51_PAD_CSI2_PIXCLK = 105,
|
||||
MX51_PAD_I2C1_CLK = 106,
|
||||
MX51_PAD_I2C1_DAT = 107,
|
||||
MX51_PAD_AUD3_BB_TXD = 108,
|
||||
MX51_PAD_AUD3_BB_RXD = 109,
|
||||
MX51_PAD_AUD3_BB_CK = 110,
|
||||
MX51_PAD_AUD3_BB_FS = 111,
|
||||
MX51_PAD_CSPI1_MOSI = 112,
|
||||
MX51_PAD_CSPI1_MISO = 113,
|
||||
MX51_PAD_CSPI1_SS0 = 114,
|
||||
MX51_PAD_CSPI1_SS1 = 115,
|
||||
MX51_PAD_CSPI1_RDY = 116,
|
||||
MX51_PAD_CSPI1_SCLK = 117,
|
||||
MX51_PAD_UART1_RXD = 118,
|
||||
MX51_PAD_UART1_TXD = 119,
|
||||
MX51_PAD_UART1_RTS = 120,
|
||||
MX51_PAD_UART1_CTS = 121,
|
||||
MX51_PAD_UART2_RXD = 122,
|
||||
MX51_PAD_UART2_TXD = 123,
|
||||
MX51_PAD_UART3_RXD = 124,
|
||||
MX51_PAD_UART3_TXD = 125,
|
||||
MX51_PAD_OWIRE_LINE = 126,
|
||||
MX51_PAD_KEY_ROW0 = 127,
|
||||
MX51_PAD_KEY_ROW1 = 128,
|
||||
MX51_PAD_KEY_ROW2 = 129,
|
||||
MX51_PAD_KEY_ROW3 = 130,
|
||||
MX51_PAD_KEY_COL0 = 131,
|
||||
MX51_PAD_KEY_COL1 = 132,
|
||||
MX51_PAD_KEY_COL2 = 133,
|
||||
MX51_PAD_KEY_COL3 = 134,
|
||||
MX51_PAD_KEY_COL4 = 135,
|
||||
MX51_PAD_KEY_COL5 = 136,
|
||||
MX51_PAD_USBH1_CLK = 137,
|
||||
MX51_PAD_USBH1_DIR = 138,
|
||||
MX51_PAD_USBH1_STP = 139,
|
||||
MX51_PAD_USBH1_NXT = 140,
|
||||
MX51_PAD_USBH1_DATA0 = 141,
|
||||
MX51_PAD_USBH1_DATA1 = 142,
|
||||
MX51_PAD_USBH1_DATA2 = 143,
|
||||
MX51_PAD_USBH1_DATA3 = 144,
|
||||
MX51_PAD_USBH1_DATA4 = 145,
|
||||
MX51_PAD_USBH1_DATA5 = 146,
|
||||
MX51_PAD_USBH1_DATA6 = 147,
|
||||
MX51_PAD_USBH1_DATA7 = 148,
|
||||
MX51_PAD_DI1_PIN11 = 149,
|
||||
MX51_PAD_DI1_PIN12 = 150,
|
||||
MX51_PAD_DI1_PIN13 = 151,
|
||||
MX51_PAD_DI1_D0_CS = 152,
|
||||
MX51_PAD_DI1_D1_CS = 153,
|
||||
MX51_PAD_DISPB2_SER_DIN = 154,
|
||||
MX51_PAD_DISPB2_SER_DIO = 155,
|
||||
MX51_PAD_DISPB2_SER_CLK = 156,
|
||||
MX51_PAD_DISPB2_SER_RS = 157,
|
||||
MX51_PAD_DISP1_DAT0 = 158,
|
||||
MX51_PAD_DISP1_DAT1 = 159,
|
||||
MX51_PAD_DISP1_DAT2 = 160,
|
||||
MX51_PAD_DISP1_DAT3 = 161,
|
||||
MX51_PAD_DISP1_DAT4 = 162,
|
||||
MX51_PAD_DISP1_DAT5 = 163,
|
||||
MX51_PAD_DISP1_DAT6 = 164,
|
||||
MX51_PAD_DISP1_DAT7 = 165,
|
||||
MX51_PAD_DISP1_DAT8 = 166,
|
||||
MX51_PAD_DISP1_DAT9 = 167,
|
||||
MX51_PAD_DISP1_DAT10 = 168,
|
||||
MX51_PAD_DISP1_DAT11 = 169,
|
||||
MX51_PAD_DISP1_DAT12 = 170,
|
||||
MX51_PAD_DISP1_DAT13 = 171,
|
||||
MX51_PAD_DISP1_DAT14 = 172,
|
||||
MX51_PAD_DISP1_DAT15 = 173,
|
||||
MX51_PAD_DISP1_DAT16 = 174,
|
||||
MX51_PAD_DISP1_DAT17 = 175,
|
||||
MX51_PAD_DISP1_DAT18 = 176,
|
||||
MX51_PAD_DISP1_DAT19 = 177,
|
||||
MX51_PAD_DISP1_DAT20 = 178,
|
||||
MX51_PAD_DISP1_DAT21 = 179,
|
||||
MX51_PAD_DISP1_DAT22 = 180,
|
||||
MX51_PAD_DISP1_DAT23 = 181,
|
||||
MX51_PAD_DI1_PIN3 = 182,
|
||||
MX51_PAD_DI1_PIN2 = 183,
|
||||
MX51_PAD_DI_GP2 = 184,
|
||||
MX51_PAD_DI_GP3 = 185,
|
||||
MX51_PAD_DI2_PIN4 = 186,
|
||||
MX51_PAD_DI2_PIN2 = 187,
|
||||
MX51_PAD_DI2_PIN3 = 188,
|
||||
MX51_PAD_DI2_DISP_CLK = 189,
|
||||
MX51_PAD_DI_GP4 = 190,
|
||||
MX51_PAD_DISP2_DAT0 = 191,
|
||||
MX51_PAD_DISP2_DAT1 = 192,
|
||||
MX51_PAD_DISP2_DAT2 = 193,
|
||||
MX51_PAD_DISP2_DAT3 = 194,
|
||||
MX51_PAD_DISP2_DAT4 = 195,
|
||||
MX51_PAD_DISP2_DAT5 = 196,
|
||||
MX51_PAD_DISP2_DAT6 = 197,
|
||||
MX51_PAD_DISP2_DAT7 = 198,
|
||||
MX51_PAD_DISP2_DAT8 = 199,
|
||||
MX51_PAD_DISP2_DAT9 = 200,
|
||||
MX51_PAD_DISP2_DAT10 = 201,
|
||||
MX51_PAD_DISP2_DAT11 = 202,
|
||||
MX51_PAD_DISP2_DAT12 = 203,
|
||||
MX51_PAD_DISP2_DAT13 = 204,
|
||||
MX51_PAD_DISP2_DAT14 = 205,
|
||||
MX51_PAD_DISP2_DAT15 = 206,
|
||||
MX51_PAD_SD1_CMD = 207,
|
||||
MX51_PAD_SD1_CLK = 208,
|
||||
MX51_PAD_SD1_DATA0 = 209,
|
||||
MX51_PAD_EIM_DA0 = 210,
|
||||
MX51_PAD_EIM_DA1 = 211,
|
||||
MX51_PAD_EIM_DA2 = 212,
|
||||
MX51_PAD_EIM_DA3 = 213,
|
||||
MX51_PAD_SD1_DATA1 = 214,
|
||||
MX51_PAD_EIM_DA4 = 215,
|
||||
MX51_PAD_EIM_DA5 = 216,
|
||||
MX51_PAD_EIM_DA6 = 217,
|
||||
MX51_PAD_EIM_DA7 = 218,
|
||||
MX51_PAD_SD1_DATA2 = 219,
|
||||
MX51_PAD_EIM_DA10 = 220,
|
||||
MX51_PAD_EIM_DA11 = 221,
|
||||
MX51_PAD_EIM_DA8 = 222,
|
||||
MX51_PAD_EIM_DA9 = 223,
|
||||
MX51_PAD_SD1_DATA3 = 224,
|
||||
MX51_PAD_GPIO1_0 = 225,
|
||||
MX51_PAD_GPIO1_1 = 226,
|
||||
MX51_PAD_EIM_DA12 = 227,
|
||||
MX51_PAD_EIM_DA13 = 228,
|
||||
MX51_PAD_EIM_DA14 = 229,
|
||||
MX51_PAD_EIM_DA15 = 230,
|
||||
MX51_PAD_SD2_CMD = 231,
|
||||
MX51_PAD_SD2_CLK = 232,
|
||||
MX51_PAD_SD2_DATA0 = 233,
|
||||
MX51_PAD_SD2_DATA1 = 234,
|
||||
MX51_PAD_SD2_DATA2 = 235,
|
||||
MX51_PAD_SD2_DATA3 = 236,
|
||||
MX51_PAD_GPIO1_2 = 237,
|
||||
MX51_PAD_GPIO1_3 = 238,
|
||||
MX51_PAD_PMIC_INT_REQ = 239,
|
||||
MX51_PAD_GPIO1_4 = 240,
|
||||
MX51_PAD_GPIO1_5 = 241,
|
||||
MX51_PAD_GPIO1_6 = 242,
|
||||
MX51_PAD_GPIO1_7 = 243,
|
||||
MX51_PAD_GPIO1_8 = 244,
|
||||
MX51_PAD_GPIO1_9 = 245,
|
||||
MX51_PAD_EIM_D16 = 0,
|
||||
MX51_PAD_EIM_D17 = 1,
|
||||
MX51_PAD_EIM_D18 = 2,
|
||||
MX51_PAD_EIM_D19 = 3,
|
||||
MX51_PAD_EIM_D20 = 4,
|
||||
MX51_PAD_EIM_D21 = 5,
|
||||
MX51_PAD_EIM_D22 = 6,
|
||||
MX51_PAD_EIM_D23 = 7,
|
||||
MX51_PAD_EIM_D24 = 8,
|
||||
MX51_PAD_EIM_D25 = 9,
|
||||
MX51_PAD_EIM_D26 = 10,
|
||||
MX51_PAD_EIM_D27 = 11,
|
||||
MX51_PAD_EIM_D28 = 12,
|
||||
MX51_PAD_EIM_D29 = 13,
|
||||
MX51_PAD_EIM_D30 = 14,
|
||||
MX51_PAD_EIM_D31 = 15,
|
||||
MX51_PAD_EIM_A16 = 16,
|
||||
MX51_PAD_EIM_A17 = 17,
|
||||
MX51_PAD_EIM_A18 = 18,
|
||||
MX51_PAD_EIM_A19 = 19,
|
||||
MX51_PAD_EIM_A20 = 20,
|
||||
MX51_PAD_EIM_A21 = 21,
|
||||
MX51_PAD_EIM_A22 = 22,
|
||||
MX51_PAD_EIM_A23 = 23,
|
||||
MX51_PAD_EIM_A24 = 24,
|
||||
MX51_PAD_EIM_A25 = 25,
|
||||
MX51_PAD_EIM_A26 = 26,
|
||||
MX51_PAD_EIM_A27 = 27,
|
||||
MX51_PAD_EIM_EB0 = 28,
|
||||
MX51_PAD_EIM_EB1 = 29,
|
||||
MX51_PAD_EIM_EB2 = 30,
|
||||
MX51_PAD_EIM_EB3 = 31,
|
||||
MX51_PAD_EIM_OE = 32,
|
||||
MX51_PAD_EIM_CS0 = 33,
|
||||
MX51_PAD_EIM_CS1 = 34,
|
||||
MX51_PAD_EIM_CS2 = 35,
|
||||
MX51_PAD_EIM_CS3 = 36,
|
||||
MX51_PAD_EIM_CS4 = 37,
|
||||
MX51_PAD_EIM_CS5 = 38,
|
||||
MX51_PAD_EIM_DTACK = 39,
|
||||
MX51_PAD_EIM_LBA = 40,
|
||||
MX51_PAD_EIM_CRE = 41,
|
||||
MX51_PAD_DRAM_CS1 = 42,
|
||||
MX51_PAD_NANDF_WE_B = 43,
|
||||
MX51_PAD_NANDF_RE_B = 44,
|
||||
MX51_PAD_NANDF_ALE = 45,
|
||||
MX51_PAD_NANDF_CLE = 46,
|
||||
MX51_PAD_NANDF_WP_B = 47,
|
||||
MX51_PAD_NANDF_RB0 = 48,
|
||||
MX51_PAD_NANDF_RB1 = 49,
|
||||
MX51_PAD_NANDF_RB2 = 50,
|
||||
MX51_PAD_NANDF_RB3 = 51,
|
||||
MX51_PAD_GPIO_NAND = 52,
|
||||
MX51_PAD_NANDF_CS0 = 53,
|
||||
MX51_PAD_NANDF_CS1 = 54,
|
||||
MX51_PAD_NANDF_CS2 = 55,
|
||||
MX51_PAD_NANDF_CS3 = 56,
|
||||
MX51_PAD_NANDF_CS4 = 57,
|
||||
MX51_PAD_NANDF_CS5 = 58,
|
||||
MX51_PAD_NANDF_CS6 = 59,
|
||||
MX51_PAD_NANDF_CS7 = 60,
|
||||
MX51_PAD_NANDF_RDY_INT = 61,
|
||||
MX51_PAD_NANDF_D15 = 62,
|
||||
MX51_PAD_NANDF_D14 = 63,
|
||||
MX51_PAD_NANDF_D13 = 64,
|
||||
MX51_PAD_NANDF_D12 = 65,
|
||||
MX51_PAD_NANDF_D11 = 66,
|
||||
MX51_PAD_NANDF_D10 = 67,
|
||||
MX51_PAD_NANDF_D9 = 68,
|
||||
MX51_PAD_NANDF_D8 = 69,
|
||||
MX51_PAD_NANDF_D7 = 70,
|
||||
MX51_PAD_NANDF_D6 = 71,
|
||||
MX51_PAD_NANDF_D5 = 72,
|
||||
MX51_PAD_NANDF_D4 = 73,
|
||||
MX51_PAD_NANDF_D3 = 74,
|
||||
MX51_PAD_NANDF_D2 = 75,
|
||||
MX51_PAD_NANDF_D1 = 76,
|
||||
MX51_PAD_NANDF_D0 = 77,
|
||||
MX51_PAD_CSI1_D8 = 78,
|
||||
MX51_PAD_CSI1_D9 = 79,
|
||||
MX51_PAD_CSI1_D10 = 80,
|
||||
MX51_PAD_CSI1_D11 = 81,
|
||||
MX51_PAD_CSI1_D12 = 82,
|
||||
MX51_PAD_CSI1_D13 = 83,
|
||||
MX51_PAD_CSI1_D14 = 84,
|
||||
MX51_PAD_CSI1_D15 = 85,
|
||||
MX51_PAD_CSI1_D16 = 86,
|
||||
MX51_PAD_CSI1_D17 = 87,
|
||||
MX51_PAD_CSI1_D18 = 88,
|
||||
MX51_PAD_CSI1_D19 = 89,
|
||||
MX51_PAD_CSI1_VSYNC = 90,
|
||||
MX51_PAD_CSI1_HSYNC = 91,
|
||||
MX51_PAD_CSI1_PIXCLK = 92,
|
||||
MX51_PAD_CSI1_MCLK = 93,
|
||||
MX51_PAD_CSI2_D12 = 94,
|
||||
MX51_PAD_CSI2_D13 = 95,
|
||||
MX51_PAD_CSI2_D14 = 96,
|
||||
MX51_PAD_CSI2_D15 = 97,
|
||||
MX51_PAD_CSI2_D16 = 98,
|
||||
MX51_PAD_CSI2_D17 = 99,
|
||||
MX51_PAD_CSI2_D18 = 100,
|
||||
MX51_PAD_CSI2_D19 = 101,
|
||||
MX51_PAD_CSI2_VSYNC = 102,
|
||||
MX51_PAD_CSI2_HSYNC = 103,
|
||||
MX51_PAD_CSI2_PIXCLK = 104,
|
||||
MX51_PAD_I2C1_CLK = 105,
|
||||
MX51_PAD_I2C1_DAT = 106,
|
||||
MX51_PAD_AUD3_BB_TXD = 107,
|
||||
MX51_PAD_AUD3_BB_RXD = 108,
|
||||
MX51_PAD_AUD3_BB_CK = 109,
|
||||
MX51_PAD_AUD3_BB_FS = 110,
|
||||
MX51_PAD_CSPI1_MOSI = 111,
|
||||
MX51_PAD_CSPI1_MISO = 112,
|
||||
MX51_PAD_CSPI1_SS0 = 113,
|
||||
MX51_PAD_CSPI1_SS1 = 114,
|
||||
MX51_PAD_CSPI1_RDY = 115,
|
||||
MX51_PAD_CSPI1_SCLK = 116,
|
||||
MX51_PAD_UART1_RXD = 117,
|
||||
MX51_PAD_UART1_TXD = 118,
|
||||
MX51_PAD_UART1_RTS = 119,
|
||||
MX51_PAD_UART1_CTS = 120,
|
||||
MX51_PAD_UART2_RXD = 121,
|
||||
MX51_PAD_UART2_TXD = 122,
|
||||
MX51_PAD_UART3_RXD = 123,
|
||||
MX51_PAD_UART3_TXD = 124,
|
||||
MX51_PAD_OWIRE_LINE = 125,
|
||||
MX51_PAD_KEY_ROW0 = 126,
|
||||
MX51_PAD_KEY_ROW1 = 127,
|
||||
MX51_PAD_KEY_ROW2 = 128,
|
||||
MX51_PAD_KEY_ROW3 = 129,
|
||||
MX51_PAD_KEY_COL0 = 130,
|
||||
MX51_PAD_KEY_COL1 = 131,
|
||||
MX51_PAD_KEY_COL2 = 132,
|
||||
MX51_PAD_KEY_COL3 = 133,
|
||||
MX51_PAD_KEY_COL4 = 134,
|
||||
MX51_PAD_KEY_COL5 = 135,
|
||||
MX51_PAD_USBH1_CLK = 136,
|
||||
MX51_PAD_USBH1_DIR = 137,
|
||||
MX51_PAD_USBH1_STP = 138,
|
||||
MX51_PAD_USBH1_NXT = 139,
|
||||
MX51_PAD_USBH1_DATA0 = 140,
|
||||
MX51_PAD_USBH1_DATA1 = 141,
|
||||
MX51_PAD_USBH1_DATA2 = 142,
|
||||
MX51_PAD_USBH1_DATA3 = 143,
|
||||
MX51_PAD_USBH1_DATA4 = 144,
|
||||
MX51_PAD_USBH1_DATA5 = 145,
|
||||
MX51_PAD_USBH1_DATA6 = 146,
|
||||
MX51_PAD_USBH1_DATA7 = 147,
|
||||
MX51_PAD_DI1_PIN11 = 148,
|
||||
MX51_PAD_DI1_PIN12 = 149,
|
||||
MX51_PAD_DI1_PIN13 = 150,
|
||||
MX51_PAD_DI1_D0_CS = 151,
|
||||
MX51_PAD_DI1_D1_CS = 152,
|
||||
MX51_PAD_DISPB2_SER_DIN = 153,
|
||||
MX51_PAD_DISPB2_SER_DIO = 154,
|
||||
MX51_PAD_DISPB2_SER_CLK = 155,
|
||||
MX51_PAD_DISPB2_SER_RS = 156,
|
||||
MX51_PAD_DISP1_DAT0 = 157,
|
||||
MX51_PAD_DISP1_DAT1 = 158,
|
||||
MX51_PAD_DISP1_DAT2 = 159,
|
||||
MX51_PAD_DISP1_DAT3 = 160,
|
||||
MX51_PAD_DISP1_DAT4 = 161,
|
||||
MX51_PAD_DISP1_DAT5 = 162,
|
||||
MX51_PAD_DISP1_DAT6 = 163,
|
||||
MX51_PAD_DISP1_DAT7 = 164,
|
||||
MX51_PAD_DISP1_DAT8 = 165,
|
||||
MX51_PAD_DISP1_DAT9 = 166,
|
||||
MX51_PAD_DISP1_DAT10 = 167,
|
||||
MX51_PAD_DISP1_DAT11 = 168,
|
||||
MX51_PAD_DISP1_DAT12 = 169,
|
||||
MX51_PAD_DISP1_DAT13 = 170,
|
||||
MX51_PAD_DISP1_DAT14 = 171,
|
||||
MX51_PAD_DISP1_DAT15 = 172,
|
||||
MX51_PAD_DISP1_DAT16 = 173,
|
||||
MX51_PAD_DISP1_DAT17 = 174,
|
||||
MX51_PAD_DISP1_DAT18 = 175,
|
||||
MX51_PAD_DISP1_DAT19 = 176,
|
||||
MX51_PAD_DISP1_DAT20 = 177,
|
||||
MX51_PAD_DISP1_DAT21 = 178,
|
||||
MX51_PAD_DISP1_DAT22 = 179,
|
||||
MX51_PAD_DISP1_DAT23 = 180,
|
||||
MX51_PAD_DI1_PIN3 = 181,
|
||||
MX51_PAD_DI1_PIN2 = 182,
|
||||
MX51_PAD_DI_GP2 = 183,
|
||||
MX51_PAD_DI_GP3 = 184,
|
||||
MX51_PAD_DI2_PIN4 = 185,
|
||||
MX51_PAD_DI2_PIN2 = 186,
|
||||
MX51_PAD_DI2_PIN3 = 187,
|
||||
MX51_PAD_DI2_DISP_CLK = 188,
|
||||
MX51_PAD_DI_GP4 = 189,
|
||||
MX51_PAD_DISP2_DAT0 = 190,
|
||||
MX51_PAD_DISP2_DAT1 = 191,
|
||||
MX51_PAD_DISP2_DAT2 = 192,
|
||||
MX51_PAD_DISP2_DAT3 = 193,
|
||||
MX51_PAD_DISP2_DAT4 = 194,
|
||||
MX51_PAD_DISP2_DAT5 = 195,
|
||||
MX51_PAD_DISP2_DAT6 = 196,
|
||||
MX51_PAD_DISP2_DAT7 = 197,
|
||||
MX51_PAD_DISP2_DAT8 = 198,
|
||||
MX51_PAD_DISP2_DAT9 = 199,
|
||||
MX51_PAD_DISP2_DAT10 = 200,
|
||||
MX51_PAD_DISP2_DAT11 = 201,
|
||||
MX51_PAD_DISP2_DAT12 = 202,
|
||||
MX51_PAD_DISP2_DAT13 = 203,
|
||||
MX51_PAD_DISP2_DAT14 = 204,
|
||||
MX51_PAD_DISP2_DAT15 = 205,
|
||||
MX51_PAD_SD1_CMD = 206,
|
||||
MX51_PAD_SD1_CLK = 207,
|
||||
MX51_PAD_SD1_DATA0 = 208,
|
||||
MX51_PAD_EIM_DA0 = 209,
|
||||
MX51_PAD_EIM_DA1 = 210,
|
||||
MX51_PAD_EIM_DA2 = 211,
|
||||
MX51_PAD_EIM_DA3 = 212,
|
||||
MX51_PAD_SD1_DATA1 = 213,
|
||||
MX51_PAD_EIM_DA4 = 214,
|
||||
MX51_PAD_EIM_DA5 = 215,
|
||||
MX51_PAD_EIM_DA6 = 216,
|
||||
MX51_PAD_EIM_DA7 = 217,
|
||||
MX51_PAD_SD1_DATA2 = 218,
|
||||
MX51_PAD_EIM_DA10 = 219,
|
||||
MX51_PAD_EIM_DA11 = 220,
|
||||
MX51_PAD_EIM_DA8 = 221,
|
||||
MX51_PAD_EIM_DA9 = 222,
|
||||
MX51_PAD_SD1_DATA3 = 223,
|
||||
MX51_PAD_GPIO1_0 = 224,
|
||||
MX51_PAD_GPIO1_1 = 225,
|
||||
MX51_PAD_EIM_DA12 = 226,
|
||||
MX51_PAD_EIM_DA13 = 227,
|
||||
MX51_PAD_EIM_DA14 = 228,
|
||||
MX51_PAD_EIM_DA15 = 229,
|
||||
MX51_PAD_SD2_CMD = 230,
|
||||
MX51_PAD_SD2_CLK = 231,
|
||||
MX51_PAD_SD2_DATA0 = 232,
|
||||
MX51_PAD_SD2_DATA1 = 233,
|
||||
MX51_PAD_SD2_DATA2 = 234,
|
||||
MX51_PAD_SD2_DATA3 = 235,
|
||||
MX51_PAD_GPIO1_2 = 236,
|
||||
MX51_PAD_GPIO1_3 = 237,
|
||||
MX51_PAD_PMIC_INT_REQ = 238,
|
||||
MX51_PAD_GPIO1_4 = 239,
|
||||
MX51_PAD_GPIO1_5 = 240,
|
||||
MX51_PAD_GPIO1_6 = 241,
|
||||
MX51_PAD_GPIO1_7 = 242,
|
||||
MX51_PAD_GPIO1_8 = 243,
|
||||
MX51_PAD_GPIO1_9 = 244,
|
||||
};
|
||||
|
||||
/* imx51 register maps */
|
||||
|
|
|
|||
|
|
@ -23,207 +23,207 @@
|
|||
#include "pinctrl-imx.h"
|
||||
|
||||
enum imx53_pads {
|
||||
MX53_PAD_GPIO_19 = 1,
|
||||
MX53_PAD_KEY_COL0 = 2,
|
||||
MX53_PAD_KEY_ROW0 = 3,
|
||||
MX53_PAD_KEY_COL1 = 4,
|
||||
MX53_PAD_KEY_ROW1 = 5,
|
||||
MX53_PAD_KEY_COL2 = 6,
|
||||
MX53_PAD_KEY_ROW2 = 7,
|
||||
MX53_PAD_KEY_COL3 = 8,
|
||||
MX53_PAD_KEY_ROW3 = 9,
|
||||
MX53_PAD_KEY_COL4 = 10,
|
||||
MX53_PAD_KEY_ROW4 = 11,
|
||||
MX53_PAD_DI0_DISP_CLK = 12,
|
||||
MX53_PAD_DI0_PIN15 = 13,
|
||||
MX53_PAD_DI0_PIN2 = 14,
|
||||
MX53_PAD_DI0_PIN3 = 15,
|
||||
MX53_PAD_DI0_PIN4 = 16,
|
||||
MX53_PAD_DISP0_DAT0 = 17,
|
||||
MX53_PAD_DISP0_DAT1 = 18,
|
||||
MX53_PAD_DISP0_DAT2 = 19,
|
||||
MX53_PAD_DISP0_DAT3 = 20,
|
||||
MX53_PAD_DISP0_DAT4 = 21,
|
||||
MX53_PAD_DISP0_DAT5 = 22,
|
||||
MX53_PAD_DISP0_DAT6 = 23,
|
||||
MX53_PAD_DISP0_DAT7 = 24,
|
||||
MX53_PAD_DISP0_DAT8 = 25,
|
||||
MX53_PAD_DISP0_DAT9 = 26,
|
||||
MX53_PAD_DISP0_DAT10 = 27,
|
||||
MX53_PAD_DISP0_DAT11 = 28,
|
||||
MX53_PAD_DISP0_DAT12 = 29,
|
||||
MX53_PAD_DISP0_DAT13 = 30,
|
||||
MX53_PAD_DISP0_DAT14 = 31,
|
||||
MX53_PAD_DISP0_DAT15 = 32,
|
||||
MX53_PAD_DISP0_DAT16 = 33,
|
||||
MX53_PAD_DISP0_DAT17 = 34,
|
||||
MX53_PAD_DISP0_DAT18 = 35,
|
||||
MX53_PAD_DISP0_DAT19 = 36,
|
||||
MX53_PAD_DISP0_DAT20 = 37,
|
||||
MX53_PAD_DISP0_DAT21 = 38,
|
||||
MX53_PAD_DISP0_DAT22 = 39,
|
||||
MX53_PAD_DISP0_DAT23 = 40,
|
||||
MX53_PAD_CSI0_PIXCLK = 41,
|
||||
MX53_PAD_CSI0_MCLK = 42,
|
||||
MX53_PAD_CSI0_DATA_EN = 43,
|
||||
MX53_PAD_CSI0_VSYNC = 44,
|
||||
MX53_PAD_CSI0_DAT4 = 45,
|
||||
MX53_PAD_CSI0_DAT5 = 46,
|
||||
MX53_PAD_CSI0_DAT6 = 47,
|
||||
MX53_PAD_CSI0_DAT7 = 48,
|
||||
MX53_PAD_CSI0_DAT8 = 49,
|
||||
MX53_PAD_CSI0_DAT9 = 50,
|
||||
MX53_PAD_CSI0_DAT10 = 51,
|
||||
MX53_PAD_CSI0_DAT11 = 52,
|
||||
MX53_PAD_CSI0_DAT12 = 53,
|
||||
MX53_PAD_CSI0_DAT13 = 54,
|
||||
MX53_PAD_CSI0_DAT14 = 55,
|
||||
MX53_PAD_CSI0_DAT15 = 56,
|
||||
MX53_PAD_CSI0_DAT16 = 57,
|
||||
MX53_PAD_CSI0_DAT17 = 58,
|
||||
MX53_PAD_CSI0_DAT18 = 59,
|
||||
MX53_PAD_CSI0_DAT19 = 60,
|
||||
MX53_PAD_EIM_A25 = 61,
|
||||
MX53_PAD_EIM_EB2 = 62,
|
||||
MX53_PAD_EIM_D16 = 63,
|
||||
MX53_PAD_EIM_D17 = 64,
|
||||
MX53_PAD_EIM_D18 = 65,
|
||||
MX53_PAD_EIM_D19 = 66,
|
||||
MX53_PAD_EIM_D20 = 67,
|
||||
MX53_PAD_EIM_D21 = 68,
|
||||
MX53_PAD_EIM_D22 = 69,
|
||||
MX53_PAD_EIM_D23 = 70,
|
||||
MX53_PAD_EIM_EB3 = 71,
|
||||
MX53_PAD_EIM_D24 = 72,
|
||||
MX53_PAD_EIM_D25 = 73,
|
||||
MX53_PAD_EIM_D26 = 74,
|
||||
MX53_PAD_EIM_D27 = 75,
|
||||
MX53_PAD_EIM_D28 = 76,
|
||||
MX53_PAD_EIM_D29 = 77,
|
||||
MX53_PAD_EIM_D30 = 78,
|
||||
MX53_PAD_EIM_D31 = 79,
|
||||
MX53_PAD_EIM_A24 = 80,
|
||||
MX53_PAD_EIM_A23 = 81,
|
||||
MX53_PAD_EIM_A22 = 82,
|
||||
MX53_PAD_EIM_A21 = 83,
|
||||
MX53_PAD_EIM_A20 = 84,
|
||||
MX53_PAD_EIM_A19 = 85,
|
||||
MX53_PAD_EIM_A18 = 86,
|
||||
MX53_PAD_EIM_A17 = 87,
|
||||
MX53_PAD_EIM_A16 = 88,
|
||||
MX53_PAD_EIM_CS0 = 89,
|
||||
MX53_PAD_EIM_CS1 = 90,
|
||||
MX53_PAD_EIM_OE = 91,
|
||||
MX53_PAD_EIM_RW = 92,
|
||||
MX53_PAD_EIM_LBA = 93,
|
||||
MX53_PAD_EIM_EB0 = 94,
|
||||
MX53_PAD_EIM_EB1 = 95,
|
||||
MX53_PAD_EIM_DA0 = 96,
|
||||
MX53_PAD_EIM_DA1 = 97,
|
||||
MX53_PAD_EIM_DA2 = 98,
|
||||
MX53_PAD_EIM_DA3 = 99,
|
||||
MX53_PAD_EIM_DA4 = 100,
|
||||
MX53_PAD_EIM_DA5 = 101,
|
||||
MX53_PAD_EIM_DA6 = 102,
|
||||
MX53_PAD_EIM_DA7 = 103,
|
||||
MX53_PAD_EIM_DA8 = 104,
|
||||
MX53_PAD_EIM_DA9 = 105,
|
||||
MX53_PAD_EIM_DA10 = 106,
|
||||
MX53_PAD_EIM_DA11 = 107,
|
||||
MX53_PAD_EIM_DA12 = 108,
|
||||
MX53_PAD_EIM_DA13 = 109,
|
||||
MX53_PAD_EIM_DA14 = 110,
|
||||
MX53_PAD_EIM_DA15 = 111,
|
||||
MX53_PAD_NANDF_WE_B = 112,
|
||||
MX53_PAD_NANDF_RE_B = 113,
|
||||
MX53_PAD_EIM_WAIT = 114,
|
||||
MX53_PAD_LVDS1_TX3_P = 115,
|
||||
MX53_PAD_LVDS1_TX2_P = 116,
|
||||
MX53_PAD_LVDS1_CLK_P = 117,
|
||||
MX53_PAD_LVDS1_TX1_P = 118,
|
||||
MX53_PAD_LVDS1_TX0_P = 119,
|
||||
MX53_PAD_LVDS0_TX3_P = 120,
|
||||
MX53_PAD_LVDS0_CLK_P = 121,
|
||||
MX53_PAD_LVDS0_TX2_P = 122,
|
||||
MX53_PAD_LVDS0_TX1_P = 123,
|
||||
MX53_PAD_LVDS0_TX0_P = 124,
|
||||
MX53_PAD_GPIO_10 = 125,
|
||||
MX53_PAD_GPIO_11 = 126,
|
||||
MX53_PAD_GPIO_12 = 127,
|
||||
MX53_PAD_GPIO_13 = 128,
|
||||
MX53_PAD_GPIO_14 = 129,
|
||||
MX53_PAD_NANDF_CLE = 130,
|
||||
MX53_PAD_NANDF_ALE = 131,
|
||||
MX53_PAD_NANDF_WP_B = 132,
|
||||
MX53_PAD_NANDF_RB0 = 133,
|
||||
MX53_PAD_NANDF_CS0 = 134,
|
||||
MX53_PAD_NANDF_CS1 = 135,
|
||||
MX53_PAD_NANDF_CS2 = 136,
|
||||
MX53_PAD_NANDF_CS3 = 137,
|
||||
MX53_PAD_FEC_MDIO = 138,
|
||||
MX53_PAD_FEC_REF_CLK = 139,
|
||||
MX53_PAD_FEC_RX_ER = 140,
|
||||
MX53_PAD_FEC_CRS_DV = 141,
|
||||
MX53_PAD_FEC_RXD1 = 142,
|
||||
MX53_PAD_FEC_RXD0 = 143,
|
||||
MX53_PAD_FEC_TX_EN = 144,
|
||||
MX53_PAD_FEC_TXD1 = 145,
|
||||
MX53_PAD_FEC_TXD0 = 146,
|
||||
MX53_PAD_FEC_MDC = 147,
|
||||
MX53_PAD_PATA_DIOW = 148,
|
||||
MX53_PAD_PATA_DMACK = 149,
|
||||
MX53_PAD_PATA_DMARQ = 150,
|
||||
MX53_PAD_PATA_BUFFER_EN = 151,
|
||||
MX53_PAD_PATA_INTRQ = 152,
|
||||
MX53_PAD_PATA_DIOR = 153,
|
||||
MX53_PAD_PATA_RESET_B = 154,
|
||||
MX53_PAD_PATA_IORDY = 155,
|
||||
MX53_PAD_PATA_DA_0 = 156,
|
||||
MX53_PAD_PATA_DA_1 = 157,
|
||||
MX53_PAD_PATA_DA_2 = 158,
|
||||
MX53_PAD_PATA_CS_0 = 159,
|
||||
MX53_PAD_PATA_CS_1 = 160,
|
||||
MX53_PAD_PATA_DATA0 = 161,
|
||||
MX53_PAD_PATA_DATA1 = 162,
|
||||
MX53_PAD_PATA_DATA2 = 163,
|
||||
MX53_PAD_PATA_DATA3 = 164,
|
||||
MX53_PAD_PATA_DATA4 = 165,
|
||||
MX53_PAD_PATA_DATA5 = 166,
|
||||
MX53_PAD_PATA_DATA6 = 167,
|
||||
MX53_PAD_PATA_DATA7 = 168,
|
||||
MX53_PAD_PATA_DATA8 = 169,
|
||||
MX53_PAD_PATA_DATA9 = 170,
|
||||
MX53_PAD_PATA_DATA10 = 171,
|
||||
MX53_PAD_PATA_DATA11 = 172,
|
||||
MX53_PAD_PATA_DATA12 = 173,
|
||||
MX53_PAD_PATA_DATA13 = 174,
|
||||
MX53_PAD_PATA_DATA14 = 175,
|
||||
MX53_PAD_PATA_DATA15 = 176,
|
||||
MX53_PAD_SD1_DATA0 = 177,
|
||||
MX53_PAD_SD1_DATA1 = 178,
|
||||
MX53_PAD_SD1_CMD = 179,
|
||||
MX53_PAD_SD1_DATA2 = 180,
|
||||
MX53_PAD_SD1_CLK = 181,
|
||||
MX53_PAD_SD1_DATA3 = 182,
|
||||
MX53_PAD_SD2_CLK = 183,
|
||||
MX53_PAD_SD2_CMD = 184,
|
||||
MX53_PAD_SD2_DATA3 = 185,
|
||||
MX53_PAD_SD2_DATA2 = 186,
|
||||
MX53_PAD_SD2_DATA1 = 187,
|
||||
MX53_PAD_SD2_DATA0 = 188,
|
||||
MX53_PAD_GPIO_0 = 189,
|
||||
MX53_PAD_GPIO_1 = 190,
|
||||
MX53_PAD_GPIO_9 = 191,
|
||||
MX53_PAD_GPIO_3 = 192,
|
||||
MX53_PAD_GPIO_6 = 193,
|
||||
MX53_PAD_GPIO_2 = 194,
|
||||
MX53_PAD_GPIO_4 = 195,
|
||||
MX53_PAD_GPIO_5 = 196,
|
||||
MX53_PAD_GPIO_7 = 197,
|
||||
MX53_PAD_GPIO_8 = 198,
|
||||
MX53_PAD_GPIO_16 = 199,
|
||||
MX53_PAD_GPIO_17 = 200,
|
||||
MX53_PAD_GPIO_18 = 201,
|
||||
MX53_PAD_GPIO_19 = 0,
|
||||
MX53_PAD_KEY_COL0 = 1,
|
||||
MX53_PAD_KEY_ROW0 = 2,
|
||||
MX53_PAD_KEY_COL1 = 3,
|
||||
MX53_PAD_KEY_ROW1 = 4,
|
||||
MX53_PAD_KEY_COL2 = 5,
|
||||
MX53_PAD_KEY_ROW2 = 6,
|
||||
MX53_PAD_KEY_COL3 = 7,
|
||||
MX53_PAD_KEY_ROW3 = 8,
|
||||
MX53_PAD_KEY_COL4 = 9,
|
||||
MX53_PAD_KEY_ROW4 = 10,
|
||||
MX53_PAD_DI0_DISP_CLK = 11,
|
||||
MX53_PAD_DI0_PIN15 = 12,
|
||||
MX53_PAD_DI0_PIN2 = 13,
|
||||
MX53_PAD_DI0_PIN3 = 14,
|
||||
MX53_PAD_DI0_PIN4 = 15,
|
||||
MX53_PAD_DISP0_DAT0 = 16,
|
||||
MX53_PAD_DISP0_DAT1 = 17,
|
||||
MX53_PAD_DISP0_DAT2 = 18,
|
||||
MX53_PAD_DISP0_DAT3 = 19,
|
||||
MX53_PAD_DISP0_DAT4 = 20,
|
||||
MX53_PAD_DISP0_DAT5 = 21,
|
||||
MX53_PAD_DISP0_DAT6 = 22,
|
||||
MX53_PAD_DISP0_DAT7 = 23,
|
||||
MX53_PAD_DISP0_DAT8 = 24,
|
||||
MX53_PAD_DISP0_DAT9 = 25,
|
||||
MX53_PAD_DISP0_DAT10 = 26,
|
||||
MX53_PAD_DISP0_DAT11 = 27,
|
||||
MX53_PAD_DISP0_DAT12 = 28,
|
||||
MX53_PAD_DISP0_DAT13 = 29,
|
||||
MX53_PAD_DISP0_DAT14 = 30,
|
||||
MX53_PAD_DISP0_DAT15 = 31,
|
||||
MX53_PAD_DISP0_DAT16 = 32,
|
||||
MX53_PAD_DISP0_DAT17 = 33,
|
||||
MX53_PAD_DISP0_DAT18 = 34,
|
||||
MX53_PAD_DISP0_DAT19 = 35,
|
||||
MX53_PAD_DISP0_DAT20 = 36,
|
||||
MX53_PAD_DISP0_DAT21 = 37,
|
||||
MX53_PAD_DISP0_DAT22 = 38,
|
||||
MX53_PAD_DISP0_DAT23 = 39,
|
||||
MX53_PAD_CSI0_PIXCLK = 40,
|
||||
MX53_PAD_CSI0_MCLK = 41,
|
||||
MX53_PAD_CSI0_DATA_EN = 42,
|
||||
MX53_PAD_CSI0_VSYNC = 43,
|
||||
MX53_PAD_CSI0_DAT4 = 44,
|
||||
MX53_PAD_CSI0_DAT5 = 45,
|
||||
MX53_PAD_CSI0_DAT6 = 46,
|
||||
MX53_PAD_CSI0_DAT7 = 47,
|
||||
MX53_PAD_CSI0_DAT8 = 48,
|
||||
MX53_PAD_CSI0_DAT9 = 49,
|
||||
MX53_PAD_CSI0_DAT10 = 50,
|
||||
MX53_PAD_CSI0_DAT11 = 51,
|
||||
MX53_PAD_CSI0_DAT12 = 52,
|
||||
MX53_PAD_CSI0_DAT13 = 53,
|
||||
MX53_PAD_CSI0_DAT14 = 54,
|
||||
MX53_PAD_CSI0_DAT15 = 55,
|
||||
MX53_PAD_CSI0_DAT16 = 56,
|
||||
MX53_PAD_CSI0_DAT17 = 57,
|
||||
MX53_PAD_CSI0_DAT18 = 58,
|
||||
MX53_PAD_CSI0_DAT19 = 59,
|
||||
MX53_PAD_EIM_A25 = 60,
|
||||
MX53_PAD_EIM_EB2 = 61,
|
||||
MX53_PAD_EIM_D16 = 62,
|
||||
MX53_PAD_EIM_D17 = 63,
|
||||
MX53_PAD_EIM_D18 = 64,
|
||||
MX53_PAD_EIM_D19 = 65,
|
||||
MX53_PAD_EIM_D20 = 66,
|
||||
MX53_PAD_EIM_D21 = 67,
|
||||
MX53_PAD_EIM_D22 = 68,
|
||||
MX53_PAD_EIM_D23 = 69,
|
||||
MX53_PAD_EIM_EB3 = 70,
|
||||
MX53_PAD_EIM_D24 = 71,
|
||||
MX53_PAD_EIM_D25 = 72,
|
||||
MX53_PAD_EIM_D26 = 73,
|
||||
MX53_PAD_EIM_D27 = 74,
|
||||
MX53_PAD_EIM_D28 = 75,
|
||||
MX53_PAD_EIM_D29 = 76,
|
||||
MX53_PAD_EIM_D30 = 77,
|
||||
MX53_PAD_EIM_D31 = 78,
|
||||
MX53_PAD_EIM_A24 = 79,
|
||||
MX53_PAD_EIM_A23 = 80,
|
||||
MX53_PAD_EIM_A22 = 81,
|
||||
MX53_PAD_EIM_A21 = 82,
|
||||
MX53_PAD_EIM_A20 = 83,
|
||||
MX53_PAD_EIM_A19 = 84,
|
||||
MX53_PAD_EIM_A18 = 85,
|
||||
MX53_PAD_EIM_A17 = 86,
|
||||
MX53_PAD_EIM_A16 = 87,
|
||||
MX53_PAD_EIM_CS0 = 88,
|
||||
MX53_PAD_EIM_CS1 = 89,
|
||||
MX53_PAD_EIM_OE = 90,
|
||||
MX53_PAD_EIM_RW = 91,
|
||||
MX53_PAD_EIM_LBA = 92,
|
||||
MX53_PAD_EIM_EB0 = 93,
|
||||
MX53_PAD_EIM_EB1 = 94,
|
||||
MX53_PAD_EIM_DA0 = 95,
|
||||
MX53_PAD_EIM_DA1 = 96,
|
||||
MX53_PAD_EIM_DA2 = 97,
|
||||
MX53_PAD_EIM_DA3 = 98,
|
||||
MX53_PAD_EIM_DA4 = 99,
|
||||
MX53_PAD_EIM_DA5 = 100,
|
||||
MX53_PAD_EIM_DA6 = 101,
|
||||
MX53_PAD_EIM_DA7 = 102,
|
||||
MX53_PAD_EIM_DA8 = 103,
|
||||
MX53_PAD_EIM_DA9 = 104,
|
||||
MX53_PAD_EIM_DA10 = 105,
|
||||
MX53_PAD_EIM_DA11 = 106,
|
||||
MX53_PAD_EIM_DA12 = 107,
|
||||
MX53_PAD_EIM_DA13 = 108,
|
||||
MX53_PAD_EIM_DA14 = 109,
|
||||
MX53_PAD_EIM_DA15 = 110,
|
||||
MX53_PAD_NANDF_WE_B = 111,
|
||||
MX53_PAD_NANDF_RE_B = 112,
|
||||
MX53_PAD_EIM_WAIT = 113,
|
||||
MX53_PAD_LVDS1_TX3_P = 114,
|
||||
MX53_PAD_LVDS1_TX2_P = 115,
|
||||
MX53_PAD_LVDS1_CLK_P = 116,
|
||||
MX53_PAD_LVDS1_TX1_P = 117,
|
||||
MX53_PAD_LVDS1_TX0_P = 118,
|
||||
MX53_PAD_LVDS0_TX3_P = 119,
|
||||
MX53_PAD_LVDS0_CLK_P = 120,
|
||||
MX53_PAD_LVDS0_TX2_P = 121,
|
||||
MX53_PAD_LVDS0_TX1_P = 122,
|
||||
MX53_PAD_LVDS0_TX0_P = 123,
|
||||
MX53_PAD_GPIO_10 = 124,
|
||||
MX53_PAD_GPIO_11 = 125,
|
||||
MX53_PAD_GPIO_12 = 126,
|
||||
MX53_PAD_GPIO_13 = 127,
|
||||
MX53_PAD_GPIO_14 = 128,
|
||||
MX53_PAD_NANDF_CLE = 129,
|
||||
MX53_PAD_NANDF_ALE = 130,
|
||||
MX53_PAD_NANDF_WP_B = 131,
|
||||
MX53_PAD_NANDF_RB0 = 132,
|
||||
MX53_PAD_NANDF_CS0 = 133,
|
||||
MX53_PAD_NANDF_CS1 = 134,
|
||||
MX53_PAD_NANDF_CS2 = 135,
|
||||
MX53_PAD_NANDF_CS3 = 136,
|
||||
MX53_PAD_FEC_MDIO = 137,
|
||||
MX53_PAD_FEC_REF_CLK = 138,
|
||||
MX53_PAD_FEC_RX_ER = 139,
|
||||
MX53_PAD_FEC_CRS_DV = 140,
|
||||
MX53_PAD_FEC_RXD1 = 141,
|
||||
MX53_PAD_FEC_RXD0 = 142,
|
||||
MX53_PAD_FEC_TX_EN = 143,
|
||||
MX53_PAD_FEC_TXD1 = 144,
|
||||
MX53_PAD_FEC_TXD0 = 145,
|
||||
MX53_PAD_FEC_MDC = 146,
|
||||
MX53_PAD_PATA_DIOW = 147,
|
||||
MX53_PAD_PATA_DMACK = 148,
|
||||
MX53_PAD_PATA_DMARQ = 149,
|
||||
MX53_PAD_PATA_BUFFER_EN = 150,
|
||||
MX53_PAD_PATA_INTRQ = 151,
|
||||
MX53_PAD_PATA_DIOR = 152,
|
||||
MX53_PAD_PATA_RESET_B = 153,
|
||||
MX53_PAD_PATA_IORDY = 154,
|
||||
MX53_PAD_PATA_DA_0 = 155,
|
||||
MX53_PAD_PATA_DA_1 = 156,
|
||||
MX53_PAD_PATA_DA_2 = 157,
|
||||
MX53_PAD_PATA_CS_0 = 158,
|
||||
MX53_PAD_PATA_CS_1 = 159,
|
||||
MX53_PAD_PATA_DATA0 = 160,
|
||||
MX53_PAD_PATA_DATA1 = 161,
|
||||
MX53_PAD_PATA_DATA2 = 162,
|
||||
MX53_PAD_PATA_DATA3 = 163,
|
||||
MX53_PAD_PATA_DATA4 = 164,
|
||||
MX53_PAD_PATA_DATA5 = 165,
|
||||
MX53_PAD_PATA_DATA6 = 166,
|
||||
MX53_PAD_PATA_DATA7 = 167,
|
||||
MX53_PAD_PATA_DATA8 = 168,
|
||||
MX53_PAD_PATA_DATA9 = 169,
|
||||
MX53_PAD_PATA_DATA10 = 170,
|
||||
MX53_PAD_PATA_DATA11 = 171,
|
||||
MX53_PAD_PATA_DATA12 = 172,
|
||||
MX53_PAD_PATA_DATA13 = 173,
|
||||
MX53_PAD_PATA_DATA14 = 174,
|
||||
MX53_PAD_PATA_DATA15 = 175,
|
||||
MX53_PAD_SD1_DATA0 = 176,
|
||||
MX53_PAD_SD1_DATA1 = 177,
|
||||
MX53_PAD_SD1_CMD = 178,
|
||||
MX53_PAD_SD1_DATA2 = 179,
|
||||
MX53_PAD_SD1_CLK = 180,
|
||||
MX53_PAD_SD1_DATA3 = 181,
|
||||
MX53_PAD_SD2_CLK = 182,
|
||||
MX53_PAD_SD2_CMD = 183,
|
||||
MX53_PAD_SD2_DATA3 = 184,
|
||||
MX53_PAD_SD2_DATA2 = 185,
|
||||
MX53_PAD_SD2_DATA1 = 186,
|
||||
MX53_PAD_SD2_DATA0 = 187,
|
||||
MX53_PAD_GPIO_0 = 188,
|
||||
MX53_PAD_GPIO_1 = 189,
|
||||
MX53_PAD_GPIO_9 = 190,
|
||||
MX53_PAD_GPIO_3 = 191,
|
||||
MX53_PAD_GPIO_6 = 192,
|
||||
MX53_PAD_GPIO_2 = 193,
|
||||
MX53_PAD_GPIO_4 = 194,
|
||||
MX53_PAD_GPIO_5 = 195,
|
||||
MX53_PAD_GPIO_7 = 196,
|
||||
MX53_PAD_GPIO_8 = 197,
|
||||
MX53_PAD_GPIO_16 = 198,
|
||||
MX53_PAD_GPIO_17 = 199,
|
||||
MX53_PAD_GPIO_18 = 200,
|
||||
};
|
||||
|
||||
/* imx53 register maps */
|
||||
|
|
|
|||
|
|
@ -465,6 +465,8 @@ static const unsigned mc4_a_1_pins[] = { DB8500_PIN_AH24, DB8500_PIN_AG25,
|
|||
static const unsigned mc1_a_1_pins[] = { DB8500_PIN_AH16, DB8500_PIN_AG15,
|
||||
DB8500_PIN_AJ15, DB8500_PIN_AG14, DB8500_PIN_AF13, DB8500_PIN_AG13,
|
||||
DB8500_PIN_AH15 };
|
||||
static const unsigned mc1_a_2_pins[] = { DB8500_PIN_AH16, DB8500_PIN_AJ15,
|
||||
DB8500_PIN_AG14, DB8500_PIN_AF13, DB8500_PIN_AG13,DB8500_PIN_AH15 };
|
||||
static const unsigned mc1dir_a_1_pins[] = { DB8500_PIN_AH13, DB8500_PIN_AG12,
|
||||
DB8500_PIN_AH12, DB8500_PIN_AH11 };
|
||||
static const unsigned hsir_a_1_pins[] = { DB8500_PIN_AG10, DB8500_PIN_AH10,
|
||||
|
|
@ -641,6 +643,7 @@ static const struct nmk_pingroup nmk_db8500_groups[] = {
|
|||
DB8500_PIN_GROUP(msp2_a_1, NMK_GPIO_ALT_A),
|
||||
DB8500_PIN_GROUP(mc4_a_1, NMK_GPIO_ALT_A),
|
||||
DB8500_PIN_GROUP(mc1_a_1, NMK_GPIO_ALT_A),
|
||||
DB8500_PIN_GROUP(mc1_a_2, NMK_GPIO_ALT_A),
|
||||
DB8500_PIN_GROUP(hsir_a_1, NMK_GPIO_ALT_A),
|
||||
DB8500_PIN_GROUP(hsit_a_1, NMK_GPIO_ALT_A),
|
||||
DB8500_PIN_GROUP(hsit_a_2, NMK_GPIO_ALT_A),
|
||||
|
|
@ -768,7 +771,7 @@ DB8500_FUNC_GROUPS(ipgpio, "ipgpio0_a_1", "ipgpio1_a_1", "ipgpio7_b_1",
|
|||
/* MSP2 can not invert the RX/TX pins but has the optional SCK pin */
|
||||
DB8500_FUNC_GROUPS(msp2, "msp2sck_a_1", "msp2_a_1");
|
||||
DB8500_FUNC_GROUPS(mc4, "mc4_a_1", "mc4rstn_c_1");
|
||||
DB8500_FUNC_GROUPS(mc1, "mc1_a_1", "mc1dir_a_1");
|
||||
DB8500_FUNC_GROUPS(mc1, "mc1_a_1", "mc1_a_2", "mc1dir_a_1");
|
||||
DB8500_FUNC_GROUPS(hsi, "hsir_a_1", "hsit_a_1", "hsit_a_2");
|
||||
DB8500_FUNC_GROUPS(clkout, "clkout_a_1", "clkout_a_2", "clkout_c_1");
|
||||
DB8500_FUNC_GROUPS(usb, "usb_a_1");
|
||||
|
|
|
|||
999
drivers/pinctrl/pinctrl-nomadik-db8540.c
Normal file
999
drivers/pinctrl/pinctrl-nomadik-db8540.c
Normal file
|
|
@ -0,0 +1,999 @@
|
|||
#include <linux/kernel.h>
|
||||
#include <linux/pinctrl/pinctrl.h>
|
||||
#include "pinctrl-nomadik.h"
|
||||
|
||||
/* All the pins that can be used for GPIO and some other functions */
|
||||
#define _GPIO(offset) (offset)
|
||||
|
||||
#define DB8540_PIN_AH6 _GPIO(0)
|
||||
#define DB8540_PIN_AG7 _GPIO(1)
|
||||
#define DB8540_PIN_AF2 _GPIO(2)
|
||||
#define DB8540_PIN_AD3 _GPIO(3)
|
||||
#define DB8540_PIN_AF6 _GPIO(4)
|
||||
#define DB8540_PIN_AG6 _GPIO(5)
|
||||
#define DB8540_PIN_AD5 _GPIO(6)
|
||||
#define DB8540_PIN_AF7 _GPIO(7)
|
||||
#define DB8540_PIN_AG5 _GPIO(8)
|
||||
#define DB8540_PIN_AH5 _GPIO(9)
|
||||
#define DB8540_PIN_AE4 _GPIO(10)
|
||||
#define DB8540_PIN_AD1 _GPIO(11)
|
||||
#define DB8540_PIN_AD2 _GPIO(12)
|
||||
#define DB8540_PIN_AC2 _GPIO(13)
|
||||
#define DB8540_PIN_AC4 _GPIO(14)
|
||||
#define DB8540_PIN_AC3 _GPIO(15)
|
||||
#define DB8540_PIN_AH7 _GPIO(16)
|
||||
#define DB8540_PIN_AE7 _GPIO(17)
|
||||
/* Hole */
|
||||
#define DB8540_PIN_AF8 _GPIO(22)
|
||||
#define DB8540_PIN_AH11 _GPIO(23)
|
||||
#define DB8540_PIN_AG11 _GPIO(24)
|
||||
#define DB8540_PIN_AF11 _GPIO(25)
|
||||
#define DB8540_PIN_AH10 _GPIO(26)
|
||||
#define DB8540_PIN_AG10 _GPIO(27)
|
||||
#define DB8540_PIN_AF10 _GPIO(28)
|
||||
/* Hole */
|
||||
#define DB8540_PIN_AD4 _GPIO(33)
|
||||
#define DB8540_PIN_AF3 _GPIO(34)
|
||||
#define DB8540_PIN_AF5 _GPIO(35)
|
||||
#define DB8540_PIN_AG4 _GPIO(36)
|
||||
#define DB8540_PIN_AF9 _GPIO(37)
|
||||
#define DB8540_PIN_AE8 _GPIO(38)
|
||||
/* Hole */
|
||||
#define DB8540_PIN_M26 _GPIO(64)
|
||||
#define DB8540_PIN_M25 _GPIO(65)
|
||||
#define DB8540_PIN_M27 _GPIO(66)
|
||||
#define DB8540_PIN_N25 _GPIO(67)
|
||||
/* Hole */
|
||||
#define DB8540_PIN_M28 _GPIO(70)
|
||||
#define DB8540_PIN_N26 _GPIO(71)
|
||||
#define DB8540_PIN_M22 _GPIO(72)
|
||||
#define DB8540_PIN_N22 _GPIO(73)
|
||||
#define DB8540_PIN_N27 _GPIO(74)
|
||||
#define DB8540_PIN_N28 _GPIO(75)
|
||||
#define DB8540_PIN_P22 _GPIO(76)
|
||||
#define DB8540_PIN_P28 _GPIO(77)
|
||||
#define DB8540_PIN_P26 _GPIO(78)
|
||||
#define DB8540_PIN_T22 _GPIO(79)
|
||||
#define DB8540_PIN_R27 _GPIO(80)
|
||||
#define DB8540_PIN_P27 _GPIO(81)
|
||||
#define DB8540_PIN_R26 _GPIO(82)
|
||||
#define DB8540_PIN_R25 _GPIO(83)
|
||||
#define DB8540_PIN_U22 _GPIO(84)
|
||||
#define DB8540_PIN_T27 _GPIO(85)
|
||||
#define DB8540_PIN_T25 _GPIO(86)
|
||||
#define DB8540_PIN_T26 _GPIO(87)
|
||||
/* Hole */
|
||||
#define DB8540_PIN_AF20 _GPIO(116)
|
||||
#define DB8540_PIN_AG21 _GPIO(117)
|
||||
#define DB8540_PIN_AH19 _GPIO(118)
|
||||
#define DB8540_PIN_AE19 _GPIO(119)
|
||||
#define DB8540_PIN_AG18 _GPIO(120)
|
||||
#define DB8540_PIN_AH17 _GPIO(121)
|
||||
#define DB8540_PIN_AF19 _GPIO(122)
|
||||
#define DB8540_PIN_AF18 _GPIO(123)
|
||||
#define DB8540_PIN_AE18 _GPIO(124)
|
||||
#define DB8540_PIN_AG17 _GPIO(125)
|
||||
#define DB8540_PIN_AF17 _GPIO(126)
|
||||
#define DB8540_PIN_AE17 _GPIO(127)
|
||||
#define DB8540_PIN_AC27 _GPIO(128)
|
||||
#define DB8540_PIN_AD27 _GPIO(129)
|
||||
#define DB8540_PIN_AE28 _GPIO(130)
|
||||
#define DB8540_PIN_AG26 _GPIO(131)
|
||||
#define DB8540_PIN_AF25 _GPIO(132)
|
||||
#define DB8540_PIN_AE27 _GPIO(133)
|
||||
#define DB8540_PIN_AF27 _GPIO(134)
|
||||
#define DB8540_PIN_AG28 _GPIO(135)
|
||||
#define DB8540_PIN_AF28 _GPIO(136)
|
||||
#define DB8540_PIN_AG25 _GPIO(137)
|
||||
#define DB8540_PIN_AG24 _GPIO(138)
|
||||
#define DB8540_PIN_AD25 _GPIO(139)
|
||||
#define DB8540_PIN_AH25 _GPIO(140)
|
||||
#define DB8540_PIN_AF26 _GPIO(141)
|
||||
#define DB8540_PIN_AF23 _GPIO(142)
|
||||
#define DB8540_PIN_AG23 _GPIO(143)
|
||||
#define DB8540_PIN_AE25 _GPIO(144)
|
||||
#define DB8540_PIN_AH24 _GPIO(145)
|
||||
#define DB8540_PIN_AJ25 _GPIO(146)
|
||||
#define DB8540_PIN_AG27 _GPIO(147)
|
||||
#define DB8540_PIN_AH23 _GPIO(148)
|
||||
#define DB8540_PIN_AE26 _GPIO(149)
|
||||
#define DB8540_PIN_AE24 _GPIO(150)
|
||||
#define DB8540_PIN_AJ24 _GPIO(151)
|
||||
#define DB8540_PIN_AE21 _GPIO(152)
|
||||
#define DB8540_PIN_AG22 _GPIO(153)
|
||||
#define DB8540_PIN_AF21 _GPIO(154)
|
||||
#define DB8540_PIN_AF24 _GPIO(155)
|
||||
#define DB8540_PIN_AH22 _GPIO(156)
|
||||
#define DB8540_PIN_AJ23 _GPIO(157)
|
||||
#define DB8540_PIN_AH21 _GPIO(158)
|
||||
#define DB8540_PIN_AG20 _GPIO(159)
|
||||
#define DB8540_PIN_AE23 _GPIO(160)
|
||||
#define DB8540_PIN_AH20 _GPIO(161)
|
||||
#define DB8540_PIN_AG19 _GPIO(162)
|
||||
#define DB8540_PIN_AF22 _GPIO(163)
|
||||
#define DB8540_PIN_AJ21 _GPIO(164)
|
||||
#define DB8540_PIN_AD26 _GPIO(165)
|
||||
#define DB8540_PIN_AD28 _GPIO(166)
|
||||
#define DB8540_PIN_AC28 _GPIO(167)
|
||||
#define DB8540_PIN_AC26 _GPIO(168)
|
||||
/* Hole */
|
||||
#define DB8540_PIN_J3 _GPIO(192)
|
||||
#define DB8540_PIN_H1 _GPIO(193)
|
||||
#define DB8540_PIN_J2 _GPIO(194)
|
||||
#define DB8540_PIN_H2 _GPIO(195)
|
||||
#define DB8540_PIN_H3 _GPIO(196)
|
||||
#define DB8540_PIN_H4 _GPIO(197)
|
||||
#define DB8540_PIN_G2 _GPIO(198)
|
||||
#define DB8540_PIN_G3 _GPIO(199)
|
||||
#define DB8540_PIN_G4 _GPIO(200)
|
||||
#define DB8540_PIN_F2 _GPIO(201)
|
||||
#define DB8540_PIN_C6 _GPIO(202)
|
||||
#define DB8540_PIN_B6 _GPIO(203)
|
||||
#define DB8540_PIN_B7 _GPIO(204)
|
||||
#define DB8540_PIN_A7 _GPIO(205)
|
||||
#define DB8540_PIN_D7 _GPIO(206)
|
||||
#define DB8540_PIN_D8 _GPIO(207)
|
||||
#define DB8540_PIN_F3 _GPIO(208)
|
||||
#define DB8540_PIN_E2 _GPIO(209)
|
||||
#define DB8540_PIN_C7 _GPIO(210)
|
||||
#define DB8540_PIN_B8 _GPIO(211)
|
||||
#define DB8540_PIN_C10 _GPIO(212)
|
||||
#define DB8540_PIN_C8 _GPIO(213)
|
||||
#define DB8540_PIN_C9 _GPIO(214)
|
||||
/* Hole */
|
||||
#define DB8540_PIN_B9 _GPIO(219)
|
||||
#define DB8540_PIN_A10 _GPIO(220)
|
||||
#define DB8540_PIN_D9 _GPIO(221)
|
||||
#define DB8540_PIN_B11 _GPIO(222)
|
||||
#define DB8540_PIN_B10 _GPIO(223)
|
||||
#define DB8540_PIN_E10 _GPIO(224)
|
||||
#define DB8540_PIN_B12 _GPIO(225)
|
||||
#define DB8540_PIN_D10 _GPIO(226)
|
||||
#define DB8540_PIN_D11 _GPIO(227)
|
||||
#define DB8540_PIN_AJ6 _GPIO(228)
|
||||
#define DB8540_PIN_B13 _GPIO(229)
|
||||
#define DB8540_PIN_C12 _GPIO(230)
|
||||
#define DB8540_PIN_B14 _GPIO(231)
|
||||
#define DB8540_PIN_E11 _GPIO(232)
|
||||
/* Hole */
|
||||
#define DB8540_PIN_D12 _GPIO(256)
|
||||
#define DB8540_PIN_D15 _GPIO(257)
|
||||
#define DB8540_PIN_C13 _GPIO(258)
|
||||
#define DB8540_PIN_C14 _GPIO(259)
|
||||
#define DB8540_PIN_C18 _GPIO(260)
|
||||
#define DB8540_PIN_C16 _GPIO(261)
|
||||
#define DB8540_PIN_B16 _GPIO(262)
|
||||
#define DB8540_PIN_D18 _GPIO(263)
|
||||
#define DB8540_PIN_C15 _GPIO(264)
|
||||
#define DB8540_PIN_C17 _GPIO(265)
|
||||
#define DB8540_PIN_B17 _GPIO(266)
|
||||
#define DB8540_PIN_D17 _GPIO(267)
|
||||
|
||||
/*
|
||||
* The names of the pins are denoted by GPIO number and ball name, even
|
||||
* though they can be used for other things than GPIO, this is the first
|
||||
* column in the table of the data sheet and often used on schematics and
|
||||
* such.
|
||||
*/
|
||||
static const struct pinctrl_pin_desc nmk_db8540_pins[] = {
|
||||
PINCTRL_PIN(DB8540_PIN_AH6, "GPIO0_AH6"),
|
||||
PINCTRL_PIN(DB8540_PIN_AG7, "GPIO1_AG7"),
|
||||
PINCTRL_PIN(DB8540_PIN_AF2, "GPIO2_AF2"),
|
||||
PINCTRL_PIN(DB8540_PIN_AD3, "GPIO3_AD3"),
|
||||
PINCTRL_PIN(DB8540_PIN_AF6, "GPIO4_AF6"),
|
||||
PINCTRL_PIN(DB8540_PIN_AG6, "GPIO5_AG6"),
|
||||
PINCTRL_PIN(DB8540_PIN_AD5, "GPIO6_AD5"),
|
||||
PINCTRL_PIN(DB8540_PIN_AF7, "GPIO7_AF7"),
|
||||
PINCTRL_PIN(DB8540_PIN_AG5, "GPIO8_AG5"),
|
||||
PINCTRL_PIN(DB8540_PIN_AH5, "GPIO9_AH5"),
|
||||
PINCTRL_PIN(DB8540_PIN_AE4, "GPIO10_AE4"),
|
||||
PINCTRL_PIN(DB8540_PIN_AD1, "GPIO11_AD1"),
|
||||
PINCTRL_PIN(DB8540_PIN_AD2, "GPIO12_AD2"),
|
||||
PINCTRL_PIN(DB8540_PIN_AC2, "GPIO13_AC2"),
|
||||
PINCTRL_PIN(DB8540_PIN_AC4, "GPIO14_AC4"),
|
||||
PINCTRL_PIN(DB8540_PIN_AC3, "GPIO15_AC3"),
|
||||
PINCTRL_PIN(DB8540_PIN_AH7, "GPIO16_AH7"),
|
||||
PINCTRL_PIN(DB8540_PIN_AE7, "GPIO17_AE7"),
|
||||
/* Hole */
|
||||
PINCTRL_PIN(DB8540_PIN_AF8, "GPIO22_AF8"),
|
||||
PINCTRL_PIN(DB8540_PIN_AH11, "GPIO23_AH11"),
|
||||
PINCTRL_PIN(DB8540_PIN_AG11, "GPIO24_AG11"),
|
||||
PINCTRL_PIN(DB8540_PIN_AF11, "GPIO25_AF11"),
|
||||
PINCTRL_PIN(DB8540_PIN_AH10, "GPIO26_AH10"),
|
||||
PINCTRL_PIN(DB8540_PIN_AG10, "GPIO27_AG10"),
|
||||
PINCTRL_PIN(DB8540_PIN_AF10, "GPIO28_AF10"),
|
||||
/* Hole */
|
||||
PINCTRL_PIN(DB8540_PIN_AD4, "GPIO33_AD4"),
|
||||
PINCTRL_PIN(DB8540_PIN_AF3, "GPIO34_AF3"),
|
||||
PINCTRL_PIN(DB8540_PIN_AF5, "GPIO35_AF5"),
|
||||
PINCTRL_PIN(DB8540_PIN_AG4, "GPIO36_AG4"),
|
||||
PINCTRL_PIN(DB8540_PIN_AF9, "GPIO37_AF9"),
|
||||
PINCTRL_PIN(DB8540_PIN_AE8, "GPIO38_AE8"),
|
||||
/* Hole */
|
||||
PINCTRL_PIN(DB8540_PIN_M26, "GPIO64_M26"),
|
||||
PINCTRL_PIN(DB8540_PIN_M25, "GPIO65_M25"),
|
||||
PINCTRL_PIN(DB8540_PIN_M27, "GPIO66_M27"),
|
||||
PINCTRL_PIN(DB8540_PIN_N25, "GPIO67_N25"),
|
||||
/* Hole */
|
||||
PINCTRL_PIN(DB8540_PIN_M28, "GPIO70_M28"),
|
||||
PINCTRL_PIN(DB8540_PIN_N26, "GPIO71_N26"),
|
||||
PINCTRL_PIN(DB8540_PIN_M22, "GPIO72_M22"),
|
||||
PINCTRL_PIN(DB8540_PIN_N22, "GPIO73_N22"),
|
||||
PINCTRL_PIN(DB8540_PIN_N27, "GPIO74_N27"),
|
||||
PINCTRL_PIN(DB8540_PIN_N28, "GPIO75_N28"),
|
||||
PINCTRL_PIN(DB8540_PIN_P22, "GPIO76_P22"),
|
||||
PINCTRL_PIN(DB8540_PIN_P28, "GPIO77_P28"),
|
||||
PINCTRL_PIN(DB8540_PIN_P26, "GPIO78_P26"),
|
||||
PINCTRL_PIN(DB8540_PIN_T22, "GPIO79_T22"),
|
||||
PINCTRL_PIN(DB8540_PIN_R27, "GPIO80_R27"),
|
||||
PINCTRL_PIN(DB8540_PIN_P27, "GPIO81_P27"),
|
||||
PINCTRL_PIN(DB8540_PIN_R26, "GPIO82_R26"),
|
||||
PINCTRL_PIN(DB8540_PIN_R25, "GPIO83_R25"),
|
||||
PINCTRL_PIN(DB8540_PIN_U22, "GPIO84_U22"),
|
||||
PINCTRL_PIN(DB8540_PIN_T27, "GPIO85_T27"),
|
||||
PINCTRL_PIN(DB8540_PIN_T25, "GPIO86_T25"),
|
||||
PINCTRL_PIN(DB8540_PIN_T26, "GPIO87_T26"),
|
||||
/* Hole */
|
||||
PINCTRL_PIN(DB8540_PIN_AF20, "GPIO116_AF20"),
|
||||
PINCTRL_PIN(DB8540_PIN_AG21, "GPIO117_AG21"),
|
||||
PINCTRL_PIN(DB8540_PIN_AH19, "GPIO118_AH19"),
|
||||
PINCTRL_PIN(DB8540_PIN_AE19, "GPIO119_AE19"),
|
||||
PINCTRL_PIN(DB8540_PIN_AG18, "GPIO120_AG18"),
|
||||
PINCTRL_PIN(DB8540_PIN_AH17, "GPIO121_AH17"),
|
||||
PINCTRL_PIN(DB8540_PIN_AF19, "GPIO122_AF19"),
|
||||
PINCTRL_PIN(DB8540_PIN_AF18, "GPIO123_AF18"),
|
||||
PINCTRL_PIN(DB8540_PIN_AE18, "GPIO124_AE18"),
|
||||
PINCTRL_PIN(DB8540_PIN_AG17, "GPIO125_AG17"),
|
||||
PINCTRL_PIN(DB8540_PIN_AF17, "GPIO126_AF17"),
|
||||
PINCTRL_PIN(DB8540_PIN_AE17, "GPIO127_AE17"),
|
||||
PINCTRL_PIN(DB8540_PIN_AC27, "GPIO128_AC27"),
|
||||
PINCTRL_PIN(DB8540_PIN_AD27, "GPIO129_AD27"),
|
||||
PINCTRL_PIN(DB8540_PIN_AE28, "GPIO130_AE28"),
|
||||
PINCTRL_PIN(DB8540_PIN_AG26, "GPIO131_AG26"),
|
||||
PINCTRL_PIN(DB8540_PIN_AF25, "GPIO132_AF25"),
|
||||
PINCTRL_PIN(DB8540_PIN_AE27, "GPIO133_AE27"),
|
||||
PINCTRL_PIN(DB8540_PIN_AF27, "GPIO134_AF27"),
|
||||
PINCTRL_PIN(DB8540_PIN_AG28, "GPIO135_AG28"),
|
||||
PINCTRL_PIN(DB8540_PIN_AF28, "GPIO136_AF28"),
|
||||
PINCTRL_PIN(DB8540_PIN_AG25, "GPIO137_AG25"),
|
||||
PINCTRL_PIN(DB8540_PIN_AG24, "GPIO138_AG24"),
|
||||
PINCTRL_PIN(DB8540_PIN_AD25, "GPIO139_AD25"),
|
||||
PINCTRL_PIN(DB8540_PIN_AH25, "GPIO140_AH25"),
|
||||
PINCTRL_PIN(DB8540_PIN_AF26, "GPIO141_AF26"),
|
||||
PINCTRL_PIN(DB8540_PIN_AF23, "GPIO142_AF23"),
|
||||
PINCTRL_PIN(DB8540_PIN_AG23, "GPIO143_AG23"),
|
||||
PINCTRL_PIN(DB8540_PIN_AE25, "GPIO144_AE25"),
|
||||
PINCTRL_PIN(DB8540_PIN_AH24, "GPIO145_AH24"),
|
||||
PINCTRL_PIN(DB8540_PIN_AJ25, "GPIO146_AJ25"),
|
||||
PINCTRL_PIN(DB8540_PIN_AG27, "GPIO147_AG27"),
|
||||
PINCTRL_PIN(DB8540_PIN_AH23, "GPIO148_AH23"),
|
||||
PINCTRL_PIN(DB8540_PIN_AE26, "GPIO149_AE26"),
|
||||
PINCTRL_PIN(DB8540_PIN_AE24, "GPIO150_AE24"),
|
||||
PINCTRL_PIN(DB8540_PIN_AJ24, "GPIO151_AJ24"),
|
||||
PINCTRL_PIN(DB8540_PIN_AE21, "GPIO152_AE21"),
|
||||
PINCTRL_PIN(DB8540_PIN_AG22, "GPIO153_AG22"),
|
||||
PINCTRL_PIN(DB8540_PIN_AF21, "GPIO154_AF21"),
|
||||
PINCTRL_PIN(DB8540_PIN_AF24, "GPIO155_AF24"),
|
||||
PINCTRL_PIN(DB8540_PIN_AH22, "GPIO156_AH22"),
|
||||
PINCTRL_PIN(DB8540_PIN_AJ23, "GPIO157_AJ23"),
|
||||
PINCTRL_PIN(DB8540_PIN_AH21, "GPIO158_AH21"),
|
||||
PINCTRL_PIN(DB8540_PIN_AG20, "GPIO159_AG20"),
|
||||
PINCTRL_PIN(DB8540_PIN_AE23, "GPIO160_AE23"),
|
||||
PINCTRL_PIN(DB8540_PIN_AH20, "GPIO161_AH20"),
|
||||
PINCTRL_PIN(DB8540_PIN_AG19, "GPIO162_AG19"),
|
||||
PINCTRL_PIN(DB8540_PIN_AF22, "GPIO163_AF22"),
|
||||
PINCTRL_PIN(DB8540_PIN_AJ21, "GPIO164_AJ21"),
|
||||
PINCTRL_PIN(DB8540_PIN_AD26, "GPIO165_AD26"),
|
||||
PINCTRL_PIN(DB8540_PIN_AD28, "GPIO166_AD28"),
|
||||
PINCTRL_PIN(DB8540_PIN_AC28, "GPIO167_AC28"),
|
||||
PINCTRL_PIN(DB8540_PIN_AC26, "GPIO168_AC26"),
|
||||
/* Hole */
|
||||
PINCTRL_PIN(DB8540_PIN_J3, "GPIO192_J3"),
|
||||
PINCTRL_PIN(DB8540_PIN_H1, "GPIO193_H1"),
|
||||
PINCTRL_PIN(DB8540_PIN_J2, "GPIO194_J2"),
|
||||
PINCTRL_PIN(DB8540_PIN_H2, "GPIO195_H2"),
|
||||
PINCTRL_PIN(DB8540_PIN_H3, "GPIO196_H3"),
|
||||
PINCTRL_PIN(DB8540_PIN_H4, "GPIO197_H4"),
|
||||
PINCTRL_PIN(DB8540_PIN_G2, "GPIO198_G2"),
|
||||
PINCTRL_PIN(DB8540_PIN_G3, "GPIO199_G3"),
|
||||
PINCTRL_PIN(DB8540_PIN_G4, "GPIO200_G4"),
|
||||
PINCTRL_PIN(DB8540_PIN_F2, "GPIO201_F2"),
|
||||
PINCTRL_PIN(DB8540_PIN_C6, "GPIO202_C6"),
|
||||
PINCTRL_PIN(DB8540_PIN_B6, "GPIO203_B6"),
|
||||
PINCTRL_PIN(DB8540_PIN_B7, "GPIO204_B7"),
|
||||
PINCTRL_PIN(DB8540_PIN_A7, "GPIO205_A7"),
|
||||
PINCTRL_PIN(DB8540_PIN_D7, "GPIO206_D7"),
|
||||
PINCTRL_PIN(DB8540_PIN_D8, "GPIO207_D8"),
|
||||
PINCTRL_PIN(DB8540_PIN_F3, "GPIO208_F3"),
|
||||
PINCTRL_PIN(DB8540_PIN_E2, "GPIO209_E2"),
|
||||
PINCTRL_PIN(DB8540_PIN_C7, "GPIO210_C7"),
|
||||
PINCTRL_PIN(DB8540_PIN_B8, "GPIO211_B8"),
|
||||
PINCTRL_PIN(DB8540_PIN_C10, "GPIO212_C10"),
|
||||
PINCTRL_PIN(DB8540_PIN_C8, "GPIO213_C8"),
|
||||
PINCTRL_PIN(DB8540_PIN_C9, "GPIO214_C9"),
|
||||
/* Hole */
|
||||
PINCTRL_PIN(DB8540_PIN_B9, "GPIO219_B9"),
|
||||
PINCTRL_PIN(DB8540_PIN_A10, "GPIO220_A10"),
|
||||
PINCTRL_PIN(DB8540_PIN_D9, "GPIO221_D9"),
|
||||
PINCTRL_PIN(DB8540_PIN_B11, "GPIO222_B11"),
|
||||
PINCTRL_PIN(DB8540_PIN_B10, "GPIO223_B10"),
|
||||
PINCTRL_PIN(DB8540_PIN_E10, "GPIO224_E10"),
|
||||
PINCTRL_PIN(DB8540_PIN_B12, "GPIO225_B12"),
|
||||
PINCTRL_PIN(DB8540_PIN_D10, "GPIO226_D10"),
|
||||
PINCTRL_PIN(DB8540_PIN_D11, "GPIO227_D11"),
|
||||
PINCTRL_PIN(DB8540_PIN_AJ6, "GPIO228_AJ6"),
|
||||
PINCTRL_PIN(DB8540_PIN_B13, "GPIO229_B13"),
|
||||
PINCTRL_PIN(DB8540_PIN_C12, "GPIO230_C12"),
|
||||
PINCTRL_PIN(DB8540_PIN_B14, "GPIO231_B14"),
|
||||
PINCTRL_PIN(DB8540_PIN_E11, "GPIO232_E11"),
|
||||
/* Hole */
|
||||
PINCTRL_PIN(DB8540_PIN_D12, "GPIO256_D12"),
|
||||
PINCTRL_PIN(DB8540_PIN_D15, "GPIO257_D15"),
|
||||
PINCTRL_PIN(DB8540_PIN_C13, "GPIO258_C13"),
|
||||
PINCTRL_PIN(DB8540_PIN_C14, "GPIO259_C14"),
|
||||
PINCTRL_PIN(DB8540_PIN_C18, "GPIO260_C18"),
|
||||
PINCTRL_PIN(DB8540_PIN_C16, "GPIO261_C16"),
|
||||
PINCTRL_PIN(DB8540_PIN_B16, "GPIO262_B16"),
|
||||
PINCTRL_PIN(DB8540_PIN_D18, "GPIO263_D18"),
|
||||
PINCTRL_PIN(DB8540_PIN_C15, "GPIO264_C15"),
|
||||
PINCTRL_PIN(DB8540_PIN_C17, "GPIO265_C17"),
|
||||
PINCTRL_PIN(DB8540_PIN_B17, "GPIO266_B17"),
|
||||
PINCTRL_PIN(DB8540_PIN_D17, "GPIO267_D17"),
|
||||
};
|
||||
|
||||
#define DB8540_GPIO_RANGE(a, b, c) { .name = "db8540", .id = a, .base = b, \
|
||||
.pin_base = b, .npins = c }
|
||||
|
||||
/*
|
||||
* This matches the 32-pin gpio chips registered by the GPIO portion. This
|
||||
* cannot be const since we assign the struct gpio_chip * pointer at runtime.
|
||||
*/
|
||||
static struct pinctrl_gpio_range nmk_db8540_ranges[] = {
|
||||
DB8540_GPIO_RANGE(0, 0, 18),
|
||||
DB8540_GPIO_RANGE(0, 22, 7),
|
||||
DB8540_GPIO_RANGE(1, 33, 6),
|
||||
DB8540_GPIO_RANGE(2, 64, 4),
|
||||
DB8540_GPIO_RANGE(2, 70, 18),
|
||||
DB8540_GPIO_RANGE(3, 116, 12),
|
||||
DB8540_GPIO_RANGE(4, 128, 32),
|
||||
DB8540_GPIO_RANGE(5, 160, 9),
|
||||
DB8540_GPIO_RANGE(6, 192, 23),
|
||||
DB8540_GPIO_RANGE(6, 219, 5),
|
||||
DB8540_GPIO_RANGE(7, 224, 9),
|
||||
DB8540_GPIO_RANGE(8, 256, 12),
|
||||
};
|
||||
|
||||
/*
|
||||
* Read the pin group names like this:
|
||||
* u0_a_1 = first groups of pins for uart0 on alt function a
|
||||
* i2c2_b_2 = second group of pins for i2c2 on alt function b
|
||||
*
|
||||
* The groups are arranged as sets per altfunction column, so we can
|
||||
* mux in one group at a time by selecting the same altfunction for them
|
||||
* all. When functions require pins on different altfunctions, you need
|
||||
* to combine several groups.
|
||||
*/
|
||||
|
||||
/* Altfunction A column */
|
||||
static const unsigned u0_a_1_pins[] = { DB8540_PIN_AH6, DB8540_PIN_AG7,
|
||||
DB8540_PIN_AF2, DB8540_PIN_AD3 };
|
||||
static const unsigned u1rxtx_a_1_pins[] = { DB8540_PIN_AF6, DB8540_PIN_AG6 };
|
||||
static const unsigned u1ctsrts_a_1_pins[] = { DB8540_PIN_AD5, DB8540_PIN_AF7 };
|
||||
/* Image processor I2C line, this is driven by image processor firmware */
|
||||
static const unsigned ipi2c_a_1_pins[] = { DB8540_PIN_AG5, DB8540_PIN_AH5 };
|
||||
static const unsigned ipi2c_a_2_pins[] = { DB8540_PIN_AE4, DB8540_PIN_AD1 };
|
||||
/* MSP0 can only be on these pins, but TXD and RXD can be flipped */
|
||||
static const unsigned msp0txrx_a_1_pins[] = { DB8540_PIN_AD2, DB8540_PIN_AC3 };
|
||||
static const unsigned msp0tfstck_a_1_pins[] = { DB8540_PIN_AC2,
|
||||
DB8540_PIN_AC4 };
|
||||
static const unsigned msp0rfsrck_a_1_pins[] = { DB8540_PIN_AH7,
|
||||
DB8540_PIN_AE7 };
|
||||
/* Basic pins of the MMC/SD card 0 interface */
|
||||
static const unsigned mc0_a_1_pins[] = { DB8540_PIN_AH11, DB8540_PIN_AG11,
|
||||
DB8540_PIN_AF11, DB8540_PIN_AH10, DB8540_PIN_AG10, DB8540_PIN_AF10};
|
||||
/* MSP1 can only be on these pins, but TXD and RXD can be flipped */
|
||||
static const unsigned msp1txrx_a_1_pins[] = { DB8540_PIN_AD4, DB8540_PIN_AG4 };
|
||||
static const unsigned msp1_a_1_pins[] = { DB8540_PIN_AF3, DB8540_PIN_AF5 };
|
||||
|
||||
static const unsigned modobsclk_a_1_pins[] = { DB8540_PIN_AF9 };
|
||||
static const unsigned clkoutreq_a_1_pins[] = { DB8540_PIN_AE8 };
|
||||
/* LCD interface */
|
||||
static const unsigned lcdb_a_1_pins[] = { DB8540_PIN_M26, DB8540_PIN_M25,
|
||||
DB8540_PIN_M27, DB8540_PIN_N25 };
|
||||
static const unsigned lcdvsi0_a_1_pins[] = { DB8540_PIN_AJ24 };
|
||||
static const unsigned lcdvsi1_a_1_pins[] = { DB8540_PIN_AE21 };
|
||||
static const unsigned lcd_d0_d7_a_1_pins[] = { DB8540_PIN_M28, DB8540_PIN_N26,
|
||||
DB8540_PIN_M22, DB8540_PIN_N22, DB8540_PIN_N27, DB8540_PIN_N28,
|
||||
DB8540_PIN_P22, DB8540_PIN_P28 };
|
||||
/* D8 thru D11 often used as TVOUT lines */
|
||||
static const unsigned lcd_d8_d11_a_1_pins[] = { DB8540_PIN_P26, DB8540_PIN_T22,
|
||||
DB8540_PIN_R27, DB8540_PIN_P27 };
|
||||
static const unsigned lcd_d12_d23_a_1_pins[] = { DB8540_PIN_R26, DB8540_PIN_R25,
|
||||
DB8540_PIN_U22, DB8540_PIN_T27, DB8540_PIN_AG22, DB8540_PIN_AF21,
|
||||
DB8540_PIN_AF24, DB8540_PIN_AH22, DB8540_PIN_AJ23, DB8540_PIN_AH21,
|
||||
DB8540_PIN_AG20, DB8540_PIN_AE23 };
|
||||
static const unsigned kp_a_1_pins[] = { DB8540_PIN_AH20, DB8540_PIN_AG19,
|
||||
DB8540_PIN_AF22, DB8540_PIN_AJ21, DB8540_PIN_T25, DB8540_PIN_T26 };
|
||||
/* MC2 has 8 data lines and no direction control, so only for (e)MMC */
|
||||
static const unsigned mc2_a_1_pins[] = { DB8540_PIN_AC27, DB8540_PIN_AD27,
|
||||
DB8540_PIN_AE28, DB8540_PIN_AG26, DB8540_PIN_AF25, DB8540_PIN_AE27,
|
||||
DB8540_PIN_AF27, DB8540_PIN_AG28, DB8540_PIN_AF28, DB8540_PIN_AG25,
|
||||
DB8540_PIN_AG24 };
|
||||
static const unsigned ssp1_a_1_pins[] = { DB8540_PIN_AD25, DB8540_PIN_AH25,
|
||||
DB8540_PIN_AF26, DB8540_PIN_AF23 };
|
||||
static const unsigned ssp0_a_1_pins[] = { DB8540_PIN_AG23, DB8540_PIN_AE25,
|
||||
DB8540_PIN_AH24, DB8540_PIN_AJ25 };
|
||||
static const unsigned i2c0_a_1_pins[] = { DB8540_PIN_AG27, DB8540_PIN_AH23 };
|
||||
/*
|
||||
* Image processor GPIO pins are named "ipgpio" and have their own
|
||||
* numberspace
|
||||
*/
|
||||
static const unsigned ipgpio0_a_1_pins[] = { DB8540_PIN_AE26 };
|
||||
static const unsigned ipgpio1_a_1_pins[] = { DB8540_PIN_AE24 };
|
||||
/* modem i2s interface */
|
||||
static const unsigned modi2s_a_1_pins[] = { DB8540_PIN_AD26, DB8540_PIN_AD28,
|
||||
DB8540_PIN_AC28, DB8540_PIN_AC26 };
|
||||
static const unsigned spi2_a_1_pins[] = { DB8540_PIN_AF20, DB8540_PIN_AG21,
|
||||
DB8540_PIN_AH19, DB8540_PIN_AE19 };
|
||||
static const unsigned u2txrx_a_1_pins[] = { DB8540_PIN_AG18, DB8540_PIN_AH17 };
|
||||
static const unsigned u2ctsrts_a_1_pins[] = { DB8540_PIN_AF19,
|
||||
DB8540_PIN_AF18 };
|
||||
static const unsigned modsmb_a_1_pins[] = { DB8540_PIN_AF17, DB8540_PIN_AE17 };
|
||||
static const unsigned msp2sck_a_1_pins[] = { DB8540_PIN_J3 };
|
||||
static const unsigned msp2txdtcktfs_a_1_pins[] = { DB8540_PIN_H1, DB8540_PIN_J2,
|
||||
DB8540_PIN_H2 };
|
||||
static const unsigned msp2rxd_a_1_pins[] = { DB8540_PIN_H3 };
|
||||
static const unsigned mc4_a_1_pins[] = { DB8540_PIN_H4, DB8540_PIN_G2,
|
||||
DB8540_PIN_G3, DB8540_PIN_G4, DB8540_PIN_F2, DB8540_PIN_C6,
|
||||
DB8540_PIN_B6, DB8540_PIN_B7, DB8540_PIN_A7, DB8540_PIN_D7,
|
||||
DB8540_PIN_D8 };
|
||||
static const unsigned mc1_a_1_pins[] = { DB8540_PIN_F3, DB8540_PIN_E2,
|
||||
DB8540_PIN_C7, DB8540_PIN_B8, DB8540_PIN_C10, DB8540_PIN_C8,
|
||||
DB8540_PIN_C9 };
|
||||
/* mc1_a_2_pins exclude MC1_FBCLK */
|
||||
static const unsigned mc1_a_2_pins[] = { DB8540_PIN_F3, DB8540_PIN_C7,
|
||||
DB8540_PIN_B8, DB8540_PIN_C10, DB8540_PIN_C8,
|
||||
DB8540_PIN_C9 };
|
||||
static const unsigned hsir_a_1_pins[] = { DB8540_PIN_B9, DB8540_PIN_A10,
|
||||
DB8540_PIN_D9 };
|
||||
static const unsigned hsit_a_1_pins[] = { DB8540_PIN_B11, DB8540_PIN_B10,
|
||||
DB8540_PIN_E10, DB8540_PIN_B12, DB8540_PIN_D10 };
|
||||
static const unsigned hsit_a_2_pins[] = { DB8540_PIN_B11, DB8540_PIN_B10,
|
||||
DB8540_PIN_E10, DB8540_PIN_B12 };
|
||||
static const unsigned clkout_a_1_pins[] = { DB8540_PIN_D11, DB8540_PIN_AJ6 };
|
||||
static const unsigned clkout_a_2_pins[] = { DB8540_PIN_B13, DB8540_PIN_C12 };
|
||||
static const unsigned msp4_a_1_pins[] = { DB8540_PIN_B14, DB8540_PIN_E11 };
|
||||
static const unsigned usb_a_1_pins[] = { DB8540_PIN_D12, DB8540_PIN_D15,
|
||||
DB8540_PIN_C13, DB8540_PIN_C14, DB8540_PIN_C18, DB8540_PIN_C16,
|
||||
DB8540_PIN_B16, DB8540_PIN_D18, DB8540_PIN_C15, DB8540_PIN_C17,
|
||||
DB8540_PIN_B17, DB8540_PIN_D17 };
|
||||
/* Altfunction B colum */
|
||||
static const unsigned apetrig_b_1_pins[] = { DB8540_PIN_AH6, DB8540_PIN_AG7 };
|
||||
static const unsigned modtrig_b_1_pins[] = { DB8540_PIN_AF2, DB8540_PIN_AD3 };
|
||||
static const unsigned i2c4_b_1_pins[] = { DB8540_PIN_AF6, DB8540_PIN_AG6 };
|
||||
static const unsigned i2c1_b_1_pins[] = { DB8540_PIN_AD5, DB8540_PIN_AF7 };
|
||||
static const unsigned i2c2_b_1_pins[] = { DB8540_PIN_AG5, DB8540_PIN_AH5 };
|
||||
static const unsigned i2c2_b_2_pins[] = { DB8540_PIN_AE4, DB8540_PIN_AD1 };
|
||||
static const unsigned msp0txrx_b_1_pins[] = { DB8540_PIN_AD2, DB8540_PIN_AC3 };
|
||||
static const unsigned i2c1_b_2_pins[] = { DB8540_PIN_AH7, DB8540_PIN_AE7 };
|
||||
static const unsigned stmmod_b_1_pins[] = { DB8540_PIN_AH11, DB8540_PIN_AF11,
|
||||
DB8540_PIN_AH10, DB8540_PIN_AG10, DB8540_PIN_AF10 };
|
||||
static const unsigned moduartstmmux_b_1_pins[] = { DB8540_PIN_AG11 };
|
||||
static const unsigned msp1txrx_b_1_pins[] = { DB8540_PIN_AD4, DB8540_PIN_AG4 };
|
||||
static const unsigned kp_b_1_pins[] = { DB8540_PIN_AJ24, DB8540_PIN_AE21,
|
||||
DB8540_PIN_M26, DB8540_PIN_M25, DB8540_PIN_M27, DB8540_PIN_N25,
|
||||
DB8540_PIN_M28, DB8540_PIN_N26, DB8540_PIN_M22, DB8540_PIN_N22,
|
||||
DB8540_PIN_N27, DB8540_PIN_N28, DB8540_PIN_P22, DB8540_PIN_P28,
|
||||
DB8540_PIN_P26, DB8540_PIN_T22, DB8540_PIN_R27, DB8540_PIN_P27,
|
||||
DB8540_PIN_R26, DB8540_PIN_R25 };
|
||||
static const unsigned u2txrx_b_1_pins[] = { DB8540_PIN_U22, DB8540_PIN_T27 };
|
||||
static const unsigned sm_b_1_pins[] = { DB8540_PIN_AG22, DB8540_PIN_AF21,
|
||||
DB8540_PIN_AF24, DB8540_PIN_AH22, DB8540_PIN_AJ23, DB8540_PIN_AH21,
|
||||
DB8540_PIN_AG20, DB8540_PIN_AE23, DB8540_PIN_AH20, DB8540_PIN_AF22,
|
||||
DB8540_PIN_AJ21, DB8540_PIN_AC27, DB8540_PIN_AD27, DB8540_PIN_AE28,
|
||||
DB8540_PIN_AG26, DB8540_PIN_AF25, DB8540_PIN_AE27, DB8540_PIN_AF27,
|
||||
DB8540_PIN_AG28, DB8540_PIN_AF28, DB8540_PIN_AG25, DB8540_PIN_AG24,
|
||||
DB8540_PIN_AD25 };
|
||||
static const unsigned smcs0_b_1_pins[] = { DB8540_PIN_AG19 };
|
||||
static const unsigned smcs1_b_1_pins[] = { DB8540_PIN_AE26 };
|
||||
static const unsigned ipgpio7_b_1_pins[] = { DB8540_PIN_AH25 };
|
||||
static const unsigned ipgpio2_b_1_pins[] = { DB8540_PIN_AF26 };
|
||||
static const unsigned ipgpio3_b_1_pins[] = { DB8540_PIN_AF23 };
|
||||
static const unsigned i2c6_b_1_pins[] = { DB8540_PIN_AG23, DB8540_PIN_AE25 };
|
||||
static const unsigned i2c5_b_1_pins[] = { DB8540_PIN_AH24, DB8540_PIN_AJ25 };
|
||||
static const unsigned u3txrx_b_1_pins[] = { DB8540_PIN_AF20, DB8540_PIN_AG21 };
|
||||
static const unsigned u3ctsrts_b_1_pins[] = { DB8540_PIN_AH19,
|
||||
DB8540_PIN_AE19 };
|
||||
static const unsigned i2c5_b_2_pins[] = { DB8540_PIN_AG18, DB8540_PIN_AH17 };
|
||||
static const unsigned i2c4_b_2_pins[] = { DB8540_PIN_AF19, DB8540_PIN_AF18 };
|
||||
static const unsigned u4txrx_b_1_pins[] = { DB8540_PIN_AE18, DB8540_PIN_AG17 };
|
||||
static const unsigned u4ctsrts_b_1_pins[] = { DB8540_PIN_AF17,
|
||||
DB8540_PIN_AE17 };
|
||||
static const unsigned ddrtrig_b_1_pins[] = { DB8540_PIN_J3 };
|
||||
static const unsigned msp4_b_1_pins[] = { DB8540_PIN_H3 };
|
||||
static const unsigned pwl_b_1_pins[] = { DB8540_PIN_C6 };
|
||||
static const unsigned spi1_b_1_pins[] = { DB8540_PIN_E2, DB8540_PIN_C10,
|
||||
DB8540_PIN_C8, DB8540_PIN_C9 };
|
||||
static const unsigned mc3_b_1_pins[] = { DB8540_PIN_B9, DB8540_PIN_A10,
|
||||
DB8540_PIN_D9, DB8540_PIN_B11, DB8540_PIN_B10, DB8540_PIN_E10,
|
||||
DB8540_PIN_B12 };
|
||||
static const unsigned pwl_b_2_pins[] = { DB8540_PIN_D10 };
|
||||
static const unsigned pwl_b_3_pins[] = { DB8540_PIN_B13 };
|
||||
static const unsigned pwl_b_4_pins[] = { DB8540_PIN_C12 };
|
||||
static const unsigned u2txrx_b_2_pins[] = { DB8540_PIN_B17, DB8540_PIN_D17 };
|
||||
|
||||
/* Altfunction C column */
|
||||
static const unsigned ipgpio6_c_1_pins[] = { DB8540_PIN_AG6 };
|
||||
static const unsigned ipgpio0_c_1_pins[] = { DB8540_PIN_AD5 };
|
||||
static const unsigned ipgpio1_c_1_pins[] = { DB8540_PIN_AF7 };
|
||||
static const unsigned ipgpio3_c_1_pins[] = { DB8540_PIN_AE4 };
|
||||
static const unsigned ipgpio2_c_1_pins[] = { DB8540_PIN_AD1 };
|
||||
static const unsigned u0_c_1_pins[] = { DB8540_PIN_AD4, DB8540_PIN_AF3,
|
||||
DB8540_PIN_AF5, DB8540_PIN_AG4 };
|
||||
static const unsigned smcleale_c_1_pins[] = { DB8540_PIN_AJ24,
|
||||
DB8540_PIN_AE21 };
|
||||
static const unsigned ipgpio4_c_1_pins[] = { DB8540_PIN_M26 };
|
||||
static const unsigned ipgpio5_c_1_pins[] = { DB8540_PIN_M25 };
|
||||
static const unsigned ipgpio6_c_2_pins[] = { DB8540_PIN_M27 };
|
||||
static const unsigned ipgpio7_c_1_pins[] = { DB8540_PIN_N25 };
|
||||
static const unsigned stmape_c_1_pins[] = { DB8540_PIN_M28, DB8540_PIN_N26,
|
||||
DB8540_PIN_M22, DB8540_PIN_N22, DB8540_PIN_N27 };
|
||||
static const unsigned u2rxtx_c_1_pins[] = { DB8540_PIN_N28, DB8540_PIN_P22 };
|
||||
static const unsigned modobsresout_c_1_pins[] = { DB8540_PIN_P28 };
|
||||
static const unsigned ipgpio2_c_2_pins[] = { DB8540_PIN_P26 };
|
||||
static const unsigned ipgpio3_c_2_pins[] = { DB8540_PIN_T22 };
|
||||
static const unsigned ipgpio4_c_2_pins[] = { DB8540_PIN_R27 };
|
||||
static const unsigned ipgpio5_c_2_pins[] = { DB8540_PIN_P27 };
|
||||
static const unsigned modaccgpo_c_1_pins[] = { DB8540_PIN_R26, DB8540_PIN_R25,
|
||||
DB8540_PIN_U22 };
|
||||
static const unsigned modobspwrrst_c_1_pins[] = { DB8540_PIN_T27 };
|
||||
static const unsigned mc5_c_1_pins[] = { DB8540_PIN_AG22, DB8540_PIN_AF21,
|
||||
DB8540_PIN_AF24, DB8540_PIN_AH22, DB8540_PIN_AJ23, DB8540_PIN_AH21,
|
||||
DB8540_PIN_AG20, DB8540_PIN_AE23, DB8540_PIN_AH20, DB8540_PIN_AF22,
|
||||
DB8540_PIN_AJ21};
|
||||
static const unsigned smps0_c_1_pins[] = { DB8540_PIN_AG19 };
|
||||
static const unsigned moduart1_c_1_pins[] = { DB8540_PIN_T25, DB8540_PIN_T26 };
|
||||
static const unsigned mc2rstn_c_1_pins[] = { DB8540_PIN_AE28 };
|
||||
static const unsigned i2c5_c_1_pins[] = { DB8540_PIN_AG28, DB8540_PIN_AF28 };
|
||||
static const unsigned ipgpio0_c_2_pins[] = { DB8540_PIN_AG25 };
|
||||
static const unsigned ipgpio1_c_2_pins[] = { DB8540_PIN_AG24 };
|
||||
static const unsigned kp_c_1_pins[] = { DB8540_PIN_AD25, DB8540_PIN_AH25,
|
||||
DB8540_PIN_AF26, DB8540_PIN_AF23 };
|
||||
static const unsigned modrf_c_1_pins[] = { DB8540_PIN_AG23, DB8540_PIN_AE25,
|
||||
DB8540_PIN_AH24 };
|
||||
static const unsigned smps1_c_1_pins[] = { DB8540_PIN_AE26 };
|
||||
static const unsigned i2c5_c_2_pins[] = { DB8540_PIN_AH19, DB8540_PIN_AE19 };
|
||||
static const unsigned u4ctsrts_c_1_pins[] = { DB8540_PIN_AG18,
|
||||
DB8540_PIN_AH17 };
|
||||
static const unsigned u3rxtx_c_1_pins[] = { DB8540_PIN_AF19, DB8540_PIN_AF18 };
|
||||
static const unsigned msp4_c_1_pins[] = { DB8540_PIN_J3 };
|
||||
static const unsigned mc4rstn_c_1_pins[] = { DB8540_PIN_C6 };
|
||||
static const unsigned spi0_c_1_pins[] = { DB8540_PIN_A10, DB8540_PIN_B10,
|
||||
DB8540_PIN_E10, DB8540_PIN_B12 };
|
||||
static const unsigned i2c3_c_1_pins[] = { DB8540_PIN_B13, DB8540_PIN_C12 };
|
||||
|
||||
/* Other alt C1 column */
|
||||
static const unsigned spi3_oc1_1_pins[] = { DB8540_PIN_AG5, DB8540_PIN_AH5,
|
||||
DB8540_PIN_AE4, DB8540_PIN_AD1 };
|
||||
static const unsigned stmape_oc1_1_pins[] = { DB8540_PIN_AH11, DB8540_PIN_AF11,
|
||||
DB8540_PIN_AH10, DB8540_PIN_AG10, DB8540_PIN_AF10 };
|
||||
static const unsigned u2_oc1_1_pins[] = { DB8540_PIN_AG11 };
|
||||
static const unsigned remap0_oc1_1_pins[] = { DB8540_PIN_AJ24 };
|
||||
static const unsigned remap1_oc1_1_pins[] = { DB8540_PIN_AE21 };
|
||||
static const unsigned modobsrefclk_oc1_1_pins[] = { DB8540_PIN_M26 };
|
||||
static const unsigned modobspwrctrl_oc1_1_pins[] = { DB8540_PIN_M25 };
|
||||
static const unsigned modobsclkout_oc1_1_pins[] = { DB8540_PIN_M27 };
|
||||
static const unsigned moduart1_oc1_1_pins[] = { DB8540_PIN_N25 };
|
||||
static const unsigned modprcmudbg_oc1_1_pins[] = { DB8540_PIN_M28,
|
||||
DB8540_PIN_N26, DB8540_PIN_M22, DB8540_PIN_N22, DB8540_PIN_N27,
|
||||
DB8540_PIN_P22, DB8540_PIN_P28, DB8540_PIN_P26, DB8540_PIN_T22,
|
||||
DB8540_PIN_R26, DB8540_PIN_R25, DB8540_PIN_U22, DB8540_PIN_T27,
|
||||
DB8540_PIN_AH20, DB8540_PIN_AG19, DB8540_PIN_AF22, DB8540_PIN_AJ21,
|
||||
DB8540_PIN_T25};
|
||||
static const unsigned modobsresout_oc1_1_pins[] = { DB8540_PIN_N28 };
|
||||
static const unsigned modaccgpo_oc1_1_pins[] = { DB8540_PIN_R27, DB8540_PIN_P27,
|
||||
DB8540_PIN_T26 };
|
||||
static const unsigned kp_oc1_1_pins[] = { DB8540_PIN_AG22, DB8540_PIN_AF21,
|
||||
DB8540_PIN_AF24, DB8540_PIN_AH22, DB8540_PIN_AJ23, DB8540_PIN_AH21,
|
||||
DB8540_PIN_AG20, DB8540_PIN_AE23 };
|
||||
static const unsigned modxmip_oc1_1_pins[] = { DB8540_PIN_AD25, DB8540_PIN_AH25,
|
||||
DB8540_PIN_AG23, DB8540_PIN_AE25 };
|
||||
static const unsigned i2c6_oc1_1_pins[] = { DB8540_PIN_AE26, DB8540_PIN_AE24 };
|
||||
static const unsigned u2txrx_oc1_1_pins[] = { DB8540_PIN_B7, DB8540_PIN_A7 };
|
||||
static const unsigned u2ctsrts_oc1_1_pins[] = { DB8540_PIN_D7, DB8540_PIN_D8 };
|
||||
|
||||
/* Other alt C2 column */
|
||||
static const unsigned sbag_oc2_1_pins[] = { DB8540_PIN_AH11, DB8540_PIN_AG11,
|
||||
DB8540_PIN_AF11, DB8540_PIN_AH10, DB8540_PIN_AG10, DB8540_PIN_AF10 };
|
||||
static const unsigned hxclk_oc2_1_pins[] = { DB8540_PIN_M25 };
|
||||
static const unsigned modaccuart_oc2_1_pins[] = { DB8540_PIN_N25 };
|
||||
static const unsigned stmmod_oc2_1_pins[] = { DB8540_PIN_M28, DB8540_PIN_N26,
|
||||
DB8540_PIN_M22, DB8540_PIN_N22, DB8540_PIN_N27 };
|
||||
static const unsigned moduartstmmux_oc2_1_pins[] = { DB8540_PIN_N28 };
|
||||
static const unsigned hxgpio_oc2_1_pins[] = { DB8540_PIN_P22, DB8540_PIN_P28,
|
||||
DB8540_PIN_P26, DB8540_PIN_T22, DB8540_PIN_R27, DB8540_PIN_P27,
|
||||
DB8540_PIN_R26, DB8540_PIN_R25 };
|
||||
static const unsigned sbag_oc2_2_pins[] = { DB8540_PIN_U22, DB8540_PIN_T27,
|
||||
DB8540_PIN_AG22, DB8540_PIN_AF21, DB8540_PIN_AF24, DB8540_PIN_AH22 };
|
||||
static const unsigned modobsservice_oc2_1_pins[] = { DB8540_PIN_AJ23 };
|
||||
static const unsigned moduart0_oc2_1_pins[] = { DB8540_PIN_AG20,
|
||||
DB8540_PIN_AE23 };
|
||||
static const unsigned stmape_oc2_1_pins[] = { DB8540_PIN_AH20, DB8540_PIN_AG19,
|
||||
DB8540_PIN_AF22, DB8540_PIN_AJ21, DB8540_PIN_T25 };
|
||||
static const unsigned u2_oc2_1_pins[] = { DB8540_PIN_T26, DB8540_PIN_AH21 };
|
||||
static const unsigned modxmip_oc2_1_pins[] = { DB8540_PIN_AE26,
|
||||
DB8540_PIN_AE24 };
|
||||
|
||||
/* Other alt C3 column */
|
||||
static const unsigned modaccgpo_oc3_1_pins[] = { DB8540_PIN_AG11 };
|
||||
static const unsigned tpui_oc3_1_pins[] = { DB8540_PIN_M26, DB8540_PIN_M25,
|
||||
DB8540_PIN_M27, DB8540_PIN_N25, DB8540_PIN_M28, DB8540_PIN_N26,
|
||||
DB8540_PIN_M22, DB8540_PIN_N22, DB8540_PIN_N27, DB8540_PIN_N28,
|
||||
DB8540_PIN_P22, DB8540_PIN_P28, DB8540_PIN_P26, DB8540_PIN_T22,
|
||||
DB8540_PIN_R27, DB8540_PIN_P27, DB8540_PIN_R26, DB8540_PIN_R25,
|
||||
DB8540_PIN_U22, DB8540_PIN_T27, DB8540_PIN_AG22, DB8540_PIN_AF21,
|
||||
DB8540_PIN_AF24, DB8540_PIN_AH22, DB8540_PIN_AJ23, DB8540_PIN_AH21,
|
||||
DB8540_PIN_AG20, DB8540_PIN_AE23, DB8540_PIN_AH20, DB8540_PIN_AG19,
|
||||
DB8540_PIN_AF22, DB8540_PIN_AJ21, DB8540_PIN_T25, DB8540_PIN_T26 };
|
||||
|
||||
/* Other alt C4 column */
|
||||
static const unsigned hwobs_oc4_1_pins[] = { DB8540_PIN_M26, DB8540_PIN_M25,
|
||||
DB8540_PIN_M27, DB8540_PIN_N25, DB8540_PIN_M28, DB8540_PIN_N26,
|
||||
DB8540_PIN_M22, DB8540_PIN_N22, DB8540_PIN_N27, DB8540_PIN_N28,
|
||||
DB8540_PIN_P22, DB8540_PIN_P28, DB8540_PIN_P26, DB8540_PIN_T22,
|
||||
DB8540_PIN_R27, DB8540_PIN_P27, DB8540_PIN_R26, DB8540_PIN_R25 };
|
||||
static const unsigned moduart1txrx_oc4_1_pins[] = { DB8540_PIN_U22,
|
||||
DB8540_PIN_T27 };
|
||||
static const unsigned moduart1rtscts_oc4_1_pins[] = { DB8540_PIN_AG22,
|
||||
DB8540_PIN_AF21 };
|
||||
static const unsigned modaccuarttxrx_oc4_1_pins[] = { DB8540_PIN_AF24,
|
||||
DB8540_PIN_AH22 };
|
||||
static const unsigned modaccuartrtscts_oc4_1_pins[] = { DB8540_PIN_AJ23,
|
||||
DB8540_PIN_AH21 };
|
||||
static const unsigned stmmod_oc4_1_pins[] = { DB8540_PIN_AH20, DB8540_PIN_AG19,
|
||||
DB8540_PIN_AF22, DB8540_PIN_AJ21, DB8540_PIN_T25 };
|
||||
static const unsigned moduartstmmux_oc4_1_pins[] = { DB8540_PIN_T26 };
|
||||
|
||||
#define DB8540_PIN_GROUP(a, b) { .name = #a, .pins = a##_pins, \
|
||||
.npins = ARRAY_SIZE(a##_pins), .altsetting = b }
|
||||
|
||||
static const struct nmk_pingroup nmk_db8540_groups[] = {
|
||||
/* Altfunction A column */
|
||||
DB8540_PIN_GROUP(u0_a_1, NMK_GPIO_ALT_A),
|
||||
DB8540_PIN_GROUP(u1rxtx_a_1, NMK_GPIO_ALT_A),
|
||||
DB8540_PIN_GROUP(u1ctsrts_a_1, NMK_GPIO_ALT_A),
|
||||
DB8540_PIN_GROUP(ipi2c_a_1, NMK_GPIO_ALT_A),
|
||||
DB8540_PIN_GROUP(ipi2c_a_2, NMK_GPIO_ALT_A),
|
||||
DB8540_PIN_GROUP(msp0txrx_a_1, NMK_GPIO_ALT_A),
|
||||
DB8540_PIN_GROUP(msp0tfstck_a_1, NMK_GPIO_ALT_A),
|
||||
DB8540_PIN_GROUP(msp0rfsrck_a_1, NMK_GPIO_ALT_A),
|
||||
DB8540_PIN_GROUP(mc0_a_1, NMK_GPIO_ALT_A),
|
||||
DB8540_PIN_GROUP(msp1txrx_a_1, NMK_GPIO_ALT_A),
|
||||
DB8540_PIN_GROUP(msp1_a_1, NMK_GPIO_ALT_A),
|
||||
DB8540_PIN_GROUP(modobsclk_a_1, NMK_GPIO_ALT_A),
|
||||
DB8540_PIN_GROUP(clkoutreq_a_1, NMK_GPIO_ALT_A),
|
||||
DB8540_PIN_GROUP(lcdb_a_1, NMK_GPIO_ALT_A),
|
||||
DB8540_PIN_GROUP(lcdvsi0_a_1, NMK_GPIO_ALT_A),
|
||||
DB8540_PIN_GROUP(lcdvsi1_a_1, NMK_GPIO_ALT_A),
|
||||
DB8540_PIN_GROUP(lcd_d0_d7_a_1, NMK_GPIO_ALT_A),
|
||||
DB8540_PIN_GROUP(lcd_d8_d11_a_1, NMK_GPIO_ALT_A),
|
||||
DB8540_PIN_GROUP(lcd_d12_d23_a_1, NMK_GPIO_ALT_A),
|
||||
DB8540_PIN_GROUP(kp_a_1, NMK_GPIO_ALT_A),
|
||||
DB8540_PIN_GROUP(mc2_a_1, NMK_GPIO_ALT_A),
|
||||
DB8540_PIN_GROUP(ssp1_a_1, NMK_GPIO_ALT_A),
|
||||
DB8540_PIN_GROUP(ssp0_a_1, NMK_GPIO_ALT_A),
|
||||
DB8540_PIN_GROUP(i2c0_a_1, NMK_GPIO_ALT_A),
|
||||
DB8540_PIN_GROUP(ipgpio0_a_1, NMK_GPIO_ALT_A),
|
||||
DB8540_PIN_GROUP(ipgpio1_a_1, NMK_GPIO_ALT_A),
|
||||
DB8540_PIN_GROUP(modi2s_a_1, NMK_GPIO_ALT_A),
|
||||
DB8540_PIN_GROUP(spi2_a_1, NMK_GPIO_ALT_A),
|
||||
DB8540_PIN_GROUP(u2txrx_a_1, NMK_GPIO_ALT_A),
|
||||
DB8540_PIN_GROUP(u2ctsrts_a_1, NMK_GPIO_ALT_A),
|
||||
DB8540_PIN_GROUP(modsmb_a_1, NMK_GPIO_ALT_A),
|
||||
DB8540_PIN_GROUP(msp2sck_a_1, NMK_GPIO_ALT_A),
|
||||
DB8540_PIN_GROUP(msp2txdtcktfs_a_1, NMK_GPIO_ALT_A),
|
||||
DB8540_PIN_GROUP(msp2rxd_a_1, NMK_GPIO_ALT_A),
|
||||
DB8540_PIN_GROUP(mc4_a_1, NMK_GPIO_ALT_A),
|
||||
DB8540_PIN_GROUP(mc1_a_1, NMK_GPIO_ALT_A),
|
||||
DB8540_PIN_GROUP(hsir_a_1, NMK_GPIO_ALT_A),
|
||||
DB8540_PIN_GROUP(hsit_a_1, NMK_GPIO_ALT_A),
|
||||
DB8540_PIN_GROUP(hsit_a_2, NMK_GPIO_ALT_A),
|
||||
DB8540_PIN_GROUP(clkout_a_1, NMK_GPIO_ALT_A),
|
||||
DB8540_PIN_GROUP(clkout_a_2, NMK_GPIO_ALT_A),
|
||||
DB8540_PIN_GROUP(msp4_a_1, NMK_GPIO_ALT_A),
|
||||
DB8540_PIN_GROUP(usb_a_1, NMK_GPIO_ALT_A),
|
||||
/* Altfunction B column */
|
||||
DB8540_PIN_GROUP(apetrig_b_1, NMK_GPIO_ALT_B),
|
||||
DB8540_PIN_GROUP(modtrig_b_1, NMK_GPIO_ALT_B),
|
||||
DB8540_PIN_GROUP(i2c4_b_1, NMK_GPIO_ALT_B),
|
||||
DB8540_PIN_GROUP(i2c1_b_1, NMK_GPIO_ALT_B),
|
||||
DB8540_PIN_GROUP(i2c2_b_1, NMK_GPIO_ALT_B),
|
||||
DB8540_PIN_GROUP(i2c2_b_2, NMK_GPIO_ALT_B),
|
||||
DB8540_PIN_GROUP(msp0txrx_b_1, NMK_GPIO_ALT_B),
|
||||
DB8540_PIN_GROUP(i2c1_b_2, NMK_GPIO_ALT_B),
|
||||
DB8540_PIN_GROUP(stmmod_b_1, NMK_GPIO_ALT_B),
|
||||
DB8540_PIN_GROUP(moduartstmmux_b_1, NMK_GPIO_ALT_B),
|
||||
DB8540_PIN_GROUP(msp1txrx_b_1, NMK_GPIO_ALT_B),
|
||||
DB8540_PIN_GROUP(kp_b_1, NMK_GPIO_ALT_B),
|
||||
DB8540_PIN_GROUP(u2txrx_b_1, NMK_GPIO_ALT_B),
|
||||
DB8540_PIN_GROUP(sm_b_1, NMK_GPIO_ALT_B),
|
||||
DB8540_PIN_GROUP(smcs0_b_1, NMK_GPIO_ALT_B),
|
||||
DB8540_PIN_GROUP(smcs1_b_1, NMK_GPIO_ALT_B),
|
||||
DB8540_PIN_GROUP(ipgpio7_b_1, NMK_GPIO_ALT_B),
|
||||
DB8540_PIN_GROUP(ipgpio2_b_1, NMK_GPIO_ALT_B),
|
||||
DB8540_PIN_GROUP(ipgpio3_b_1, NMK_GPIO_ALT_B),
|
||||
DB8540_PIN_GROUP(i2c6_b_1, NMK_GPIO_ALT_B),
|
||||
DB8540_PIN_GROUP(i2c5_b_1, NMK_GPIO_ALT_B),
|
||||
DB8540_PIN_GROUP(u3txrx_b_1, NMK_GPIO_ALT_B),
|
||||
DB8540_PIN_GROUP(u3ctsrts_b_1, NMK_GPIO_ALT_B),
|
||||
DB8540_PIN_GROUP(i2c5_b_2, NMK_GPIO_ALT_B),
|
||||
DB8540_PIN_GROUP(i2c4_b_2, NMK_GPIO_ALT_B),
|
||||
DB8540_PIN_GROUP(u4txrx_b_1, NMK_GPIO_ALT_B),
|
||||
DB8540_PIN_GROUP(u4ctsrts_b_1, NMK_GPIO_ALT_B),
|
||||
DB8540_PIN_GROUP(ddrtrig_b_1, NMK_GPIO_ALT_B),
|
||||
DB8540_PIN_GROUP(msp4_b_1, NMK_GPIO_ALT_B),
|
||||
DB8540_PIN_GROUP(pwl_b_1, NMK_GPIO_ALT_B),
|
||||
DB8540_PIN_GROUP(spi1_b_1, NMK_GPIO_ALT_B),
|
||||
DB8540_PIN_GROUP(mc3_b_1, NMK_GPIO_ALT_B),
|
||||
DB8540_PIN_GROUP(pwl_b_2, NMK_GPIO_ALT_B),
|
||||
DB8540_PIN_GROUP(pwl_b_3, NMK_GPIO_ALT_B),
|
||||
DB8540_PIN_GROUP(pwl_b_4, NMK_GPIO_ALT_B),
|
||||
DB8540_PIN_GROUP(u2txrx_b_2, NMK_GPIO_ALT_B),
|
||||
/* Altfunction C column */
|
||||
DB8540_PIN_GROUP(ipgpio6_c_1, NMK_GPIO_ALT_C),
|
||||
DB8540_PIN_GROUP(ipgpio0_c_1, NMK_GPIO_ALT_C),
|
||||
DB8540_PIN_GROUP(ipgpio1_c_1, NMK_GPIO_ALT_C),
|
||||
DB8540_PIN_GROUP(ipgpio3_c_1, NMK_GPIO_ALT_C),
|
||||
DB8540_PIN_GROUP(ipgpio2_c_1, NMK_GPIO_ALT_C),
|
||||
DB8540_PIN_GROUP(u0_c_1, NMK_GPIO_ALT_C),
|
||||
DB8540_PIN_GROUP(smcleale_c_1, NMK_GPIO_ALT_C),
|
||||
DB8540_PIN_GROUP(ipgpio4_c_1, NMK_GPIO_ALT_C),
|
||||
DB8540_PIN_GROUP(ipgpio5_c_1, NMK_GPIO_ALT_C),
|
||||
DB8540_PIN_GROUP(ipgpio6_c_2, NMK_GPIO_ALT_C),
|
||||
DB8540_PIN_GROUP(ipgpio7_c_1, NMK_GPIO_ALT_C),
|
||||
DB8540_PIN_GROUP(stmape_c_1, NMK_GPIO_ALT_C),
|
||||
DB8540_PIN_GROUP(u2rxtx_c_1, NMK_GPIO_ALT_C),
|
||||
DB8540_PIN_GROUP(modobsresout_c_1, NMK_GPIO_ALT_C),
|
||||
DB8540_PIN_GROUP(ipgpio2_c_2, NMK_GPIO_ALT_C),
|
||||
DB8540_PIN_GROUP(ipgpio3_c_2, NMK_GPIO_ALT_C),
|
||||
DB8540_PIN_GROUP(ipgpio4_c_2, NMK_GPIO_ALT_C),
|
||||
DB8540_PIN_GROUP(ipgpio5_c_2, NMK_GPIO_ALT_C),
|
||||
DB8540_PIN_GROUP(modaccgpo_c_1, NMK_GPIO_ALT_C),
|
||||
DB8540_PIN_GROUP(modobspwrrst_c_1, NMK_GPIO_ALT_C),
|
||||
DB8540_PIN_GROUP(mc5_c_1, NMK_GPIO_ALT_C),
|
||||
DB8540_PIN_GROUP(smps0_c_1, NMK_GPIO_ALT_C),
|
||||
DB8540_PIN_GROUP(moduart1_c_1, NMK_GPIO_ALT_C),
|
||||
DB8540_PIN_GROUP(mc2rstn_c_1, NMK_GPIO_ALT_C),
|
||||
DB8540_PIN_GROUP(i2c5_c_1, NMK_GPIO_ALT_C),
|
||||
DB8540_PIN_GROUP(ipgpio0_c_2, NMK_GPIO_ALT_C),
|
||||
DB8540_PIN_GROUP(ipgpio1_c_2, NMK_GPIO_ALT_C),
|
||||
DB8540_PIN_GROUP(kp_c_1, NMK_GPIO_ALT_C),
|
||||
DB8540_PIN_GROUP(modrf_c_1, NMK_GPIO_ALT_C),
|
||||
DB8540_PIN_GROUP(smps1_c_1, NMK_GPIO_ALT_C),
|
||||
DB8540_PIN_GROUP(i2c5_c_2, NMK_GPIO_ALT_C),
|
||||
DB8540_PIN_GROUP(u4ctsrts_c_1, NMK_GPIO_ALT_C),
|
||||
DB8540_PIN_GROUP(u3rxtx_c_1, NMK_GPIO_ALT_C),
|
||||
DB8540_PIN_GROUP(msp4_c_1, NMK_GPIO_ALT_C),
|
||||
DB8540_PIN_GROUP(mc4rstn_c_1, NMK_GPIO_ALT_C),
|
||||
DB8540_PIN_GROUP(spi0_c_1, NMK_GPIO_ALT_C),
|
||||
DB8540_PIN_GROUP(i2c3_c_1, NMK_GPIO_ALT_C),
|
||||
|
||||
/* Other alt C1 column, these are still configured as alt C */
|
||||
DB8540_PIN_GROUP(spi3_oc1_1, NMK_GPIO_ALT_C),
|
||||
DB8540_PIN_GROUP(stmape_oc1_1, NMK_GPIO_ALT_C),
|
||||
DB8540_PIN_GROUP(u2_oc1_1, NMK_GPIO_ALT_C),
|
||||
DB8540_PIN_GROUP(remap0_oc1_1, NMK_GPIO_ALT_C),
|
||||
DB8540_PIN_GROUP(remap1_oc1_1, NMK_GPIO_ALT_C),
|
||||
DB8540_PIN_GROUP(modobsrefclk_oc1_1, NMK_GPIO_ALT_C),
|
||||
DB8540_PIN_GROUP(modobspwrctrl_oc1_1, NMK_GPIO_ALT_C),
|
||||
DB8540_PIN_GROUP(modobsclkout_oc1_1, NMK_GPIO_ALT_C),
|
||||
DB8540_PIN_GROUP(moduart1_oc1_1, NMK_GPIO_ALT_C),
|
||||
DB8540_PIN_GROUP(modprcmudbg_oc1_1, NMK_GPIO_ALT_C),
|
||||
DB8540_PIN_GROUP(modobsresout_oc1_1, NMK_GPIO_ALT_C),
|
||||
DB8540_PIN_GROUP(modaccgpo_oc1_1, NMK_GPIO_ALT_C),
|
||||
DB8540_PIN_GROUP(kp_oc1_1, NMK_GPIO_ALT_C),
|
||||
DB8540_PIN_GROUP(modxmip_oc1_1, NMK_GPIO_ALT_C),
|
||||
DB8540_PIN_GROUP(i2c6_oc1_1, NMK_GPIO_ALT_C),
|
||||
DB8540_PIN_GROUP(u2txrx_oc1_1, NMK_GPIO_ALT_C),
|
||||
DB8540_PIN_GROUP(u2ctsrts_oc1_1, NMK_GPIO_ALT_C),
|
||||
|
||||
/* Other alt C2 column, these are still configured as alt C */
|
||||
DB8540_PIN_GROUP(sbag_oc2_1, NMK_GPIO_ALT_C),
|
||||
DB8540_PIN_GROUP(hxclk_oc2_1, NMK_GPIO_ALT_C),
|
||||
DB8540_PIN_GROUP(modaccuart_oc2_1, NMK_GPIO_ALT_C),
|
||||
DB8540_PIN_GROUP(stmmod_oc2_1, NMK_GPIO_ALT_C),
|
||||
DB8540_PIN_GROUP(moduartstmmux_oc2_1, NMK_GPIO_ALT_C),
|
||||
DB8540_PIN_GROUP(hxgpio_oc2_1, NMK_GPIO_ALT_C),
|
||||
DB8540_PIN_GROUP(sbag_oc2_2, NMK_GPIO_ALT_C),
|
||||
DB8540_PIN_GROUP(modobsservice_oc2_1, NMK_GPIO_ALT_C),
|
||||
DB8540_PIN_GROUP(moduart0_oc2_1, NMK_GPIO_ALT_C),
|
||||
DB8540_PIN_GROUP(stmape_oc2_1, NMK_GPIO_ALT_C),
|
||||
DB8540_PIN_GROUP(u2_oc2_1, NMK_GPIO_ALT_C),
|
||||
DB8540_PIN_GROUP(modxmip_oc2_1, NMK_GPIO_ALT_C),
|
||||
|
||||
/* Other alt C3 column, these are still configured as alt C */
|
||||
DB8540_PIN_GROUP(modaccgpo_oc3_1, NMK_GPIO_ALT_C),
|
||||
DB8540_PIN_GROUP(tpui_oc3_1, NMK_GPIO_ALT_C),
|
||||
|
||||
/* Other alt C4 column, these are still configured as alt C */
|
||||
DB8540_PIN_GROUP(hwobs_oc4_1, NMK_GPIO_ALT_C),
|
||||
DB8540_PIN_GROUP(moduart1txrx_oc4_1, NMK_GPIO_ALT_C),
|
||||
DB8540_PIN_GROUP(moduart1rtscts_oc4_1, NMK_GPIO_ALT_C),
|
||||
DB8540_PIN_GROUP(modaccuarttxrx_oc4_1, NMK_GPIO_ALT_C),
|
||||
DB8540_PIN_GROUP(modaccuartrtscts_oc4_1, NMK_GPIO_ALT_C),
|
||||
DB8540_PIN_GROUP(stmmod_oc4_1, NMK_GPIO_ALT_C),
|
||||
|
||||
};
|
||||
|
||||
/* We use this macro to define the groups applicable to a function */
|
||||
#define DB8540_FUNC_GROUPS(a, b...) \
|
||||
static const char * const a##_groups[] = { b };
|
||||
|
||||
DB8540_FUNC_GROUPS(apetrig, "apetrig_b_1");
|
||||
DB8540_FUNC_GROUPS(clkout, "clkoutreq_a_1", "clkout_a_1", "clkout_a_2");
|
||||
DB8540_FUNC_GROUPS(ddrtrig, "ddrtrig_b_1");
|
||||
DB8540_FUNC_GROUPS(hsi, "hsir_a_1", "hsit_a_1", "hsit_a_2");
|
||||
DB8540_FUNC_GROUPS(hwobs, "hwobs_oc4_1");
|
||||
DB8540_FUNC_GROUPS(hx, "hxclk_oc2_1", "hxgpio_oc2_1");
|
||||
DB8540_FUNC_GROUPS(i2c0, "i2c0_a_1");
|
||||
DB8540_FUNC_GROUPS(i2c1, "i2c1_b_1", "i2c1_b_2");
|
||||
DB8540_FUNC_GROUPS(i2c2, "i2c2_b_1", "i2c2_b_2");
|
||||
DB8540_FUNC_GROUPS(i2c3, "i2c3_c_1", "i2c4_b_1");
|
||||
DB8540_FUNC_GROUPS(i2c4, "i2c4_b_2");
|
||||
DB8540_FUNC_GROUPS(i2c5, "i2c5_b_1", "i2c5_b_2", "i2c5_c_1", "i2c5_c_2");
|
||||
DB8540_FUNC_GROUPS(i2c6, "i2c6_b_1", "i2c6_oc1_1");
|
||||
/* The image processor has 8 GPIO pins that can be muxed out */
|
||||
DB8540_FUNC_GROUPS(ipgpio, "ipgpio0_a_1", "ipgpio0_c_1", "ipgpio0_c_2",
|
||||
"ipgpio1_a_1", "ipgpio1_c_1", "ipgpio1_c_2",
|
||||
"ipgpio2_b_1", "ipgpio2_c_1", "ipgpio2_c_2",
|
||||
"ipgpio3_b_1", "ipgpio3_c_1", "ipgpio3_c_2",
|
||||
"ipgpio4_c_1", "ipgpio4_c_2",
|
||||
"ipgpio5_c_1", "ipgpio5_c_2",
|
||||
"ipgpio6_c_1", "ipgpio6_c_2",
|
||||
"ipgpio7_b_1", "ipgpio7_c_1");
|
||||
DB8540_FUNC_GROUPS(ipi2c, "ipi2c_a_1", "ipi2c_a_2");
|
||||
DB8540_FUNC_GROUPS(kp, "kp_a_1", "kp_b_1", "kp_c_1", "kp_oc1_1");
|
||||
DB8540_FUNC_GROUPS(lcd, "lcd_d0_d7_a_1", "lcd_d12_d23_a_1", "lcd_d8_d11_a_1",
|
||||
"lcdvsi0_a_1", "lcdvsi1_a_1");
|
||||
DB8540_FUNC_GROUPS(lcdb, "lcdb_a_1");
|
||||
DB8540_FUNC_GROUPS(mc0, "mc0_a_1");
|
||||
DB8540_FUNC_GROUPS(mc1, "mc1_a_1", "mc1_a_2");
|
||||
DB8540_FUNC_GROUPS(mc2, "mc2_a_1", "mc2rstn_c_1");
|
||||
DB8540_FUNC_GROUPS(mc3, "mc3_b_1");
|
||||
DB8540_FUNC_GROUPS(mc4, "mc4_a_1", "mc4rstn_c_1");
|
||||
DB8540_FUNC_GROUPS(mc5, "mc5_c_1");
|
||||
DB8540_FUNC_GROUPS(modaccgpo, "modaccgpo_c_1", "modaccgpo_oc1_1",
|
||||
"modaccgpo_oc3_1");
|
||||
DB8540_FUNC_GROUPS(modaccuart, "modaccuart_oc2_1", "modaccuarttxrx_oc4_1",
|
||||
"modaccuartrtccts_oc4_1");
|
||||
DB8540_FUNC_GROUPS(modi2s, "modi2s_a_1");
|
||||
DB8540_FUNC_GROUPS(modobs, "modobsclk_a_1", "modobsclkout_oc1_1",
|
||||
"modobspwrctrl_oc1_1", "modobspwrrst_c_1",
|
||||
"modobsrefclk_oc1_1", "modobsresout_c_1",
|
||||
"modobsresout_oc1_1", "modobsservice_oc2_1");
|
||||
DB8540_FUNC_GROUPS(modprcmudbg, "modprcmudbg_oc1_1");
|
||||
DB8540_FUNC_GROUPS(modrf, "modrf_c_1");
|
||||
DB8540_FUNC_GROUPS(modsmb, "modsmb_a_1");
|
||||
DB8540_FUNC_GROUPS(modtrig, "modtrig_b_1");
|
||||
DB8540_FUNC_GROUPS(moduart, "moduart1_c_1", "moduart1_oc1_1",
|
||||
"moduart1txrx_oc4_1", "moduart1rtscts_oc4_1", "moduart0_oc2_1");
|
||||
DB8540_FUNC_GROUPS(moduartstmmux, "moduartstmmux_b_1", "moduartstmmux_oc2_1",
|
||||
"moduartstmmux_oc4_1");
|
||||
DB8540_FUNC_GROUPS(modxmip, "modxmip_oc1_1", "modxmip_oc2_1");
|
||||
/*
|
||||
* MSP0 can only be on a certain set of pins, but the TX/RX pins can be
|
||||
* switched around by selecting the altfunction A or B.
|
||||
*/
|
||||
DB8540_FUNC_GROUPS(msp0, "msp0rfsrck_a_1", "msp0tfstck_a_1", "msp0txrx_a_1",
|
||||
"msp0txrx_b_1");
|
||||
DB8540_FUNC_GROUPS(msp1, "msp1_a_1", "msp1txrx_a_1", "msp1txrx_b_1");
|
||||
DB8540_FUNC_GROUPS(msp2, "msp2sck_a_1", "msp2txdtcktfs_a_1", "msp2rxd_a_1");
|
||||
DB8540_FUNC_GROUPS(msp4, "msp4_a_1", "msp4_b_1", "msp4_c_1");
|
||||
DB8540_FUNC_GROUPS(pwl, "pwl_b_1", "pwl_b_2", "pwl_b_3", "pwl_b_4");
|
||||
DB8540_FUNC_GROUPS(remap, "remap0_oc1_1", "remap1_oc1_1");
|
||||
DB8540_FUNC_GROUPS(sbag, "sbag_oc2_1", "sbag_oc2_2");
|
||||
/* Select between CS0 on alt B or PS1 on alt C */
|
||||
DB8540_FUNC_GROUPS(sm, "sm_b_1", "smcleale_c_1", "smcs0_b_1", "smcs1_b_1",
|
||||
"smps0_c_1", "smps1_c_1");
|
||||
DB8540_FUNC_GROUPS(spi0, "spi0_c_1");
|
||||
DB8540_FUNC_GROUPS(spi1, "spi1_b_1");
|
||||
DB8540_FUNC_GROUPS(spi2, "spi2_a_1");
|
||||
DB8540_FUNC_GROUPS(spi3, "spi3_oc1_1");
|
||||
DB8540_FUNC_GROUPS(ssp0, "ssp0_a_1");
|
||||
DB8540_FUNC_GROUPS(ssp1, "ssp1_a_1");
|
||||
DB8540_FUNC_GROUPS(stmape, "stmape_c_1", "stmape_oc1_1", "stmape_oc2_1");
|
||||
DB8540_FUNC_GROUPS(stmmod, "stmmod_b_1", "stmmod_oc2_1", "stmmod_oc4_1");
|
||||
DB8540_FUNC_GROUPS(tpui, "tpui_oc3_1");
|
||||
DB8540_FUNC_GROUPS(u0, "u0_a_1", "u0_c_1");
|
||||
DB8540_FUNC_GROUPS(u1, "u1ctsrts_a_1", "u1rxtx_a_1");
|
||||
DB8540_FUNC_GROUPS(u2, "u2_oc1_1", "u2_oc2_1", "u2ctsrts_a_1", "u2ctsrts_oc1_1",
|
||||
"u2rxtx_c_1", "u2txrx_a_1", "u2txrx_b_1", "u2txrx_b_2",
|
||||
"u2txrx_oc1_1");
|
||||
DB8540_FUNC_GROUPS(u3, "u3ctsrts_b_1", "u3rxtx_c_1", "u3txrxa_b_1");
|
||||
DB8540_FUNC_GROUPS(u4, "u4ctsrts_b_1", "u4ctsrts_c_1", "u4txrx_b_1");
|
||||
DB8540_FUNC_GROUPS(usb, "usb_a_1");
|
||||
|
||||
|
||||
#define FUNCTION(fname) \
|
||||
{ \
|
||||
.name = #fname, \
|
||||
.groups = fname##_groups, \
|
||||
.ngroups = ARRAY_SIZE(fname##_groups), \
|
||||
}
|
||||
|
||||
static const struct nmk_function nmk_db8540_functions[] = {
|
||||
FUNCTION(apetrig),
|
||||
FUNCTION(clkout),
|
||||
FUNCTION(ddrtrig),
|
||||
FUNCTION(hsi),
|
||||
FUNCTION(hwobs),
|
||||
FUNCTION(hx),
|
||||
FUNCTION(i2c0),
|
||||
FUNCTION(i2c1),
|
||||
FUNCTION(i2c2),
|
||||
FUNCTION(i2c3),
|
||||
FUNCTION(i2c4),
|
||||
FUNCTION(i2c5),
|
||||
FUNCTION(i2c6),
|
||||
FUNCTION(ipgpio),
|
||||
FUNCTION(ipi2c),
|
||||
FUNCTION(kp),
|
||||
FUNCTION(lcd),
|
||||
FUNCTION(lcdb),
|
||||
FUNCTION(mc0),
|
||||
FUNCTION(mc1),
|
||||
FUNCTION(mc2),
|
||||
FUNCTION(mc3),
|
||||
FUNCTION(mc4),
|
||||
FUNCTION(mc5),
|
||||
FUNCTION(modaccgpo),
|
||||
FUNCTION(modaccuart),
|
||||
FUNCTION(modi2s),
|
||||
FUNCTION(modobs),
|
||||
FUNCTION(modprcmudbg),
|
||||
FUNCTION(modrf),
|
||||
FUNCTION(modsmb),
|
||||
FUNCTION(modtrig),
|
||||
FUNCTION(moduart),
|
||||
FUNCTION(modxmip),
|
||||
FUNCTION(msp0),
|
||||
FUNCTION(msp1),
|
||||
FUNCTION(msp2),
|
||||
FUNCTION(msp4),
|
||||
FUNCTION(pwl),
|
||||
FUNCTION(remap),
|
||||
FUNCTION(sbag),
|
||||
FUNCTION(sm),
|
||||
FUNCTION(spi0),
|
||||
FUNCTION(spi1),
|
||||
FUNCTION(spi2),
|
||||
FUNCTION(spi3),
|
||||
FUNCTION(ssp0),
|
||||
FUNCTION(ssp1),
|
||||
FUNCTION(stmape),
|
||||
FUNCTION(stmmod),
|
||||
FUNCTION(tpui),
|
||||
FUNCTION(u0),
|
||||
FUNCTION(u1),
|
||||
FUNCTION(u2),
|
||||
FUNCTION(u3),
|
||||
FUNCTION(u4),
|
||||
FUNCTION(usb)
|
||||
};
|
||||
|
||||
static const struct nmk_pinctrl_soc_data nmk_db8540_soc = {
|
||||
.gpio_ranges = nmk_db8540_ranges,
|
||||
.gpio_num_ranges = ARRAY_SIZE(nmk_db8540_ranges),
|
||||
.pins = nmk_db8540_pins,
|
||||
.npins = ARRAY_SIZE(nmk_db8540_pins),
|
||||
.functions = nmk_db8540_functions,
|
||||
.nfunctions = ARRAY_SIZE(nmk_db8540_functions),
|
||||
.groups = nmk_db8540_groups,
|
||||
.ngroups = ARRAY_SIZE(nmk_db8540_groups),
|
||||
};
|
||||
|
||||
void __devinit
|
||||
nmk_pinctrl_db8540_init(const struct nmk_pinctrl_soc_data **soc)
|
||||
{
|
||||
*soc = &nmk_db8540_soc;
|
||||
}
|
||||
357
drivers/pinctrl/pinctrl-nomadik-stn8815.c
Normal file
357
drivers/pinctrl/pinctrl-nomadik-stn8815.c
Normal file
|
|
@ -0,0 +1,357 @@
|
|||
#include <linux/kernel.h>
|
||||
#include <linux/pinctrl/pinctrl.h>
|
||||
#include "pinctrl-nomadik.h"
|
||||
|
||||
/* All the pins that can be used for GPIO and some other functions */
|
||||
#define _GPIO(offset) (offset)
|
||||
|
||||
#define STN8815_PIN_B4 _GPIO(0)
|
||||
#define STN8815_PIN_D5 _GPIO(1)
|
||||
#define STN8815_PIN_C5 _GPIO(2)
|
||||
#define STN8815_PIN_A4 _GPIO(3)
|
||||
#define STN8815_PIN_B5 _GPIO(4)
|
||||
#define STN8815_PIN_D6 _GPIO(5)
|
||||
#define STN8815_PIN_C6 _GPIO(6)
|
||||
#define STN8815_PIN_B6 _GPIO(7)
|
||||
#define STN8815_PIN_B10 _GPIO(8)
|
||||
#define STN8815_PIN_A10 _GPIO(9)
|
||||
#define STN8815_PIN_C11 _GPIO(10)
|
||||
#define STN8815_PIN_B11 _GPIO(11)
|
||||
#define STN8815_PIN_A11 _GPIO(12)
|
||||
#define STN8815_PIN_C12 _GPIO(13)
|
||||
#define STN8815_PIN_B12 _GPIO(14)
|
||||
#define STN8815_PIN_A12 _GPIO(15)
|
||||
#define STN8815_PIN_C13 _GPIO(16)
|
||||
#define STN8815_PIN_B13 _GPIO(17)
|
||||
#define STN8815_PIN_A13 _GPIO(18)
|
||||
#define STN8815_PIN_D13 _GPIO(19)
|
||||
#define STN8815_PIN_C14 _GPIO(20)
|
||||
#define STN8815_PIN_B14 _GPIO(21)
|
||||
#define STN8815_PIN_A14 _GPIO(22)
|
||||
#define STN8815_PIN_D15 _GPIO(23)
|
||||
#define STN8815_PIN_C15 _GPIO(24)
|
||||
#define STN8815_PIN_B15 _GPIO(25)
|
||||
#define STN8815_PIN_A15 _GPIO(26)
|
||||
#define STN8815_PIN_C16 _GPIO(27)
|
||||
#define STN8815_PIN_B16 _GPIO(28)
|
||||
#define STN8815_PIN_A16 _GPIO(29)
|
||||
#define STN8815_PIN_D17 _GPIO(30)
|
||||
#define STN8815_PIN_C17 _GPIO(31)
|
||||
#define STN8815_PIN_AB6 _GPIO(32)
|
||||
#define STN8815_PIN_AA6 _GPIO(33)
|
||||
#define STN8815_PIN_Y6 _GPIO(34)
|
||||
#define STN8815_PIN_Y5 _GPIO(35)
|
||||
#define STN8815_PIN_AA5 _GPIO(36)
|
||||
#define STN8815_PIN_AB5 _GPIO(37)
|
||||
#define STN8815_PIN_AB4 _GPIO(38)
|
||||
#define STN8815_PIN_Y4 _GPIO(39)
|
||||
#define STN8815_PIN_R1 _GPIO(40)
|
||||
#define STN8815_PIN_R2 _GPIO(41)
|
||||
#define STN8815_PIN_R3 _GPIO(42)
|
||||
#define STN8815_PIN_P1 _GPIO(43)
|
||||
#define STN8815_PIN_P2 _GPIO(44)
|
||||
#define STN8815_PIN_P3 _GPIO(45)
|
||||
#define STN8815_PIN_N1 _GPIO(46)
|
||||
#define STN8815_PIN_N2 _GPIO(47)
|
||||
#define STN8815_PIN_N3 _GPIO(48)
|
||||
#define STN8815_PIN_M1 _GPIO(49)
|
||||
#define STN8815_PIN_M3 _GPIO(50)
|
||||
#define STN8815_PIN_M2 _GPIO(51)
|
||||
#define STN8815_PIN_L1 _GPIO(52)
|
||||
#define STN8815_PIN_L4 _GPIO(53)
|
||||
#define STN8815_PIN_L3 _GPIO(54)
|
||||
#define STN8815_PIN_L2 _GPIO(55)
|
||||
#define STN8815_PIN_F3 _GPIO(56)
|
||||
#define STN8815_PIN_F2 _GPIO(57)
|
||||
#define STN8815_PIN_E1 _GPIO(58)
|
||||
#define STN8815_PIN_E3 _GPIO(59)
|
||||
#define STN8815_PIN_E2 _GPIO(60)
|
||||
#define STN8815_PIN_E4 _GPIO(61)
|
||||
#define STN8815_PIN_D3 _GPIO(62)
|
||||
#define STN8815_PIN_D2 _GPIO(63)
|
||||
#define STN8815_PIN_F21 _GPIO(64)
|
||||
#define STN8815_PIN_F20 _GPIO(65)
|
||||
#define STN8815_PIN_E22 _GPIO(66)
|
||||
#define STN8815_PIN_D22 _GPIO(67)
|
||||
#define STN8815_PIN_E21 _GPIO(68)
|
||||
#define STN8815_PIN_E20 _GPIO(69)
|
||||
#define STN8815_PIN_C22 _GPIO(70)
|
||||
#define STN8815_PIN_D21 _GPIO(71)
|
||||
#define STN8815_PIN_D20 _GPIO(72)
|
||||
#define STN8815_PIN_C21 _GPIO(73)
|
||||
#define STN8815_PIN_C20 _GPIO(74)
|
||||
#define STN8815_PIN_C19 _GPIO(75)
|
||||
#define STN8815_PIN_B20 _GPIO(76)
|
||||
#define STN8815_PIN_B8 _GPIO(77)
|
||||
#define STN8815_PIN_A8 _GPIO(78)
|
||||
#define STN8815_PIN_C9 _GPIO(79)
|
||||
#define STN8815_PIN_B9 _GPIO(80)
|
||||
#define STN8815_PIN_A9 _GPIO(81)
|
||||
#define STN8815_PIN_C10 _GPIO(82)
|
||||
#define STN8815_PIN_K1 _GPIO(83)
|
||||
#define STN8815_PIN_K3 _GPIO(84)
|
||||
#define STN8815_PIN_K2 _GPIO(85)
|
||||
#define STN8815_PIN_J1 _GPIO(86)
|
||||
#define STN8815_PIN_J3 _GPIO(87)
|
||||
#define STN8815_PIN_J2 _GPIO(88)
|
||||
#define STN8815_PIN_H1 _GPIO(89)
|
||||
#define STN8815_PIN_H3 _GPIO(90)
|
||||
#define STN8815_PIN_H2 _GPIO(91)
|
||||
#define STN8815_PIN_G1 _GPIO(92)
|
||||
#define STN8815_PIN_G3 _GPIO(93)
|
||||
#define STN8815_PIN_G2 _GPIO(94)
|
||||
#define STN8815_PIN_F1 _GPIO(95)
|
||||
#define STN8815_PIN_T20 _GPIO(96)
|
||||
#define STN8815_PIN_R21 _GPIO(97)
|
||||
#define STN8815_PIN_R20 _GPIO(98)
|
||||
#define STN8815_PIN_U22 _GPIO(99)
|
||||
#define STN8815_PIN_N21 _GPIO(100)
|
||||
#define STN8815_PIN_N20 _GPIO(101)
|
||||
#define STN8815_PIN_P22 _GPIO(102)
|
||||
#define STN8815_PIN_N22 _GPIO(103)
|
||||
#define STN8815_PIN_V22 _GPIO(104)
|
||||
#define STN8815_PIN_V21 _GPIO(105)
|
||||
#define STN8815_PIN_K22 _GPIO(106)
|
||||
#define STN8815_PIN_K21 _GPIO(107)
|
||||
#define STN8815_PIN_H20 _GPIO(108)
|
||||
#define STN8815_PIN_G20 _GPIO(109)
|
||||
#define STN8815_PIN_L21 _GPIO(110)
|
||||
#define STN8815_PIN_H21 _GPIO(111)
|
||||
#define STN8815_PIN_J21 _GPIO(112)
|
||||
#define STN8815_PIN_H22 _GPIO(113)
|
||||
#define STN8815_PIN_K20 _GPIO(114)
|
||||
#define STN8815_PIN_L22 _GPIO(115)
|
||||
#define STN8815_PIN_G21 _GPIO(116)
|
||||
#define STN8815_PIN_J20 _GPIO(117)
|
||||
#define STN8815_PIN_G22 _GPIO(118)
|
||||
#define STN8815_PIN_U19 _GPIO(119)
|
||||
#define STN8815_PIN_G19 _GPIO(120)
|
||||
#define STN8815_PIN_M22 _GPIO(121)
|
||||
#define STN8815_PIN_M19 _GPIO(122)
|
||||
#define STN8815_PIN_J22 _GPIO(123)
|
||||
/* GPIOs 124-127 not routed to pins */
|
||||
|
||||
/*
|
||||
* The names of the pins are denoted by GPIO number and ball name, even
|
||||
* though they can be used for other things than GPIO, this is the first
|
||||
* column in the table of the data sheet and often used on schematics and
|
||||
* such.
|
||||
*/
|
||||
static const struct pinctrl_pin_desc nmk_stn8815_pins[] = {
|
||||
PINCTRL_PIN(STN8815_PIN_B4, "GPIO0_B4"),
|
||||
PINCTRL_PIN(STN8815_PIN_D5, "GPIO1_D5"),
|
||||
PINCTRL_PIN(STN8815_PIN_C5, "GPIO2_C5"),
|
||||
PINCTRL_PIN(STN8815_PIN_A4, "GPIO3_A4"),
|
||||
PINCTRL_PIN(STN8815_PIN_B5, "GPIO4_B5"),
|
||||
PINCTRL_PIN(STN8815_PIN_D6, "GPIO5_D6"),
|
||||
PINCTRL_PIN(STN8815_PIN_C6, "GPIO6_C6"),
|
||||
PINCTRL_PIN(STN8815_PIN_B6, "GPIO7_B6"),
|
||||
PINCTRL_PIN(STN8815_PIN_B10, "GPIO8_B10"),
|
||||
PINCTRL_PIN(STN8815_PIN_A10, "GPIO9_A10"),
|
||||
PINCTRL_PIN(STN8815_PIN_C11, "GPIO10_C11"),
|
||||
PINCTRL_PIN(STN8815_PIN_B11, "GPIO11_B11"),
|
||||
PINCTRL_PIN(STN8815_PIN_A11, "GPIO12_A11"),
|
||||
PINCTRL_PIN(STN8815_PIN_C12, "GPIO13_C12"),
|
||||
PINCTRL_PIN(STN8815_PIN_B12, "GPIO14_B12"),
|
||||
PINCTRL_PIN(STN8815_PIN_A12, "GPIO15_A12"),
|
||||
PINCTRL_PIN(STN8815_PIN_C13, "GPIO16_C13"),
|
||||
PINCTRL_PIN(STN8815_PIN_B13, "GPIO17_B13"),
|
||||
PINCTRL_PIN(STN8815_PIN_A13, "GPIO18_A13"),
|
||||
PINCTRL_PIN(STN8815_PIN_D13, "GPIO19_D13"),
|
||||
PINCTRL_PIN(STN8815_PIN_C14, "GPIO20_C14"),
|
||||
PINCTRL_PIN(STN8815_PIN_B14, "GPIO21_B14"),
|
||||
PINCTRL_PIN(STN8815_PIN_A14, "GPIO22_A14"),
|
||||
PINCTRL_PIN(STN8815_PIN_D15, "GPIO23_D15"),
|
||||
PINCTRL_PIN(STN8815_PIN_C15, "GPIO24_C15"),
|
||||
PINCTRL_PIN(STN8815_PIN_B15, "GPIO25_B15"),
|
||||
PINCTRL_PIN(STN8815_PIN_A15, "GPIO26_A15"),
|
||||
PINCTRL_PIN(STN8815_PIN_C16, "GPIO27_C16"),
|
||||
PINCTRL_PIN(STN8815_PIN_B16, "GPIO28_B16"),
|
||||
PINCTRL_PIN(STN8815_PIN_A16, "GPIO29_A16"),
|
||||
PINCTRL_PIN(STN8815_PIN_D17, "GPIO30_D17"),
|
||||
PINCTRL_PIN(STN8815_PIN_C17, "GPIO31_C17"),
|
||||
PINCTRL_PIN(STN8815_PIN_AB6, "GPIO32_AB6"),
|
||||
PINCTRL_PIN(STN8815_PIN_AA6, "GPIO33_AA6"),
|
||||
PINCTRL_PIN(STN8815_PIN_Y6, "GPIO34_Y6"),
|
||||
PINCTRL_PIN(STN8815_PIN_Y5, "GPIO35_Y5"),
|
||||
PINCTRL_PIN(STN8815_PIN_AA5, "GPIO36_AA5"),
|
||||
PINCTRL_PIN(STN8815_PIN_AB5, "GPIO37_AB5"),
|
||||
PINCTRL_PIN(STN8815_PIN_AB4, "GPIO38_AB4"),
|
||||
PINCTRL_PIN(STN8815_PIN_Y4, "GPIO39_Y4"),
|
||||
PINCTRL_PIN(STN8815_PIN_R1, "GPIO40_R1"),
|
||||
PINCTRL_PIN(STN8815_PIN_R2, "GPIO41_R2"),
|
||||
PINCTRL_PIN(STN8815_PIN_R3, "GPIO42_R3"),
|
||||
PINCTRL_PIN(STN8815_PIN_P1, "GPIO43_P1"),
|
||||
PINCTRL_PIN(STN8815_PIN_P2, "GPIO44_P2"),
|
||||
PINCTRL_PIN(STN8815_PIN_P3, "GPIO45_P3"),
|
||||
PINCTRL_PIN(STN8815_PIN_N1, "GPIO46_N1"),
|
||||
PINCTRL_PIN(STN8815_PIN_N2, "GPIO47_N2"),
|
||||
PINCTRL_PIN(STN8815_PIN_N3, "GPIO48_N3"),
|
||||
PINCTRL_PIN(STN8815_PIN_M1, "GPIO49_M1"),
|
||||
PINCTRL_PIN(STN8815_PIN_M3, "GPIO50_M3"),
|
||||
PINCTRL_PIN(STN8815_PIN_M2, "GPIO51_M2"),
|
||||
PINCTRL_PIN(STN8815_PIN_L1, "GPIO52_L1"),
|
||||
PINCTRL_PIN(STN8815_PIN_L4, "GPIO53_L4"),
|
||||
PINCTRL_PIN(STN8815_PIN_L3, "GPIO54_L3"),
|
||||
PINCTRL_PIN(STN8815_PIN_L2, "GPIO55_L2"),
|
||||
PINCTRL_PIN(STN8815_PIN_F3, "GPIO56_F3"),
|
||||
PINCTRL_PIN(STN8815_PIN_F2, "GPIO57_F2"),
|
||||
PINCTRL_PIN(STN8815_PIN_E1, "GPIO58_E1"),
|
||||
PINCTRL_PIN(STN8815_PIN_E3, "GPIO59_E3"),
|
||||
PINCTRL_PIN(STN8815_PIN_E2, "GPIO60_E2"),
|
||||
PINCTRL_PIN(STN8815_PIN_E4, "GPIO61_E4"),
|
||||
PINCTRL_PIN(STN8815_PIN_D3, "GPIO62_D3"),
|
||||
PINCTRL_PIN(STN8815_PIN_D2, "GPIO63_D2"),
|
||||
PINCTRL_PIN(STN8815_PIN_F21, "GPIO64_F21"),
|
||||
PINCTRL_PIN(STN8815_PIN_F20, "GPIO65_F20"),
|
||||
PINCTRL_PIN(STN8815_PIN_E22, "GPIO66_E22"),
|
||||
PINCTRL_PIN(STN8815_PIN_D22, "GPIO67_D22"),
|
||||
PINCTRL_PIN(STN8815_PIN_E21, "GPIO68_E21"),
|
||||
PINCTRL_PIN(STN8815_PIN_E20, "GPIO69_E20"),
|
||||
PINCTRL_PIN(STN8815_PIN_C22, "GPIO70_C22"),
|
||||
PINCTRL_PIN(STN8815_PIN_D21, "GPIO71_D21"),
|
||||
PINCTRL_PIN(STN8815_PIN_D20, "GPIO72_D20"),
|
||||
PINCTRL_PIN(STN8815_PIN_C21, "GPIO73_C21"),
|
||||
PINCTRL_PIN(STN8815_PIN_C20, "GPIO74_C20"),
|
||||
PINCTRL_PIN(STN8815_PIN_C19, "GPIO75_C19"),
|
||||
PINCTRL_PIN(STN8815_PIN_B20, "GPIO76_B20"),
|
||||
PINCTRL_PIN(STN8815_PIN_B8, "GPIO77_B8"),
|
||||
PINCTRL_PIN(STN8815_PIN_A8, "GPIO78_A8"),
|
||||
PINCTRL_PIN(STN8815_PIN_C9, "GPIO79_C9"),
|
||||
PINCTRL_PIN(STN8815_PIN_B9, "GPIO80_B9"),
|
||||
PINCTRL_PIN(STN8815_PIN_A9, "GPIO81_A9"),
|
||||
PINCTRL_PIN(STN8815_PIN_C10, "GPIO82_C10"),
|
||||
PINCTRL_PIN(STN8815_PIN_K1, "GPIO83_K1"),
|
||||
PINCTRL_PIN(STN8815_PIN_K3, "GPIO84_K3"),
|
||||
PINCTRL_PIN(STN8815_PIN_K2, "GPIO85_K2"),
|
||||
PINCTRL_PIN(STN8815_PIN_J1, "GPIO86_J1"),
|
||||
PINCTRL_PIN(STN8815_PIN_J3, "GPIO87_J3"),
|
||||
PINCTRL_PIN(STN8815_PIN_J2, "GPIO88_J2"),
|
||||
PINCTRL_PIN(STN8815_PIN_H1, "GPIO89_H1"),
|
||||
PINCTRL_PIN(STN8815_PIN_H3, "GPIO90_H3"),
|
||||
PINCTRL_PIN(STN8815_PIN_H2, "GPIO91_H2"),
|
||||
PINCTRL_PIN(STN8815_PIN_G1, "GPIO92_G1"),
|
||||
PINCTRL_PIN(STN8815_PIN_G3, "GPIO93_G3"),
|
||||
PINCTRL_PIN(STN8815_PIN_G2, "GPIO94_G2"),
|
||||
PINCTRL_PIN(STN8815_PIN_F1, "GPIO95_F1"),
|
||||
PINCTRL_PIN(STN8815_PIN_T20, "GPIO96_T20"),
|
||||
PINCTRL_PIN(STN8815_PIN_R21, "GPIO97_R21"),
|
||||
PINCTRL_PIN(STN8815_PIN_R20, "GPIO98_R20"),
|
||||
PINCTRL_PIN(STN8815_PIN_U22, "GPIO99_U22"),
|
||||
PINCTRL_PIN(STN8815_PIN_N21, "GPIO100_N21"),
|
||||
PINCTRL_PIN(STN8815_PIN_N20, "GPIO101_N20"),
|
||||
PINCTRL_PIN(STN8815_PIN_P22, "GPIO102_P22"),
|
||||
PINCTRL_PIN(STN8815_PIN_N22, "GPIO103_N22"),
|
||||
PINCTRL_PIN(STN8815_PIN_V22, "GPIO104_V22"),
|
||||
PINCTRL_PIN(STN8815_PIN_V21, "GPIO105_V21"),
|
||||
PINCTRL_PIN(STN8815_PIN_K22, "GPIO106_K22"),
|
||||
PINCTRL_PIN(STN8815_PIN_K21, "GPIO107_K21"),
|
||||
PINCTRL_PIN(STN8815_PIN_H20, "GPIO108_H20"),
|
||||
PINCTRL_PIN(STN8815_PIN_G20, "GPIO109_G20"),
|
||||
PINCTRL_PIN(STN8815_PIN_L21, "GPIO110_L21"),
|
||||
PINCTRL_PIN(STN8815_PIN_H21, "GPIO111_H21"),
|
||||
PINCTRL_PIN(STN8815_PIN_J21, "GPIO112_J21"),
|
||||
PINCTRL_PIN(STN8815_PIN_H22, "GPIO113_H22"),
|
||||
PINCTRL_PIN(STN8815_PIN_K20, "GPIO114_K20"),
|
||||
PINCTRL_PIN(STN8815_PIN_L22, "GPIO115_L22"),
|
||||
PINCTRL_PIN(STN8815_PIN_G21, "GPIO116_G21"),
|
||||
PINCTRL_PIN(STN8815_PIN_J20, "GPIO117_J20"),
|
||||
PINCTRL_PIN(STN8815_PIN_G22, "GPIO118_G22"),
|
||||
PINCTRL_PIN(STN8815_PIN_U19, "GPIO119_U19"),
|
||||
PINCTRL_PIN(STN8815_PIN_G19, "GPIO120_G19"),
|
||||
PINCTRL_PIN(STN8815_PIN_M22, "GPIO121_M22"),
|
||||
PINCTRL_PIN(STN8815_PIN_M19, "GPIO122_M19"),
|
||||
PINCTRL_PIN(STN8815_PIN_J22, "GPIO123_J22"),
|
||||
};
|
||||
|
||||
#define STN8815_GPIO_RANGE(a, b, c) { .name = "STN8815", .id = a, .base = b, \
|
||||
.pin_base = b, .npins = c }
|
||||
|
||||
/*
|
||||
* This matches the 32-pin gpio chips registered by the GPIO portion. This
|
||||
* cannot be const since we assign the struct gpio_chip * pointer at runtime.
|
||||
*/
|
||||
static struct pinctrl_gpio_range nmk_stn8815_ranges[] = {
|
||||
STN8815_GPIO_RANGE(0, 0, 32),
|
||||
STN8815_GPIO_RANGE(1, 32, 32),
|
||||
STN8815_GPIO_RANGE(2, 64, 32),
|
||||
STN8815_GPIO_RANGE(3, 96, 28),
|
||||
};
|
||||
|
||||
/*
|
||||
* Read the pin group names like this:
|
||||
* u0_a_1 = first groups of pins for uart0 on alt function a
|
||||
* i2c2_b_2 = second group of pins for i2c2 on alt function b
|
||||
*/
|
||||
|
||||
/* Altfunction A */
|
||||
static const unsigned u0_a_1_pins[] = { STN8815_PIN_B4, STN8815_PIN_D5,
|
||||
STN8815_PIN_C5, STN8815_PIN_A4, STN8815_PIN_B5, STN8815_PIN_D6,
|
||||
STN8815_PIN_C6, STN8815_PIN_B6 };
|
||||
static const unsigned mmcsd_a_1_pins[] = { STN8815_PIN_B10, STN8815_PIN_A10,
|
||||
STN8815_PIN_C11, STN8815_PIN_B11, STN8815_PIN_A11, STN8815_PIN_C12,
|
||||
STN8815_PIN_B12, STN8815_PIN_A12, STN8815_PIN_C13, STN8815_PIN_C15 };
|
||||
static const unsigned u1_a_1_pins[] = { STN8815_PIN_M2, STN8815_PIN_L1,
|
||||
STN8815_PIN_F3, STN8815_PIN_F2 };
|
||||
static const unsigned i2c1_a_1_pins[] = { STN8815_PIN_L4, STN8815_PIN_L3 };
|
||||
static const unsigned i2c0_a_1_pins[] = { STN8815_PIN_D3, STN8815_PIN_D2 };
|
||||
/* Altfunction B */
|
||||
static const unsigned u1_b_1_pins[] = { STN8815_PIN_B16, STN8815_PIN_A16 };
|
||||
static const unsigned i2cusb_b_1_pins[] = { STN8815_PIN_C21, STN8815_PIN_C20 };
|
||||
|
||||
#define STN8815_PIN_GROUP(a,b) { .name = #a, .pins = a##_pins, \
|
||||
.npins = ARRAY_SIZE(a##_pins), .altsetting = b }
|
||||
|
||||
static const struct nmk_pingroup nmk_stn8815_groups[] = {
|
||||
STN8815_PIN_GROUP(u0_a_1, NMK_GPIO_ALT_A),
|
||||
STN8815_PIN_GROUP(mmcsd_a_1, NMK_GPIO_ALT_A),
|
||||
STN8815_PIN_GROUP(u1_a_1, NMK_GPIO_ALT_A),
|
||||
STN8815_PIN_GROUP(i2c1_a_1, NMK_GPIO_ALT_A),
|
||||
STN8815_PIN_GROUP(i2c0_a_1, NMK_GPIO_ALT_A),
|
||||
STN8815_PIN_GROUP(u1_b_1, NMK_GPIO_ALT_B),
|
||||
STN8815_PIN_GROUP(i2cusb_b_1, NMK_GPIO_ALT_B),
|
||||
};
|
||||
|
||||
/* We use this macro to define the groups applicable to a function */
|
||||
#define STN8815_FUNC_GROUPS(a, b...) \
|
||||
static const char * const a##_groups[] = { b };
|
||||
|
||||
STN8815_FUNC_GROUPS(u0, "u0_a_1");
|
||||
STN8815_FUNC_GROUPS(mmcsd, "mmcsd_a_1");
|
||||
STN8815_FUNC_GROUPS(u1, "u1_a_1", "u1_b_1");
|
||||
STN8815_FUNC_GROUPS(i2c1, "i2c1_a_1");
|
||||
STN8815_FUNC_GROUPS(i2c0, "i2c0_a_1");
|
||||
STN8815_FUNC_GROUPS(i2cusb, "i2cusb_b_1");
|
||||
|
||||
#define FUNCTION(fname) \
|
||||
{ \
|
||||
.name = #fname, \
|
||||
.groups = fname##_groups, \
|
||||
.ngroups = ARRAY_SIZE(fname##_groups), \
|
||||
}
|
||||
|
||||
static const struct nmk_function nmk_stn8815_functions[] = {
|
||||
FUNCTION(u0),
|
||||
FUNCTION(mmcsd),
|
||||
FUNCTION(u1),
|
||||
FUNCTION(i2c1),
|
||||
FUNCTION(i2c0),
|
||||
FUNCTION(i2cusb),
|
||||
};
|
||||
|
||||
static const struct nmk_pinctrl_soc_data nmk_stn8815_soc = {
|
||||
.gpio_ranges = nmk_stn8815_ranges,
|
||||
.gpio_num_ranges = ARRAY_SIZE(nmk_stn8815_ranges),
|
||||
.pins = nmk_stn8815_pins,
|
||||
.npins = ARRAY_SIZE(nmk_stn8815_pins),
|
||||
.functions = nmk_stn8815_functions,
|
||||
.nfunctions = ARRAY_SIZE(nmk_stn8815_functions),
|
||||
.groups = nmk_stn8815_groups,
|
||||
.ngroups = ARRAY_SIZE(nmk_stn8815_groups),
|
||||
};
|
||||
|
||||
void __devinit
|
||||
nmk_pinctrl_stn8815_init(const struct nmk_pinctrl_soc_data **soc)
|
||||
{
|
||||
*soc = &nmk_stn8815_soc;
|
||||
}
|
||||
|
|
@ -819,6 +819,7 @@ static struct irq_chip nmk_gpio_irq_chip = {
|
|||
.irq_set_wake = nmk_gpio_irq_set_wake,
|
||||
.irq_startup = nmk_gpio_irq_startup,
|
||||
.irq_shutdown = nmk_gpio_irq_shutdown,
|
||||
.flags = IRQCHIP_MASK_ON_SUSPEND,
|
||||
};
|
||||
|
||||
static void __nmk_gpio_irq_handler(unsigned int irq, struct irq_desc *desc,
|
||||
|
|
@ -826,16 +827,14 @@ static void __nmk_gpio_irq_handler(unsigned int irq, struct irq_desc *desc,
|
|||
{
|
||||
struct nmk_gpio_chip *nmk_chip;
|
||||
struct irq_chip *host_chip = irq_get_chip(irq);
|
||||
unsigned int first_irq;
|
||||
|
||||
chained_irq_enter(host_chip, desc);
|
||||
|
||||
nmk_chip = irq_get_handler_data(irq);
|
||||
first_irq = nmk_chip->domain->revmap_data.legacy.first_irq;
|
||||
while (status) {
|
||||
int bit = __ffs(status);
|
||||
|
||||
generic_handle_irq(first_irq + bit);
|
||||
generic_handle_irq(irq_find_mapping(nmk_chip->domain, bit));
|
||||
status &= ~BIT(bit);
|
||||
}
|
||||
|
||||
|
|
@ -1720,8 +1719,12 @@ static int __devinit nmk_pinctrl_probe(struct platform_device *pdev)
|
|||
of_match_device(nmk_pinctrl_match, &pdev->dev)->data;
|
||||
|
||||
/* Poke in other ASIC variants here */
|
||||
if (version == PINCTRL_NMK_STN8815)
|
||||
nmk_pinctrl_stn8815_init(&npct->soc);
|
||||
if (version == PINCTRL_NMK_DB8500)
|
||||
nmk_pinctrl_db8500_init(&npct->soc);
|
||||
if (version == PINCTRL_NMK_DB8540)
|
||||
nmk_pinctrl_db8540_init(&npct->soc);
|
||||
|
||||
/*
|
||||
* We need all the GPIO drivers to probe FIRST, or we will not be able
|
||||
|
|
@ -1772,6 +1775,7 @@ static struct platform_driver nmk_gpio_driver = {
|
|||
static const struct platform_device_id nmk_pinctrl_id[] = {
|
||||
{ "pinctrl-stn8815", PINCTRL_NMK_STN8815 },
|
||||
{ "pinctrl-db8500", PINCTRL_NMK_DB8500 },
|
||||
{ "pinctrl-db8540", PINCTRL_NMK_DB8540 },
|
||||
};
|
||||
|
||||
static struct platform_driver nmk_pinctrl_driver = {
|
||||
|
|
|
|||
|
|
@ -6,6 +6,7 @@
|
|||
/* Package definitions */
|
||||
#define PINCTRL_NMK_STN8815 0
|
||||
#define PINCTRL_NMK_DB8500 1
|
||||
#define PINCTRL_NMK_DB8540 2
|
||||
|
||||
/**
|
||||
* struct nmk_function - Nomadik pinctrl mux function
|
||||
|
|
@ -61,6 +62,19 @@ struct nmk_pinctrl_soc_data {
|
|||
unsigned ngroups;
|
||||
};
|
||||
|
||||
#ifdef CONFIG_PINCTRL_STN8815
|
||||
|
||||
void nmk_pinctrl_stn8815_init(const struct nmk_pinctrl_soc_data **soc);
|
||||
|
||||
#else
|
||||
|
||||
static inline void
|
||||
nmk_pinctrl_stn8815_init(const struct nmk_pinctrl_soc_data **soc)
|
||||
{
|
||||
}
|
||||
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_PINCTRL_DB8500
|
||||
|
||||
void nmk_pinctrl_db8500_init(const struct nmk_pinctrl_soc_data **soc);
|
||||
|
|
@ -74,4 +88,17 @@ nmk_pinctrl_db8500_init(const struct nmk_pinctrl_soc_data **soc)
|
|||
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_PINCTRL_DB8540
|
||||
|
||||
void nmk_pinctrl_db8540_init(const struct nmk_pinctrl_soc_data **soc);
|
||||
|
||||
#else
|
||||
|
||||
static inline void
|
||||
nmk_pinctrl_db8540_init(const struct nmk_pinctrl_soc_data **soc)
|
||||
{
|
||||
}
|
||||
|
||||
#endif
|
||||
|
||||
#endif /* PINCTRL_PINCTRL_NOMADIK_H */
|
||||
|
|
|
|||
|
|
@ -26,7 +26,8 @@
|
|||
#include "core.h"
|
||||
|
||||
#define DRIVER_NAME "pinctrl-single"
|
||||
#define PCS_MUX_NAME "pinctrl-single,pins"
|
||||
#define PCS_MUX_PINS_NAME "pinctrl-single,pins"
|
||||
#define PCS_MUX_BITS_NAME "pinctrl-single,bits"
|
||||
#define PCS_REG_NAME_LEN ((sizeof(unsigned long) * 2) + 1)
|
||||
#define PCS_OFF_DISABLED ~0U
|
||||
|
||||
|
|
@ -54,6 +55,7 @@ struct pcs_pingroup {
|
|||
struct pcs_func_vals {
|
||||
void __iomem *reg;
|
||||
unsigned val;
|
||||
unsigned mask;
|
||||
};
|
||||
|
||||
/**
|
||||
|
|
@ -139,6 +141,7 @@ struct pcs_device {
|
|||
unsigned fshift;
|
||||
unsigned foff;
|
||||
unsigned fmax;
|
||||
bool bits_per_mux;
|
||||
struct pcs_name *names;
|
||||
struct pcs_data pins;
|
||||
struct radix_tree_root pgtree;
|
||||
|
|
@ -243,7 +246,15 @@ static void pcs_pin_dbg_show(struct pinctrl_dev *pctldev,
|
|||
struct seq_file *s,
|
||||
unsigned offset)
|
||||
{
|
||||
seq_printf(s, " " DRIVER_NAME);
|
||||
struct pcs_device *pcs;
|
||||
unsigned val;
|
||||
|
||||
pcs = pinctrl_dev_get_drvdata(pctldev);
|
||||
|
||||
val = pcs->read(pcs->base + offset);
|
||||
val &= pcs->fmask;
|
||||
|
||||
seq_printf(s, "%08x %s " , val, DRIVER_NAME);
|
||||
}
|
||||
|
||||
static void pcs_dt_free_map(struct pinctrl_dev *pctldev,
|
||||
|
|
@ -332,12 +343,17 @@ static int pcs_enable(struct pinctrl_dev *pctldev, unsigned fselector,
|
|||
|
||||
for (i = 0; i < func->nvals; i++) {
|
||||
struct pcs_func_vals *vals;
|
||||
unsigned val;
|
||||
unsigned val, mask;
|
||||
|
||||
vals = &func->vals[i];
|
||||
val = pcs->read(vals->reg);
|
||||
val &= ~pcs->fmask;
|
||||
val |= vals->val;
|
||||
if (!vals->mask)
|
||||
mask = pcs->fmask;
|
||||
else
|
||||
mask = pcs->fmask & vals->mask;
|
||||
|
||||
val &= ~mask;
|
||||
val |= (vals->val & mask);
|
||||
pcs->write(val, vals->reg);
|
||||
}
|
||||
|
||||
|
|
@ -657,18 +673,29 @@ static int pcs_parse_one_pinctrl_entry(struct pcs_device *pcs,
|
|||
{
|
||||
struct pcs_func_vals *vals;
|
||||
const __be32 *mux;
|
||||
int size, rows, *pins, index = 0, found = 0, res = -ENOMEM;
|
||||
int size, params, rows, *pins, index = 0, found = 0, res = -ENOMEM;
|
||||
struct pcs_function *function;
|
||||
|
||||
mux = of_get_property(np, PCS_MUX_NAME, &size);
|
||||
if ((!mux) || (size < sizeof(*mux) * 2)) {
|
||||
dev_err(pcs->dev, "bad data for mux %s\n",
|
||||
np->name);
|
||||
if (pcs->bits_per_mux) {
|
||||
params = 3;
|
||||
mux = of_get_property(np, PCS_MUX_BITS_NAME, &size);
|
||||
} else {
|
||||
params = 2;
|
||||
mux = of_get_property(np, PCS_MUX_PINS_NAME, &size);
|
||||
}
|
||||
|
||||
if (!mux) {
|
||||
dev_err(pcs->dev, "no valid property for %s\n", np->name);
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
if (size < (sizeof(*mux) * params)) {
|
||||
dev_err(pcs->dev, "bad data for %s\n", np->name);
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
size /= sizeof(*mux); /* Number of elements in array */
|
||||
rows = size / 2; /* Each row is a key value pair */
|
||||
rows = size / params;
|
||||
|
||||
vals = devm_kzalloc(pcs->dev, sizeof(*vals) * rows, GFP_KERNEL);
|
||||
if (!vals)
|
||||
|
|
@ -686,6 +713,10 @@ static int pcs_parse_one_pinctrl_entry(struct pcs_device *pcs,
|
|||
val = be32_to_cpup(mux + index++);
|
||||
vals[found].reg = pcs->base + offset;
|
||||
vals[found].val = val;
|
||||
if (params == 3) {
|
||||
val = be32_to_cpup(mux + index++);
|
||||
vals[found].mask = val;
|
||||
}
|
||||
|
||||
pin = pcs_get_pin_by_offset(pcs, offset);
|
||||
if (pin < 0) {
|
||||
|
|
@ -883,6 +914,9 @@ static int __devinit pcs_probe(struct platform_device *pdev)
|
|||
if (ret)
|
||||
pcs->foff = PCS_OFF_DISABLED;
|
||||
|
||||
pcs->bits_per_mux = of_property_read_bool(np,
|
||||
"pinctrl-single,bit-per-mux");
|
||||
|
||||
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
|
||||
if (!res) {
|
||||
dev_err(pcs->dev, "could not get resource\n");
|
||||
|
|
|
|||
|
|
@ -25,6 +25,7 @@
|
|||
#include <linux/bitops.h>
|
||||
#include <linux/gpio.h>
|
||||
#include <linux/of_gpio.h>
|
||||
#include <asm/mach/irq.h>
|
||||
|
||||
#define DRIVER_NAME "pinmux-sirf"
|
||||
|
||||
|
|
@ -69,6 +70,10 @@ static DEFINE_SPINLOCK(sgpio_lock);
|
|||
* refer to CS-131858-DC-6A.xls
|
||||
*/
|
||||
static const struct pinctrl_pin_desc sirfsoc_pads[] = {
|
||||
PINCTRL_PIN(0, "gpio0-0"),
|
||||
PINCTRL_PIN(1, "gpio0-1"),
|
||||
PINCTRL_PIN(2, "gpio0-2"),
|
||||
PINCTRL_PIN(3, "gpio0-3"),
|
||||
PINCTRL_PIN(4, "pwm0"),
|
||||
PINCTRL_PIN(5, "pwm1"),
|
||||
PINCTRL_PIN(6, "pwm2"),
|
||||
|
|
@ -77,7 +82,9 @@ static const struct pinctrl_pin_desc sirfsoc_pads[] = {
|
|||
PINCTRL_PIN(9, "odo_0"),
|
||||
PINCTRL_PIN(10, "odo_1"),
|
||||
PINCTRL_PIN(11, "dr_dir"),
|
||||
PINCTRL_PIN(12, "viprom_fa"),
|
||||
PINCTRL_PIN(13, "scl_1"),
|
||||
PINCTRL_PIN(14, "ntrst"),
|
||||
PINCTRL_PIN(15, "sda_1"),
|
||||
PINCTRL_PIN(16, "x_ldd[16]"),
|
||||
PINCTRL_PIN(17, "x_ldd[17]"),
|
||||
|
|
@ -1260,8 +1267,10 @@ static int __devinit sirfsoc_pinmux_probe(struct platform_device *pdev)
|
|||
goto out_no_pmx;
|
||||
}
|
||||
|
||||
for (i = 0; i < ARRAY_SIZE(sirfsoc_gpio_ranges); i++)
|
||||
for (i = 0; i < ARRAY_SIZE(sirfsoc_gpio_ranges); i++) {
|
||||
sirfsoc_gpio_ranges[i].gc = &sgpio_bank[i].chip.gc;
|
||||
pinctrl_add_gpio_range(spmx->pmx, &sirfsoc_gpio_ranges[i]);
|
||||
}
|
||||
|
||||
dev_info(&pdev->dev, "initialized SIRFSOC pinmux driver\n");
|
||||
|
||||
|
|
@ -1475,6 +1484,9 @@ static void sirfsoc_gpio_handle_irq(unsigned int irq, struct irq_desc *desc)
|
|||
u32 status, ctrl;
|
||||
int idx = 0;
|
||||
unsigned int first_irq;
|
||||
struct irq_chip *chip = irq_get_chip(irq);
|
||||
|
||||
chained_irq_enter(chip, desc);
|
||||
|
||||
status = readl(bank->chip.regs + SIRFSOC_GPIO_INT_STATUS(bank->id));
|
||||
if (!status) {
|
||||
|
|
@ -1503,20 +1515,17 @@ static void sirfsoc_gpio_handle_irq(unsigned int irq, struct irq_desc *desc)
|
|||
idx++;
|
||||
status = status >> 1;
|
||||
}
|
||||
|
||||
chained_irq_exit(chip, desc);
|
||||
}
|
||||
|
||||
static inline void sirfsoc_gpio_set_input(struct sirfsoc_gpio_bank *bank, unsigned ctrl_offset)
|
||||
{
|
||||
u32 val;
|
||||
unsigned long flags;
|
||||
|
||||
spin_lock_irqsave(&bank->lock, flags);
|
||||
|
||||
val = readl(bank->chip.regs + ctrl_offset);
|
||||
val &= ~SIRFSOC_GPIO_CTL_OUT_EN_MASK;
|
||||
writel(val, bank->chip.regs + ctrl_offset);
|
||||
|
||||
spin_unlock_irqrestore(&bank->lock, flags);
|
||||
}
|
||||
|
||||
static int sirfsoc_gpio_request(struct gpio_chip *chip, unsigned offset)
|
||||
|
|
@ -1726,6 +1735,8 @@ static int __devinit sirfsoc_gpio_probe(struct device_node *np)
|
|||
irq_set_handler_data(bank->parent_irq, bank);
|
||||
}
|
||||
|
||||
return 0;
|
||||
|
||||
out:
|
||||
iounmap(regs);
|
||||
return err;
|
||||
|
|
|
|||
|
|
@ -232,14 +232,11 @@ int pinmux_request_gpio(struct pinctrl_dev *pctldev,
|
|||
struct pinctrl_gpio_range *range,
|
||||
unsigned pin, unsigned gpio)
|
||||
{
|
||||
char gpiostr[16];
|
||||
const char *owner;
|
||||
int ret;
|
||||
|
||||
/* Conjure some name stating what chip and pin this is taken by */
|
||||
snprintf(gpiostr, 15, "%s:%d", range->name, gpio);
|
||||
|
||||
owner = kstrdup(gpiostr, GFP_KERNEL);
|
||||
owner = kasprintf(GFP_KERNEL, "%s:%d", range->name, gpio);
|
||||
if (!owner)
|
||||
return -EINVAL;
|
||||
|
||||
|
|
|
|||
|
|
@ -140,7 +140,7 @@ static inline struct pinctrl * __must_check devm_pinctrl_get_select(
|
|||
s = pinctrl_lookup_state(p, name);
|
||||
if (IS_ERR(s)) {
|
||||
devm_pinctrl_put(p);
|
||||
return ERR_PTR(PTR_ERR(s));
|
||||
return ERR_CAST(s);
|
||||
}
|
||||
|
||||
ret = pinctrl_select_state(p, s);
|
||||
|
|
|
|||
|
|
@ -6,13 +6,18 @@
|
|||
* @PINCTRL_STATE_DEFAULT: the state the pinctrl handle shall be put
|
||||
* into as default, usually this means the pins are up and ready to
|
||||
* be used by the device driver. This state is commonly used by
|
||||
* hogs to configure muxing and pins at boot.
|
||||
* hogs to configure muxing and pins at boot, and also as a state
|
||||
* to go into when returning from sleep and idle in
|
||||
* .pm_runtime_resume() or ordinary .resume() for example.
|
||||
* @PINCTRL_STATE_IDLE: the state the pinctrl handle shall be put into
|
||||
* when the pins are idle. Could typically be set from a
|
||||
* pm_runtime_suspend() operation.
|
||||
* when the pins are idle. This is a state where the system is relaxed
|
||||
* but not fully sleeping - some power may be on but clocks gated for
|
||||
* example. Could typically be set from a pm_runtime_suspend() or
|
||||
* pm_runtime_idle() operation.
|
||||
* @PINCTRL_STATE_SLEEP: the state the pinctrl handle shall be put into
|
||||
* when the pins are sleeping. Could typically be set from a
|
||||
* common suspend() function.
|
||||
* when the pins are sleeping. This is a state where the system is in
|
||||
* its lowest sleep state. Could typically be set from an
|
||||
* ordinary .suspend() function.
|
||||
*/
|
||||
#define PINCTRL_STATE_DEFAULT "default"
|
||||
#define PINCTRL_STATE_IDLE "idle"
|
||||
|
|
|
|||
Loading…
Reference in a new issue