Staging: winbond: Fix Sparse Warnings in phy_calibration.c
This patch fixes Sparse Warnings "symbol was not declared. Should it be static?" and "defined but not used [-Wunused-function]" in phy_calibration.c Signed-off-by: Ebru Akagunduz <ebru.akagunduz@gmail.com> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
This commit is contained in:
Ebru Akagunduz
Greg Kroah-Hartman
parent
f0c80e4e1c
commit
06c789ed3b
1 changed files with 16 additions and 299 deletions
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@ -44,7 +44,7 @@ static const s32 Angles[] = {
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/****************** FUNCTION DEFINITION SECTION *****************************/
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s32 _s13_to_s32(u32 data)
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static s32 _s13_to_s32(u32 data)
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{
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u32 val;
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@ -56,22 +56,8 @@ s32 _s13_to_s32(u32 data)
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return (s32) val;
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}
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u32 _s32_to_s13(s32 data)
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{
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u32 val;
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if (data > 4095)
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data = 4095;
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else if (data < -4096)
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data = -4096;
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val = data & 0x1FFF;
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return val;
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}
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/****************************************************************************/
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s32 _s4_to_s32(u32 data)
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static s32 _s4_to_s32(u32 data)
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{
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s32 val;
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@ -83,7 +69,7 @@ s32 _s4_to_s32(u32 data)
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return val;
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}
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u32 _s32_to_s4(s32 data)
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static u32 _s32_to_s4(s32 data)
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{
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u32 val;
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@ -98,7 +84,7 @@ u32 _s32_to_s4(s32 data)
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}
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/****************************************************************************/
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s32 _s5_to_s32(u32 data)
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static s32 _s5_to_s32(u32 data)
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{
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s32 val;
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@ -110,7 +96,7 @@ s32 _s5_to_s32(u32 data)
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return val;
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}
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u32 _s32_to_s5(s32 data)
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static u32 _s32_to_s5(s32 data)
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{
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u32 val;
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@ -125,7 +111,7 @@ u32 _s32_to_s5(s32 data)
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}
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/****************************************************************************/
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s32 _s6_to_s32(u32 data)
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static s32 _s6_to_s32(u32 data)
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{
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s32 val;
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@ -137,7 +123,7 @@ s32 _s6_to_s32(u32 data)
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return val;
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}
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u32 _s32_to_s6(s32 data)
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static u32 _s32_to_s6(s32 data)
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{
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u32 val;
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@ -152,34 +138,7 @@ u32 _s32_to_s6(s32 data)
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}
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/****************************************************************************/
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s32 _s9_to_s32(u32 data)
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{
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s32 val;
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val = data & 0x00FF;
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if ((data & BIT(8)) != 0)
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val |= 0xFFFFFF00;
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return val;
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}
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u32 _s32_to_s9(s32 data)
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{
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u32 val;
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if (data > 255)
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data = 255;
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else if (data < -256)
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data = -256;
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val = data & 0x01FF;
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return val;
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}
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/****************************************************************************/
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s32 _floor(s32 n)
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static s32 _floor(s32 n)
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{
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if (n > 0)
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n += 5;
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@ -195,7 +154,7 @@ s32 _floor(s32 n)
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* sqsum is the input and the output is sq_rt;
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* The maximum of sqsum = 2^27 -1;
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*/
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u32 _sqrt(u32 sqsum)
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static u32 _sqrt(u32 sqsum)
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{
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u32 sq_rt;
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@ -263,7 +222,7 @@ u32 _sqrt(u32 sqsum)
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}
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/****************************************************************************/
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void _sin_cos(s32 angle, s32 *sin, s32 *cos)
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static void _sin_cos(s32 angle, s32 *sin, s32 *cos)
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{
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s32 X, Y, TargetAngle, CurrAngle;
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unsigned Step;
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@ -320,7 +279,7 @@ static unsigned char hal_set_dxx_reg(struct hw_data *pHwData, u16 number,
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#define hw_set_dxx_reg(_A, _B, _C) hal_set_dxx_reg(_A, _B, (u32)_C)
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void _reset_rx_cal(struct hw_data *phw_data)
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static void _reset_rx_cal(struct hw_data *phw_data)
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{
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u32 val;
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@ -340,7 +299,7 @@ void _reset_rx_cal(struct hw_data *phw_data)
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/**********************************************/
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void _rxadc_dc_offset_cancellation_winbond(struct hw_data *phw_data, u32 frequency)
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static void _rxadc_dc_offset_cancellation_winbond(struct hw_data *phw_data, u32 frequency)
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{
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u32 reg_agc_ctrl3;
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u32 reg_a_acq_ctrl;
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@ -435,250 +394,8 @@ void _rxadc_dc_offset_cancellation_winbond(struct hw_data *phw_data, u32 frequen
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hw_set_dxx_reg(phw_data, REG_AGC_CTRL3, reg_agc_ctrl3);
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}
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/****************************************************************/
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void _txidac_dc_offset_cancellation_winbond(struct hw_data *phw_data)
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{
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u32 reg_agc_ctrl3;
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u32 reg_mode_ctrl;
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u32 reg_dc_cancel;
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s32 iqcal_image_i;
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s32 iqcal_image_q;
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u32 sqsum;
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s32 mag_0;
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s32 mag_1;
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s32 fix_cancel_dc_i = 0;
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u32 val;
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int loop;
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PHY_DEBUG(("[CAL] -> [2]_txidac_dc_offset_cancellation()\n"));
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/* a. Set to "TX calibration mode" */
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/* 0x01 0xEE3FC2 ; 3B8FF ; Calibration (6a). enable TX IQ calibration loop circuits */
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phy_set_rf_data(phw_data, 1, (1<<24)|0xEE3FC2);
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/* 0x0B 0x1905D6 ; 06417 ; Calibration (6b). enable TX I/Q cal loop squaring circuit */
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phy_set_rf_data(phw_data, 11, (11<<24)|0x1901D6);
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/* 0x05 0x24C60A ; 09318 ; Calibration (6c). setting TX-VGA gain: TXGCH=2 & GPK=110 --> to be optimized */
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phy_set_rf_data(phw_data, 5, (5<<24)|0x24C48A);
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/* 0x06 0x06880C ; 01A20 ; Calibration (6d). RXGCH=00; RXGCL=100 000 (RXVGA=32) --> to be optimized */
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phy_set_rf_data(phw_data, 6, (6<<24)|0x06890C);
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/* 0x00 0xFDF1C0 ; 3F7C7 ; Calibration (6e). turn on IQ imbalance/Test mode */
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phy_set_rf_data(phw_data, 0, (0<<24)|0xFDF1C0);
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hw_set_dxx_reg(phw_data, 0x58, 0x30303030); /* IQ_Alpha Changed */
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/* a. Disable AGC */
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hw_get_dxx_reg(phw_data, REG_AGC_CTRL3, ®_agc_ctrl3);
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reg_agc_ctrl3 &= ~BIT(2);
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reg_agc_ctrl3 |= (MASK_LNA_FIX_GAIN|MASK_AGC_FIX);
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hw_set_dxx_reg(phw_data, REG_AGC_CTRL3, reg_agc_ctrl3);
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hw_get_dxx_reg(phw_data, REG_AGC_CTRL5, &val);
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val |= MASK_AGC_FIX_GAIN;
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hw_set_dxx_reg(phw_data, REG_AGC_CTRL5, val);
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/* b. set iqcal_mode[1:0] to 0x2 and set iqcal_tone[3:2] to 0 */
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hw_get_dxx_reg(phw_data, REG_MODE_CTRL, ®_mode_ctrl);
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PHY_DEBUG(("[CAL] MODE_CTRL (read) = 0x%08X\n", reg_mode_ctrl));
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reg_mode_ctrl &= ~(MASK_IQCAL_TONE_SEL|MASK_IQCAL_MODE);
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/* mode=2, tone=0 */
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/* reg_mode_ctrl |= (MASK_CALIB_START|2); */
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/* mode=2, tone=1 */
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/* reg_mode_ctrl |= (MASK_CALIB_START|2|(1<<2)); */
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/* mode=2, tone=2 */
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reg_mode_ctrl |= (MASK_CALIB_START|2|(2<<2));
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hw_set_dxx_reg(phw_data, REG_MODE_CTRL, reg_mode_ctrl);
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PHY_DEBUG(("[CAL] MODE_CTRL (write) = 0x%08X\n", reg_mode_ctrl));
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hw_get_dxx_reg(phw_data, 0x5C, ®_dc_cancel);
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PHY_DEBUG(("[CAL] DC_CANCEL (read) = 0x%08X\n", reg_dc_cancel));
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for (loop = 0; loop < LOOP_TIMES; loop++) {
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PHY_DEBUG(("[CAL] [%d.] ==================================\n", loop));
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/* c. reset cancel_dc_i[9:5] and cancel_dc_q[4:0] in register DC_Cancel */
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reg_dc_cancel &= ~(0x03FF);
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PHY_DEBUG(("[CAL] DC_CANCEL (write) = 0x%08X\n", reg_dc_cancel));
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hw_set_dxx_reg(phw_data, 0x5C, reg_dc_cancel);
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hw_get_dxx_reg(phw_data, REG_CALIB_READ2, &val);
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PHY_DEBUG(("[CAL] CALIB_READ2 = 0x%08X\n", val));
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iqcal_image_i = _s13_to_s32(val & 0x00001FFF);
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iqcal_image_q = _s13_to_s32((val & 0x03FFE000) >> 13);
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sqsum = iqcal_image_i*iqcal_image_i + iqcal_image_q*iqcal_image_q;
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mag_0 = (s32) _sqrt(sqsum);
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PHY_DEBUG(("[CAL] mag_0=%d (iqcal_image_i=%d, iqcal_image_q=%d)\n",
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mag_0, iqcal_image_i, iqcal_image_q));
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/* d. */
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reg_dc_cancel |= (1 << CANCEL_DC_I_SHIFT);
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PHY_DEBUG(("[CAL] DC_CANCEL (write) = 0x%08X\n", reg_dc_cancel));
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hw_set_dxx_reg(phw_data, 0x5C, reg_dc_cancel);
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hw_get_dxx_reg(phw_data, REG_CALIB_READ2, &val);
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PHY_DEBUG(("[CAL] CALIB_READ2 = 0x%08X\n", val));
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iqcal_image_i = _s13_to_s32(val & 0x00001FFF);
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iqcal_image_q = _s13_to_s32((val & 0x03FFE000) >> 13);
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sqsum = iqcal_image_i*iqcal_image_i + iqcal_image_q*iqcal_image_q;
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mag_1 = (s32) _sqrt(sqsum);
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PHY_DEBUG(("[CAL] mag_1=%d (iqcal_image_i=%d, iqcal_image_q=%d)\n",
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mag_1, iqcal_image_i, iqcal_image_q));
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/* e. Calculate the correct DC offset cancellation value for I */
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if (mag_0 != mag_1)
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fix_cancel_dc_i = (mag_0*10000) / (mag_0*10000 - mag_1*10000);
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else {
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if (mag_0 == mag_1)
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PHY_DEBUG(("[CAL] ***** mag_0 = mag_1 !!\n"));
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fix_cancel_dc_i = 0;
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}
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PHY_DEBUG(("[CAL] ** fix_cancel_dc_i = %d (0x%04X)\n",
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fix_cancel_dc_i,
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_s32_to_s5(fix_cancel_dc_i)));
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if ((abs(mag_1-mag_0)*6) > mag_0)
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break;
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}
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if (loop >= 19)
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fix_cancel_dc_i = 0;
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reg_dc_cancel &= ~(0x03FF);
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reg_dc_cancel |= (_s32_to_s5(fix_cancel_dc_i) << CANCEL_DC_I_SHIFT);
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hw_set_dxx_reg(phw_data, 0x5C, reg_dc_cancel);
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PHY_DEBUG(("[CAL] DC_CANCEL (write) = 0x%08X\n", reg_dc_cancel));
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/* g. */
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reg_mode_ctrl &= ~MASK_CALIB_START;
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hw_set_dxx_reg(phw_data, REG_MODE_CTRL, reg_mode_ctrl);
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PHY_DEBUG(("[CAL] MODE_CTRL (write) = 0x%08X\n", reg_mode_ctrl));
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}
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/*****************************************************/
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void _txqdac_dc_offset_cacellation_winbond(struct hw_data *phw_data)
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{
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u32 reg_agc_ctrl3;
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u32 reg_mode_ctrl;
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u32 reg_dc_cancel;
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s32 iqcal_image_i;
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s32 iqcal_image_q;
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u32 sqsum;
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s32 mag_0;
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s32 mag_1;
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s32 fix_cancel_dc_q = 0;
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u32 val;
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int loop;
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PHY_DEBUG(("[CAL] -> [3]_txqdac_dc_offset_cacellation()\n"));
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/*0x01 0xEE3FC2 ; 3B8FF ; Calibration (6a). enable TX IQ calibration loop circuits */
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phy_set_rf_data(phw_data, 1, (1<<24)|0xEE3FC2);
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/* 0x0B 0x1905D6 ; 06417 ; Calibration (6b). enable TX I/Q cal loop squaring circuit */
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phy_set_rf_data(phw_data, 11, (11<<24)|0x1901D6);
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/* 0x05 0x24C60A ; 09318 ; Calibration (6c). setting TX-VGA gain: TXGCH=2 & GPK=110 --> to be optimized */
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phy_set_rf_data(phw_data, 5, (5<<24)|0x24C48A);
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/* 0x06 0x06880C ; 01A20 ; Calibration (6d). RXGCH=00; RXGCL=100 000 (RXVGA=32) --> to be optimized */
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phy_set_rf_data(phw_data, 6, (6<<24)|0x06890C);
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/* 0x00 0xFDF1C0 ; 3F7C7 ; Calibration (6e). turn on IQ imbalance/Test mode */
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phy_set_rf_data(phw_data, 0, (0<<24)|0xFDF1C0);
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hw_set_dxx_reg(phw_data, 0x58, 0x30303030); /* IQ_Alpha Changed */
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/* a. Disable AGC */
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hw_get_dxx_reg(phw_data, REG_AGC_CTRL3, ®_agc_ctrl3);
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reg_agc_ctrl3 &= ~BIT(2);
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reg_agc_ctrl3 |= (MASK_LNA_FIX_GAIN|MASK_AGC_FIX);
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hw_set_dxx_reg(phw_data, REG_AGC_CTRL3, reg_agc_ctrl3);
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hw_get_dxx_reg(phw_data, REG_AGC_CTRL5, &val);
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val |= MASK_AGC_FIX_GAIN;
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hw_set_dxx_reg(phw_data, REG_AGC_CTRL5, val);
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/* a. set iqcal_mode[1:0] to 0x3 and set iqcal_tone[3:2] to 0 */
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hw_get_dxx_reg(phw_data, REG_MODE_CTRL, ®_mode_ctrl);
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PHY_DEBUG(("[CAL] MODE_CTRL (read) = 0x%08X\n", reg_mode_ctrl));
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/* reg_mode_ctrl &= ~(MASK_IQCAL_TONE_SEL|MASK_IQCAL_MODE); */
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reg_mode_ctrl &= ~(MASK_IQCAL_MODE);
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reg_mode_ctrl |= (MASK_CALIB_START|3);
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hw_set_dxx_reg(phw_data, REG_MODE_CTRL, reg_mode_ctrl);
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PHY_DEBUG(("[CAL] MODE_CTRL (write) = 0x%08X\n", reg_mode_ctrl));
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hw_get_dxx_reg(phw_data, 0x5C, ®_dc_cancel);
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PHY_DEBUG(("[CAL] DC_CANCEL (read) = 0x%08X\n", reg_dc_cancel));
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for (loop = 0; loop < LOOP_TIMES; loop++) {
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PHY_DEBUG(("[CAL] [%d.] ==================================\n", loop));
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/* b. reset cancel_dc_q[4:0] in register DC_Cancel */
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reg_dc_cancel &= ~(0x001F);
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PHY_DEBUG(("[CAL] DC_CANCEL (write) = 0x%08X\n", reg_dc_cancel));
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hw_set_dxx_reg(phw_data, 0x5C, reg_dc_cancel);
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hw_get_dxx_reg(phw_data, REG_CALIB_READ2, &val);
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PHY_DEBUG(("[CAL] CALIB_READ2 = 0x%08X\n", val));
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iqcal_image_i = _s13_to_s32(val & 0x00001FFF);
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iqcal_image_q = _s13_to_s32((val & 0x03FFE000) >> 13);
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sqsum = iqcal_image_i*iqcal_image_i + iqcal_image_q*iqcal_image_q;
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mag_0 = _sqrt(sqsum);
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PHY_DEBUG(("[CAL] mag_0=%d (iqcal_image_i=%d, iqcal_image_q=%d)\n",
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mag_0, iqcal_image_i, iqcal_image_q));
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/* c. */
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reg_dc_cancel |= (1 << CANCEL_DC_Q_SHIFT);
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PHY_DEBUG(("[CAL] DC_CANCEL (write) = 0x%08X\n", reg_dc_cancel));
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hw_set_dxx_reg(phw_data, 0x5C, reg_dc_cancel);
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hw_get_dxx_reg(phw_data, REG_CALIB_READ2, &val);
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PHY_DEBUG(("[CAL] CALIB_READ2 = 0x%08X\n", val));
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iqcal_image_i = _s13_to_s32(val & 0x00001FFF);
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iqcal_image_q = _s13_to_s32((val & 0x03FFE000) >> 13);
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sqsum = iqcal_image_i*iqcal_image_i + iqcal_image_q*iqcal_image_q;
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mag_1 = _sqrt(sqsum);
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PHY_DEBUG(("[CAL] mag_1=%d (iqcal_image_i=%d, iqcal_image_q=%d)\n",
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mag_1, iqcal_image_i, iqcal_image_q));
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/* d. Calculate the correct DC offset cancellation value for I */
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if (mag_0 != mag_1)
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fix_cancel_dc_q = (mag_0*10000) / (mag_0*10000 - mag_1*10000);
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else {
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if (mag_0 == mag_1)
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PHY_DEBUG(("[CAL] ***** mag_0 = mag_1 !!\n"));
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fix_cancel_dc_q = 0;
|
||||
}
|
||||
|
||||
PHY_DEBUG(("[CAL] ** fix_cancel_dc_q = %d (0x%04X)\n",
|
||||
fix_cancel_dc_q, _s32_to_s5(fix_cancel_dc_q)));
|
||||
|
||||
if ((abs(mag_1-mag_0)*6) > mag_0)
|
||||
break;
|
||||
}
|
||||
|
||||
if (loop >= 19)
|
||||
fix_cancel_dc_q = 0;
|
||||
|
||||
reg_dc_cancel &= ~(0x001F);
|
||||
reg_dc_cancel |= (_s32_to_s5(fix_cancel_dc_q) << CANCEL_DC_Q_SHIFT);
|
||||
hw_set_dxx_reg(phw_data, 0x5C, reg_dc_cancel);
|
||||
PHY_DEBUG(("[CAL] DC_CANCEL (write) = 0x%08X\n", reg_dc_cancel));
|
||||
|
||||
|
||||
/* f. */
|
||||
reg_mode_ctrl &= ~MASK_CALIB_START;
|
||||
hw_set_dxx_reg(phw_data, REG_MODE_CTRL, reg_mode_ctrl);
|
||||
PHY_DEBUG(("[CAL] MODE_CTRL (write) = 0x%08X\n", reg_mode_ctrl));
|
||||
}
|
||||
|
||||
/* 20060612.1.a 20060718.1 Modify */
|
||||
u8 _tx_iq_calibration_loop_winbond(struct hw_data *phw_data,
|
||||
static u8 _tx_iq_calibration_loop_winbond(struct hw_data *phw_data,
|
||||
s32 a_2_threshold,
|
||||
s32 b_2_threshold)
|
||||
{
|
||||
|
|
@ -962,7 +679,7 @@ u8 _tx_iq_calibration_loop_winbond(struct hw_data *phw_data,
|
|||
return 1;
|
||||
}
|
||||
|
||||
void _tx_iq_calibration_winbond(struct hw_data *phw_data)
|
||||
static void _tx_iq_calibration_winbond(struct hw_data *phw_data)
|
||||
{
|
||||
u32 reg_agc_ctrl3;
|
||||
#ifdef _DEBUG
|
||||
|
|
@ -1108,7 +825,7 @@ void _tx_iq_calibration_winbond(struct hw_data *phw_data)
|
|||
}
|
||||
|
||||
/*****************************************************/
|
||||
u8 _rx_iq_calibration_loop_winbond(struct hw_data *phw_data, u16 factor, u32 frequency)
|
||||
static u8 _rx_iq_calibration_loop_winbond(struct hw_data *phw_data, u16 factor, u32 frequency)
|
||||
{
|
||||
u32 reg_mode_ctrl;
|
||||
s32 iqcal_tone_i;
|
||||
|
|
@ -1382,7 +1099,7 @@ u8 _rx_iq_calibration_loop_winbond(struct hw_data *phw_data, u16 factor, u32 fre
|
|||
/*************************************************/
|
||||
|
||||
/***************************************************************/
|
||||
void _rx_iq_calibration_winbond(struct hw_data *phw_data, u32 frequency)
|
||||
static void _rx_iq_calibration_winbond(struct hw_data *phw_data, u32 frequency)
|
||||
{
|
||||
/* figo 20050523 marked this flag for can't compile for release */
|
||||
#ifdef _DEBUG
|
||||
|
|
|
|||
Loading…
Reference in a new issue