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Merge "msm: kgsl: Update the IFPC power up reglist"

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qctecmdr 2021-11-05 08:45:46 -07:00 committed by Gerrit - the friendly Code Review server
commit 05b4289870
1 changed files with 30 additions and 5 deletions
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35
drivers/gpu/msm/adreno_a6xx.c
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@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0-only // SPDX-License-Identifier: GPL-2.0-only
/* /*
* Copyright (c) 2017-2020, The Linux Foundation. All rights reserved. * Copyright (c) 2017-2021, The Linux Foundation. All rights reserved.
*/ */
#include <linux/firmware.h> #include <linux/firmware.h>
@ -89,9 +89,27 @@ static u32 a6xx_ifpc_pwrup_reglist[] = {
}; };
/* Applicable to a620 and a650 */ /* Applicable to a620 and a650 */
static u32 a650_ifpc_pwrup_reglist[] = {
A6XX_CP_PROTECT_REG+32,
A6XX_CP_PROTECT_REG+33,
A6XX_CP_PROTECT_REG+34,
A6XX_CP_PROTECT_REG+35,
A6XX_CP_PROTECT_REG+36,
A6XX_CP_PROTECT_REG+37,
A6XX_CP_PROTECT_REG+38,
A6XX_CP_PROTECT_REG+39,
A6XX_CP_PROTECT_REG+40,
A6XX_CP_PROTECT_REG+41,
A6XX_CP_PROTECT_REG+42,
A6XX_CP_PROTECT_REG+43,
A6XX_CP_PROTECT_REG+44,
A6XX_CP_PROTECT_REG+45,
A6XX_CP_PROTECT_REG+46,
A6XX_CP_PROTECT_REG+47,
};
static u32 a650_pwrup_reglist[] = { static u32 a650_pwrup_reglist[] = {
A6XX_RBBM_GBIF_CLIENT_QOS_CNTL, A6XX_RBBM_GBIF_CLIENT_QOS_CNTL,
A6XX_CP_PROTECT_REG + 47, /* Programmed for infinite span */
A6XX_TPL1_BICUBIC_WEIGHTS_TABLE_0, A6XX_TPL1_BICUBIC_WEIGHTS_TABLE_0,
A6XX_TPL1_BICUBIC_WEIGHTS_TABLE_1, A6XX_TPL1_BICUBIC_WEIGHTS_TABLE_1,
A6XX_TPL1_BICUBIC_WEIGHTS_TABLE_2, A6XX_TPL1_BICUBIC_WEIGHTS_TABLE_2,
@ -351,14 +369,21 @@ struct a6xx_reglist_list {
static void a6xx_patch_pwrup_reglist(struct adreno_device *adreno_dev) static void a6xx_patch_pwrup_reglist(struct adreno_device *adreno_dev)
{ {
struct a6xx_reglist_list reglist[3]; struct a6xx_reglist_list reglist[4];
void *ptr = adreno_dev->pwrup_reglist.hostptr; void *ptr = adreno_dev->pwrup_reglist.hostptr;
struct cpu_gpu_lock *lock = ptr; struct cpu_gpu_lock *lock = ptr;
int items = 0, i, j; int items = 0, i, j;
u32 *dest = ptr + sizeof(*lock); u32 *dest = ptr + sizeof(*lock);
u16 list_offset = 0;
/* Static IFPC-only registers */ /* Static IFPC-only registers */
reglist[items++] = REGLIST(a6xx_ifpc_pwrup_reglist); reglist[items] = REGLIST(a6xx_ifpc_pwrup_reglist);
list_offset += reglist[items++].count * 2;
if (adreno_is_a650_family(adreno_dev)) {
reglist[items] = REGLIST(a650_ifpc_pwrup_reglist);
list_offset += reglist[items++].count * 2;
}
/* Static IFPC + preemption registers */ /* Static IFPC + preemption registers */
reglist[items++] = REGLIST(a6xx_pwrup_reglist); reglist[items++] = REGLIST(a6xx_pwrup_reglist);
@ -401,7 +426,7 @@ static void a6xx_patch_pwrup_reglist(struct adreno_device *adreno_dev)
* all the lists and list_offset should be specified as the size in * all the lists and list_offset should be specified as the size in
* dwords of the first entry in the list. * dwords of the first entry in the list.
*/ */
lock->list_offset = reglist[0].count * 2; lock->list_offset = list_offset;
} }
/* /*