[POWERPC] Generalize tsi108 PCI setup

Generalize tsi108_setup_pci to take the config space physical address and
primary bus designator as a parameter.

Signed-off-by: Josh Boyer <jwboyer@linux.vnet.ibm.com>
Acked-by: Olof Johansson <olof@lixom.net>
Signed-off-by: Paul Mackerras <paulus@samba.org>
This commit is contained in:
Josh Boyer 2007-05-08 07:27:15 +10:00 committed by Paul Mackerras
parent c1b78d05b3
commit 05ad6a9159
4 changed files with 10 additions and 8 deletions

View file

@ -52,6 +52,8 @@
#define DBG(fmt...) do { } while(0)
#endif
#define MPC7448HPC2_PCI_CFG_PHYS 0xfb000000
#ifndef CONFIG_PCI
isa_io_base = MPC7448_HPC2_ISA_IO_BASE;
isa_mem_base = MPC7448_HPC2_ISA_MEM_BASE;
@ -79,7 +81,7 @@ static void __init mpc7448_hpc2_setup_arch(void)
/* setup PCI host bridge */
#ifdef CONFIG_PCI
for (np = NULL; (np = of_find_node_by_type(np, "pci")) != NULL;)
tsi108_setup_pci(np);
tsi108_setup_pci(np, MPC7448HPC2_PCI_CFG_PHYS, 0);
ppc_md.pci_exclude_device = mpc7448_hpc2_exclude_device;
if (ppc_md.progress)

View file

@ -50,6 +50,7 @@
((((bus)<<16) | ((devfunc)<<8) | (offset & 0xfc)) + tsi108_pci_cfg_base)
u32 tsi108_pci_cfg_base;
static u32 tsi108_pci_cfg_phys;
u32 tsi108_csr_vir_base;
static struct device_node *pci_irq_node;
static struct irq_host *pci_irq_host;
@ -186,7 +187,7 @@ tsi108_direct_read_config(struct pci_bus *bus, unsigned int devfn, int offset,
void tsi108_clear_pci_cfg_error(void)
{
tsi108_clear_pci_error(TSI108_PCI_CFG_BASE_PHYS);
tsi108_clear_pci_error(tsi108_pci_cfg_phys);
}
static struct pci_ops tsi108_direct_pci_ops = {
@ -194,17 +195,17 @@ static struct pci_ops tsi108_direct_pci_ops = {
tsi108_direct_write_config
};
int __init tsi108_setup_pci(struct device_node *dev)
int __init tsi108_setup_pci(struct device_node *dev, u32 cfg_phys, int primary)
{
int len;
struct pci_controller *hose;
struct resource rsrc;
const int *bus_range;
int primary = 0, has_address = 0;
int has_address = 0;
/* PCI Config mapping */
tsi108_pci_cfg_base = (u32)ioremap(TSI108_PCI_CFG_BASE_PHYS,
TSI108_PCI_CFG_SIZE);
tsi108_pci_cfg_base = (u32)ioremap(cfg_phys, TSI108_PCI_CFG_SIZE);
tsi108_pci_cfg_phys = cfg_phys;
DBG("TSI_PCI: %s tsi108_pci_cfg_base=0x%x\n", __FUNCTION__,
tsi108_pci_cfg_base);

View file

@ -68,7 +68,6 @@
#define TSI108_PB_ERRCS_ES (1 << 1)
#define TSI108_PB_ISR_PBS_RD_ERR (1 << 8)
#define TSI108_PCI_CFG_BASE_PHYS (0xfb000000)
#define TSI108_PCI_CFG_SIZE (0x01000000)
/*

View file

@ -37,7 +37,7 @@
#define TSI108_PCI_PFAB_PFM3 (TSI108_PCI_OFFSET + 0x220)
#define TSI108_PCI_PFAB_PFM4 (TSI108_PCI_OFFSET + 0x230)
extern int tsi108_setup_pci(struct device_node *dev);
extern int tsi108_setup_pci(struct device_node *dev, u32 cfg_phys, int primary);
extern void tsi108_pci_int_init(struct device_node *node);
extern void tsi108_irq_cascade(unsigned int irq, struct irq_desc *desc);
extern void tsi108_clear_pci_cfg_error(void);