ALSA: pxa27x: rename pxa27x_assert_ac97reset()
This patch does nothing functionally, it just gives the function a new name and modifies the prototype slightly in order to clarify what the function is doing (which is not necessarily asserting the reset). Some commentary also added. Tested on a palm treo 680 machine. Signed-off-by: Mike Dunn <mikedunn@newsguy.com> Acked-by: Igor Grinberg <grinberg@compulab.co.il> Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
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2 changed files with 18 additions and 10 deletions
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@ -53,17 +53,25 @@ static unsigned long ac97_reset_config[] = {
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GPIO95_AC97_nRESET,
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};
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void pxa27x_assert_ac97reset(int reset_gpio, int on)
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void pxa27x_configure_ac97reset(int reset_gpio, bool to_gpio)
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{
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/*
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* This helper function is used to work around a bug in the pxa27x's
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* ac97 controller during a warm reset. The configuration of the
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* reset_gpio is changed as follows:
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* to_gpio == true: configured to generic output gpio and driven high
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* to_gpio == false: configured to ac97 controller alt fn AC97_nRESET
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*/
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if (reset_gpio == 113)
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pxa2xx_mfp_config(on ? &ac97_reset_config[0] :
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&ac97_reset_config[1], 1);
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pxa2xx_mfp_config(to_gpio ? &ac97_reset_config[0] :
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&ac97_reset_config[1], 1);
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if (reset_gpio == 95)
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pxa2xx_mfp_config(on ? &ac97_reset_config[2] :
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&ac97_reset_config[3], 1);
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pxa2xx_mfp_config(to_gpio ? &ac97_reset_config[2] :
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&ac97_reset_config[3], 1);
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}
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EXPORT_SYMBOL_GPL(pxa27x_assert_ac97reset);
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EXPORT_SYMBOL_GPL(pxa27x_configure_ac97reset);
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/* Crystal clock: 13MHz */
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#define BASE_CLK 13000000
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@ -34,7 +34,7 @@ static struct clk *ac97_clk;
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static struct clk *ac97conf_clk;
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static int reset_gpio;
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extern void pxa27x_assert_ac97reset(int reset_gpio, int on);
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extern void pxa27x_configure_ac97reset(int reset_gpio, bool to_gpio);
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/*
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* Beware PXA27x bugs:
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@ -140,10 +140,10 @@ static inline void pxa_ac97_warm_pxa27x(void)
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gsr_bits = 0;
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/* warm reset broken on Bulverde, so manually keep AC97 reset high */
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pxa27x_assert_ac97reset(reset_gpio, 1);
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pxa27x_configure_ac97reset(reset_gpio, true);
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udelay(10);
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GCR |= GCR_WARM_RST;
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pxa27x_assert_ac97reset(reset_gpio, 0);
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pxa27x_configure_ac97reset(reset_gpio, false);
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udelay(500);
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}
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@ -358,7 +358,7 @@ int pxa2xx_ac97_hw_probe(struct platform_device *dev)
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__func__, ret);
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goto err_conf;
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}
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pxa27x_assert_ac97reset(reset_gpio, 0);
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pxa27x_configure_ac97reset(reset_gpio, false);
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ac97conf_clk = clk_get(&dev->dev, "AC97CONFCLK");
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if (IS_ERR(ac97conf_clk)) {
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