clockevents/driversi/mps2: add MPS2 Timer driver
MPS2 platform has simple 32 bits general purpose countdown timers. The driver uses the first detected timer as a clocksource and the rest of the timers as a clockevent Acked-by: Daniel Lezcano <daniel.lezcano@linaro.org> Signed-off-by: Vladimir Murzin <vladimir.murzin@arm.com> Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
This commit is contained in:
Vladimir Murzin
Daniel Lezcano
parent
96669fa43c
commit
0302637f18
3 changed files with 282 additions and 0 deletions
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@ -186,6 +186,12 @@ config CLKSRC_STM32
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depends on OF && ARM && (ARCH_STM32 || COMPILE_TEST)
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select CLKSRC_MMIO
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config CLKSRC_MPS2
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bool "Clocksource for MPS2 SoCs" if COMPILE_TEST
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depends on GENERIC_SCHED_CLOCK
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select CLKSRC_MMIO
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select CLKSRC_OF
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config ARM_ARCH_TIMER
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bool
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select CLKSRC_OF if OF
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@ -39,6 +39,7 @@ obj-$(CONFIG_CLKSRC_EFM32) += time-efm32.o
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obj-$(CONFIG_CLKSRC_STM32) += timer-stm32.o
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obj-$(CONFIG_CLKSRC_EXYNOS_MCT) += exynos_mct.o
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obj-$(CONFIG_CLKSRC_LPC32XX) += time-lpc32xx.o
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obj-$(CONFIG_CLKSRC_MPS2) += mps2-timer.o
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obj-$(CONFIG_CLKSRC_SAMSUNG_PWM) += samsung_pwm_timer.o
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obj-$(CONFIG_FSL_FTM_TIMER) += fsl_ftm_timer.o
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obj-$(CONFIG_VF_PIT_TIMER) += vf_pit_timer.o
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275
drivers/clocksource/mps2-timer.c
Normal file
275
drivers/clocksource/mps2-timer.c
Normal file
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@ -0,0 +1,275 @@
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/*
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* Copyright (C) 2015 ARM Limited
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*
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* Author: Vladimir Murzin <vladimir.murzin@arm.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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*/
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#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
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#include <linux/clk.h>
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#include <linux/clockchips.h>
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#include <linux/clocksource.h>
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#include <linux/err.h>
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#include <linux/interrupt.h>
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#include <linux/io.h>
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#include <linux/irq.h>
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#include <linux/of_address.h>
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#include <linux/of.h>
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#include <linux/of_irq.h>
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#include <linux/sched_clock.h>
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#include <linux/slab.h>
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#define TIMER_CTRL 0x0
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#define TIMER_CTRL_ENABLE BIT(0)
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#define TIMER_CTRL_IE BIT(3)
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#define TIMER_VALUE 0x4
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#define TIMER_RELOAD 0x8
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#define TIMER_INT 0xc
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struct clockevent_mps2 {
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void __iomem *reg;
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u32 clock_count_per_tick;
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struct clock_event_device clkevt;
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};
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static void __iomem *sched_clock_base;
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static u64 notrace mps2_sched_read(void)
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{
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return ~readl_relaxed(sched_clock_base + TIMER_VALUE);
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}
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static inline struct clockevent_mps2 *to_mps2_clkevt(struct clock_event_device *c)
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{
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return container_of(c, struct clockevent_mps2, clkevt);
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}
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static void clockevent_mps2_writel(u32 val, struct clock_event_device *c, u32 offset)
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{
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writel_relaxed(val, to_mps2_clkevt(c)->reg + offset);
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}
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static int mps2_timer_shutdown(struct clock_event_device *ce)
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{
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clockevent_mps2_writel(0, ce, TIMER_RELOAD);
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clockevent_mps2_writel(0, ce, TIMER_CTRL);
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return 0;
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}
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static int mps2_timer_set_next_event(unsigned long next, struct clock_event_device *ce)
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{
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clockevent_mps2_writel(next, ce, TIMER_VALUE);
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clockevent_mps2_writel(TIMER_CTRL_IE | TIMER_CTRL_ENABLE, ce, TIMER_CTRL);
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return 0;
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}
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static int mps2_timer_set_periodic(struct clock_event_device *ce)
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{
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u32 clock_count_per_tick = to_mps2_clkevt(ce)->clock_count_per_tick;
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clockevent_mps2_writel(clock_count_per_tick, ce, TIMER_RELOAD);
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clockevent_mps2_writel(clock_count_per_tick, ce, TIMER_VALUE);
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clockevent_mps2_writel(TIMER_CTRL_IE | TIMER_CTRL_ENABLE, ce, TIMER_CTRL);
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return 0;
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}
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static irqreturn_t mps2_timer_interrupt(int irq, void *dev_id)
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{
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struct clockevent_mps2 *ce = dev_id;
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u32 status = readl_relaxed(ce->reg + TIMER_INT);
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if (!status) {
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pr_warn("spurious interrupt\n");
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return IRQ_NONE;
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}
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writel_relaxed(1, ce->reg + TIMER_INT);
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ce->clkevt.event_handler(&ce->clkevt);
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return IRQ_HANDLED;
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}
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static int __init mps2_clockevent_init(struct device_node *np)
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{
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void __iomem *base;
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struct clk *clk = NULL;
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struct clockevent_mps2 *ce;
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u32 rate;
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int irq, ret;
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const char *name = "mps2-clkevt";
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ret = of_property_read_u32(np, "clock-frequency", &rate);
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if (ret) {
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clk = of_clk_get(np, 0);
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if (IS_ERR(clk)) {
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ret = PTR_ERR(clk);
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pr_err("failed to get clock for clockevent: %d\n", ret);
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goto out;
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}
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ret = clk_prepare_enable(clk);
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if (ret) {
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pr_err("failed to enable clock for clockevent: %d\n", ret);
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goto out_clk_put;
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}
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rate = clk_get_rate(clk);
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}
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base = of_iomap(np, 0);
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if (!base) {
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ret = -EADDRNOTAVAIL;
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pr_err("failed to map register for clockevent: %d\n", ret);
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goto out_clk_disable;
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}
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irq = irq_of_parse_and_map(np, 0);
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if (!irq) {
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ret = -ENOENT;
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pr_err("failed to get irq for clockevent: %d\n", ret);
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goto out_iounmap;
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}
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ce = kzalloc(sizeof(*ce), GFP_KERNEL);
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if (!ce) {
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ret = -ENOMEM;
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goto out_iounmap;
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}
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ce->reg = base;
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ce->clock_count_per_tick = DIV_ROUND_CLOSEST(rate, HZ);
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ce->clkevt.irq = irq;
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ce->clkevt.name = name;
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ce->clkevt.rating = 200;
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ce->clkevt.features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT;
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ce->clkevt.cpumask = cpu_possible_mask;
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ce->clkevt.set_state_shutdown = mps2_timer_shutdown,
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ce->clkevt.set_state_periodic = mps2_timer_set_periodic,
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ce->clkevt.set_state_oneshot = mps2_timer_shutdown,
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ce->clkevt.set_next_event = mps2_timer_set_next_event;
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/* Ensure timer is disabled */
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writel_relaxed(0, base + TIMER_CTRL);
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ret = request_irq(irq, mps2_timer_interrupt, IRQF_TIMER, name, ce);
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if (ret) {
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pr_err("failed to request irq for clockevent: %d\n", ret);
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goto out_kfree;
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}
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clockevents_config_and_register(&ce->clkevt, rate, 0xf, 0xffffffff);
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return 0;
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out_kfree:
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kfree(ce);
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out_iounmap:
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iounmap(base);
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out_clk_disable:
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/* clk_{disable, unprepare, put}() can handle NULL as a parameter */
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clk_disable_unprepare(clk);
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out_clk_put:
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clk_put(clk);
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out:
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return ret;
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}
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static int __init mps2_clocksource_init(struct device_node *np)
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{
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void __iomem *base;
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struct clk *clk = NULL;
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u32 rate;
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int ret;
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const char *name = "mps2-clksrc";
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ret = of_property_read_u32(np, "clock-frequency", &rate);
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if (ret) {
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clk = of_clk_get(np, 0);
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if (IS_ERR(clk)) {
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ret = PTR_ERR(clk);
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pr_err("failed to get clock for clocksource: %d\n", ret);
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goto out;
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}
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ret = clk_prepare_enable(clk);
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if (ret) {
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pr_err("failed to enable clock for clocksource: %d\n", ret);
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goto out_clk_put;
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}
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rate = clk_get_rate(clk);
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}
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base = of_iomap(np, 0);
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if (!base) {
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ret = -EADDRNOTAVAIL;
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pr_err("failed to map register for clocksource: %d\n", ret);
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goto out_clk_disable;
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}
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/* Ensure timer is disabled */
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writel_relaxed(0, base + TIMER_CTRL);
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/* ... and set it up as free-running clocksource */
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writel_relaxed(0xffffffff, base + TIMER_VALUE);
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writel_relaxed(0xffffffff, base + TIMER_RELOAD);
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writel_relaxed(TIMER_CTRL_ENABLE, base + TIMER_CTRL);
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ret = clocksource_mmio_init(base + TIMER_VALUE, name,
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rate, 200, 32,
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clocksource_mmio_readl_down);
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if (ret) {
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pr_err("failed to init clocksource: %d\n", ret);
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goto out_iounmap;
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}
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sched_clock_base = base;
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sched_clock_register(mps2_sched_read, 32, rate);
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return 0;
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out_iounmap:
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iounmap(base);
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out_clk_disable:
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/* clk_{disable, unprepare, put}() can handle NULL as a parameter */
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clk_disable_unprepare(clk);
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out_clk_put:
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clk_put(clk);
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out:
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return ret;
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}
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static void __init mps2_timer_init(struct device_node *np)
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{
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static int has_clocksource, has_clockevent;
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int ret;
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if (!has_clocksource) {
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ret = mps2_clocksource_init(np);
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if (!ret) {
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has_clocksource = 1;
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return;
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}
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}
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if (!has_clockevent) {
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ret = mps2_clockevent_init(np);
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if (!ret) {
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has_clockevent = 1;
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return;
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}
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}
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}
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CLOCKSOURCE_OF_DECLARE(mps2_timer, "arm,mps2-timer", mps2_timer_init);
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