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sfc: Move descriptor cache base addresses to struct efx_nic_type

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Signed-off-by: Ben Hutchings <bhutchings@solarflare.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
Ben Hutchings 2009-11-28 05:36:12 +00:00 • committed by David S. Miller
parent daeda6309e
commit 0228f5cdb0
2 changed files with 12 additions and 4 deletions
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12
drivers/net/sfc/falcon.c
View file

@ -45,11 +45,9 @@
*/ */
#define TX_DC_ENTRIES 16 #define TX_DC_ENTRIES 16
#define TX_DC_ENTRIES_ORDER 1 #define TX_DC_ENTRIES_ORDER 1
#define TX_DC_BASE 0x130000
#define RX_DC_ENTRIES 64 #define RX_DC_ENTRIES 64
#define RX_DC_ENTRIES_ORDER 3 #define RX_DC_ENTRIES_ORDER 3
#define RX_DC_BASE 0x100000
static const unsigned int static const unsigned int
/* "Large" EEPROM device: Atmel AT25640 or similar /* "Large" EEPROM device: Atmel AT25640 or similar
@ -3043,9 +3041,11 @@ int falcon_init_nic(struct efx_nic *efx)
return rc; return rc;
/* Set positions of descriptor caches in SRAM. */ /* Set positions of descriptor caches in SRAM. */
EFX_POPULATE_OWORD_1(temp, FRF_AZ_SRM_TX_DC_BASE_ADR, TX_DC_BASE / 8); EFX_POPULATE_OWORD_1(temp, FRF_AZ_SRM_TX_DC_BASE_ADR,
efx->type->tx_dc_base / 8);
efx_writeo(efx, &temp, FR_AZ_SRM_TX_DC_CFG); efx_writeo(efx, &temp, FR_AZ_SRM_TX_DC_CFG);
EFX_POPULATE_OWORD_1(temp, FRF_AZ_SRM_RX_DC_BASE_ADR, RX_DC_BASE / 8); EFX_POPULATE_OWORD_1(temp, FRF_AZ_SRM_RX_DC_BASE_ADR,
efx->type->rx_dc_base / 8);
efx_writeo(efx, &temp, FR_AZ_SRM_RX_DC_CFG); efx_writeo(efx, &temp, FR_AZ_SRM_RX_DC_CFG);
/* Set TX descriptor cache size. */ /* Set TX descriptor cache size. */
@ -3248,6 +3248,8 @@ struct efx_nic_type falcon_a1_nic_type = {
.rx_buffer_padding = 0x24, .rx_buffer_padding = 0x24,
.max_interrupt_mode = EFX_INT_MODE_MSI, .max_interrupt_mode = EFX_INT_MODE_MSI,
.phys_addr_channels = 4, .phys_addr_channels = 4,
.tx_dc_base = 0x130000,
.rx_dc_base = 0x100000,
}; };
struct efx_nic_type falcon_b0_nic_type = { struct efx_nic_type falcon_b0_nic_type = {
@ -3271,5 +3273,7 @@ struct efx_nic_type falcon_b0_nic_type = {
.phys_addr_channels = 32, /* Hardware limit is 64, but the legacy .phys_addr_channels = 32, /* Hardware limit is 64, but the legacy
* interrupt handler only supports 32 * interrupt handler only supports 32
* channels */ * channels */
.tx_dc_base = 0x130000,
.rx_dc_base = 0x100000,
}; };

4
drivers/net/sfc/net_driver.h
View file

@ -857,6 +857,8 @@ static inline const char *efx_dev_name(struct efx_nic *efx)
* from &enum efx_init_mode. * from &enum efx_init_mode.
* @phys_addr_channels: Number of channels with physically addressed * @phys_addr_channels: Number of channels with physically addressed
* descriptors * descriptors
* @tx_dc_base: Base address in SRAM of TX queue descriptor caches
* @rx_dc_base: Base address in SRAM of RX queue descriptor caches
*/ */
struct efx_nic_type { struct efx_nic_type {
struct efx_mac_operations *default_mac_ops; struct efx_mac_operations *default_mac_ops;
@ -872,6 +874,8 @@ struct efx_nic_type {
unsigned int rx_buffer_padding; unsigned int rx_buffer_padding;
unsigned int max_interrupt_mode; unsigned int max_interrupt_mode;
unsigned int phys_addr_channels; unsigned int phys_addr_channels;
unsigned int tx_dc_base;
unsigned int rx_dc_base;
}; };
/************************************************************************** /**************************************************************************