MIPS: Reorganize Cavium OCTEON PCI support.
Move the cavium PCI files to the arch/mips/pci directory. Also cleanup comment formatting and code layout. Code from pci-common.c, was moved into other files. Signed-off-by: David Daney <ddaney@caviumnetworks.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
This commit is contained in:
David Daney
Ralf Baechle
parent
ada8e9514b
commit
01a6221a6a
8 changed files with 197 additions and 221 deletions
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@ -14,9 +14,5 @@ obj-y += dma-octeon.o flash_setup.o
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obj-y += octeon-memcpy.o
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obj-$(CONFIG_SMP) += smp.o
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obj-$(CONFIG_PCI) += pci-common.o
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obj-$(CONFIG_PCI) += pci.o
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obj-$(CONFIG_PCI) += pcie.o
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obj-$(CONFIG_PCI_MSI) += msi.o
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EXTRA_CFLAGS += -Werror
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@ -29,7 +29,7 @@
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#include <dma-coherence.h>
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#ifdef CONFIG_PCI
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#include "pci-common.h"
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#include <asm/octeon/pci-octeon.h>
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#endif
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#define BAR2_PCI_ADDRESS 0x8000000000ul
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@ -1,137 +0,0 @@
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/*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*
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* Copyright (C) 2005-2007 Cavium Networks
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*/
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#include <linux/kernel.h>
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#include <linux/init.h>
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#include <linux/pci.h>
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#include <linux/interrupt.h>
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#include <linux/time.h>
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#include <linux/delay.h>
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#include "pci-common.h"
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typeof(pcibios_map_irq) *octeon_pcibios_map_irq;
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enum octeon_dma_bar_type octeon_dma_bar_type = OCTEON_DMA_BAR_TYPE_INVALID;
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/**
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* Map a PCI device to the appropriate interrupt line
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*
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* @param dev The Linux PCI device structure for the device to map
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* @param slot The slot number for this device on __BUS 0__. Linux
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* enumerates through all the bridges and figures out the
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* slot on Bus 0 where this device eventually hooks to.
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* @param pin The PCI interrupt pin read from the device, then swizzled
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* as it goes through each bridge.
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* @return Interrupt number for the device
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*/
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int __init pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
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{
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if (octeon_pcibios_map_irq)
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return octeon_pcibios_map_irq(dev, slot, pin);
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else
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panic("octeon_pcibios_map_irq doesn't point to a "
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"pcibios_map_irq() function");
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}
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/**
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* Called to perform platform specific PCI setup
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*
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* @param dev
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* @return
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*/
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int pcibios_plat_dev_init(struct pci_dev *dev)
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{
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uint16_t config;
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uint32_t dconfig;
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int pos;
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/*
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* Force the Cache line setting to 64 bytes. The standard
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* Linux bus scan doesn't seem to set it. Octeon really has
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* 128 byte lines, but Intel bridges get really upset if you
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* try and set values above 64 bytes. Value is specified in
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* 32bit words.
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*/
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pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, 64 / 4);
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/* Set latency timers for all devices */
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pci_write_config_byte(dev, PCI_LATENCY_TIMER, 48);
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/* Enable reporting System errors and parity errors on all devices */
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/* Enable parity checking and error reporting */
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pci_read_config_word(dev, PCI_COMMAND, &config);
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config |= PCI_COMMAND_PARITY | PCI_COMMAND_SERR;
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pci_write_config_word(dev, PCI_COMMAND, config);
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if (dev->subordinate) {
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/* Set latency timers on sub bridges */
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pci_write_config_byte(dev, PCI_SEC_LATENCY_TIMER, 48);
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/* More bridge error detection */
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pci_read_config_word(dev, PCI_BRIDGE_CONTROL, &config);
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config |= PCI_BRIDGE_CTL_PARITY | PCI_BRIDGE_CTL_SERR;
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pci_write_config_word(dev, PCI_BRIDGE_CONTROL, config);
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}
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/* Enable the PCIe normal error reporting */
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pos = pci_find_capability(dev, PCI_CAP_ID_EXP);
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if (pos) {
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/* Update Device Control */
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pci_read_config_word(dev, pos + PCI_EXP_DEVCTL, &config);
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/* Correctable Error Reporting */
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config |= PCI_EXP_DEVCTL_CERE;
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/* Non-Fatal Error Reporting */
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config |= PCI_EXP_DEVCTL_NFERE;
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/* Fatal Error Reporting */
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config |= PCI_EXP_DEVCTL_FERE;
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/* Unsupported Request */
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config |= PCI_EXP_DEVCTL_URRE;
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pci_write_config_word(dev, pos + PCI_EXP_DEVCTL, config);
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}
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/* Find the Advanced Error Reporting capability */
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pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ERR);
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if (pos) {
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/* Clear Uncorrectable Error Status */
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pci_read_config_dword(dev, pos + PCI_ERR_UNCOR_STATUS,
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&dconfig);
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pci_write_config_dword(dev, pos + PCI_ERR_UNCOR_STATUS,
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dconfig);
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/* Enable reporting of all uncorrectable errors */
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/* Uncorrectable Error Mask - turned on bits disable errors */
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pci_write_config_dword(dev, pos + PCI_ERR_UNCOR_MASK, 0);
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/*
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* Leave severity at HW default. This only controls if
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* errors are reported as uncorrectable or
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* correctable, not if the error is reported.
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*/
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/* PCI_ERR_UNCOR_SEVER - Uncorrectable Error Severity */
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/* Clear Correctable Error Status */
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pci_read_config_dword(dev, pos + PCI_ERR_COR_STATUS, &dconfig);
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pci_write_config_dword(dev, pos + PCI_ERR_COR_STATUS, dconfig);
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/* Enable reporting of all correctable errors */
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/* Correctable Error Mask - turned on bits disable errors */
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pci_write_config_dword(dev, pos + PCI_ERR_COR_MASK, 0);
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/* Advanced Error Capabilities */
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pci_read_config_dword(dev, pos + PCI_ERR_CAP, &dconfig);
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/* ECRC Generation Enable */
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if (config & PCI_ERR_CAP_ECRC_GENC)
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config |= PCI_ERR_CAP_ECRC_GENE;
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/* ECRC Check Enable */
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if (config & PCI_ERR_CAP_ECRC_CHKC)
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config |= PCI_ERR_CAP_ECRC_CHKE;
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pci_write_config_dword(dev, pos + PCI_ERR_CAP, dconfig);
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/* PCI_ERR_HEADER_LOG - Header Log Register (16 bytes) */
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/* Report all errors to the root complex */
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pci_write_config_dword(dev, pos + PCI_ERR_ROOT_COMMAND,
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PCI_ERR_ROOT_CMD_COR_EN |
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PCI_ERR_ROOT_CMD_NONFATAL_EN |
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PCI_ERR_ROOT_CMD_FATAL_EN);
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/* Clear the Root status register */
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pci_read_config_dword(dev, pos + PCI_ERR_ROOT_STATUS, &dconfig);
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pci_write_config_dword(dev, pos + PCI_ERR_ROOT_STATUS, dconfig);
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}
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return 0;
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}
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@ -3,23 +3,29 @@
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*
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* Copyright (C) 2005-2007 Cavium Networks
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* Copyright (C) 2005-2009 Cavium Networks
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*/
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#ifndef __OCTEON_PCI_COMMON_H__
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#define __OCTEON_PCI_COMMON_H__
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#ifndef __PCI_OCTEON_H__
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#define __PCI_OCTEON_H__
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#include <linux/pci.h>
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/* Some PCI cards require delays when accessing config space. */
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#define PCI_CONFIG_SPACE_DELAY 10000
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/* pcibios_map_irq() is defined inside pci-common.c. All it does is call the
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Octeon specific version pointed to by this variable. This function needs to
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change for PCI or PCIe based hosts */
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extern typeof(pcibios_map_irq) *octeon_pcibios_map_irq;
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/*
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* pcibios_map_irq() is defined inside pci-octeon.c. All it does is
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* call the Octeon specific version pointed to by this variable. This
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* function needs to change for PCI or PCIe based hosts.
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*/
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extern int (*octeon_pcibios_map_irq)(const struct pci_dev *dev,
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u8 slot, u8 pin);
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/* The following defines are only used when octeon_dma_bar_type =
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OCTEON_DMA_BAR_TYPE_BIG */
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/*
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* The following defines are used when octeon_dma_bar_type =
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* OCTEON_DMA_BAR_TYPE_BIG
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*/
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#define OCTEON_PCI_BAR1_HOLE_BITS 5
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#define OCTEON_PCI_BAR1_HOLE_SIZE (1ul<<(OCTEON_PCI_BAR1_HOLE_BITS+3))
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@ -30,9 +36,9 @@ enum octeon_dma_bar_type {
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OCTEON_DMA_BAR_TYPE_PCIE
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};
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/**
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* This is a variable to tell the DMA mapping system in dma-octeon.c
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* how to map PCI DMA addresses.
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/*
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* This tells the DMA mapping system in dma-octeon.c how to map PCI
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* DMA addresses.
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*/
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extern enum octeon_dma_bar_type octeon_dma_bar_type;
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@ -52,3 +52,8 @@ obj-$(CONFIG_VICTOR_MPC30X) += fixup-mpc30x.o
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obj-$(CONFIG_ZAO_CAPCELLA) += fixup-capcella.o
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obj-$(CONFIG_WR_PPMC) += fixup-wrppmc.o
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obj-$(CONFIG_MIKROTIK_RB532) += pci-rc32434.o ops-rc32434.o fixup-rc32434.o
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obj-$(CONFIG_CPU_CAVIUM_OCTEON) += pci-octeon.o pcie-octeon.o
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ifdef CONFIG_PCI_MSI
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obj-$(CONFIG_CPU_CAVIUM_OCTEON) += msi-octeon.o
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endif
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@ -3,7 +3,7 @@
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*
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* Copyright (C) 2005-2007 Cavium Networks
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* Copyright (C) 2005-2009 Cavium Networks
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*/
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#include <linux/kernel.h>
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#include <linux/init.h>
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@ -16,8 +16,7 @@
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#include <asm/octeon/cvmx-pci-defs.h>
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#include <asm/octeon/cvmx-npei-defs.h>
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#include <asm/octeon/cvmx-pexp-defs.h>
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#include "pci-common.h"
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#include <asm/octeon/pci-octeon.h>
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/*
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* Each bit in msi_free_irq_bitmask represents a MSI interrupt that is
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@ -47,8 +46,8 @@ static DEFINE_SPINLOCK(msi_free_irq_bitmask_lock);
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* programming the MSI control bits [6:4] before calling
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* pci_enable_msi().
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*
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* @param dev Device requesting MSI interrupts
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* @param desc MSI descriptor
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* @dev: Device requesting MSI interrupts
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* @desc: MSI descriptor
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*
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* Returns 0 on success.
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*/
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@ -213,14 +212,9 @@ void arch_teardown_msi_irq(unsigned int irq)
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}
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/**
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/*
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* Called by the interrupt handling code when an MSI interrupt
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* occurs.
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*
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* @param cpl
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* @param dev_id
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*
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* @return
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*/
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static irqreturn_t octeon_msi_interrupt(int cpl, void *dev_id)
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{
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@ -256,31 +250,37 @@ static irqreturn_t octeon_msi_interrupt(int cpl, void *dev_id)
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}
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/**
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/*
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* Initializes the MSI interrupt handling code
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*
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* @return
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*/
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int octeon_msi_initialize(void)
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{
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int r;
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if (octeon_has_feature(OCTEON_FEATURE_PCIE)) {
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r = request_irq(OCTEON_IRQ_PCI_MSI0, octeon_msi_interrupt,
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if (request_irq(OCTEON_IRQ_PCI_MSI0, octeon_msi_interrupt,
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IRQF_SHARED,
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"MSI[0:63]", octeon_msi_interrupt);
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"MSI[0:63]", octeon_msi_interrupt))
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panic("request_irq(OCTEON_IRQ_PCI_MSI0) failed");
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} else if (octeon_is_pci_host()) {
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r = request_irq(OCTEON_IRQ_PCI_MSI0, octeon_msi_interrupt,
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if (request_irq(OCTEON_IRQ_PCI_MSI0, octeon_msi_interrupt,
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IRQF_SHARED,
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"MSI[0:15]", octeon_msi_interrupt);
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r += request_irq(OCTEON_IRQ_PCI_MSI1, octeon_msi_interrupt,
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IRQF_SHARED,
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"MSI[16:31]", octeon_msi_interrupt);
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r += request_irq(OCTEON_IRQ_PCI_MSI2, octeon_msi_interrupt,
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IRQF_SHARED,
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"MSI[32:47]", octeon_msi_interrupt);
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r += request_irq(OCTEON_IRQ_PCI_MSI3, octeon_msi_interrupt,
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IRQF_SHARED,
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"MSI[48:63]", octeon_msi_interrupt);
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"MSI[0:15]", octeon_msi_interrupt))
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panic("request_irq(OCTEON_IRQ_PCI_MSI0) failed");
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if (request_irq(OCTEON_IRQ_PCI_MSI1, octeon_msi_interrupt,
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IRQF_SHARED,
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"MSI[16:31]", octeon_msi_interrupt))
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panic("request_irq(OCTEON_IRQ_PCI_MSI1) failed");
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if (request_irq(OCTEON_IRQ_PCI_MSI2, octeon_msi_interrupt,
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IRQF_SHARED,
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"MSI[32:47]", octeon_msi_interrupt))
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panic("request_irq(OCTEON_IRQ_PCI_MSI2) failed");
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if (request_irq(OCTEON_IRQ_PCI_MSI3, octeon_msi_interrupt,
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IRQF_SHARED,
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"MSI[48:63]", octeon_msi_interrupt))
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panic("request_irq(OCTEON_IRQ_PCI_MSI3) failed");
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}
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return 0;
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}
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@ -3,7 +3,7 @@
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*
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* Copyright (C) 2005-2007 Cavium Networks
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* Copyright (C) 2005-2009 Cavium Networks
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*/
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#include <linux/kernel.h>
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#include <linux/init.h>
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@ -17,8 +17,7 @@
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#include <asm/octeon/octeon.h>
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#include <asm/octeon/cvmx-npi-defs.h>
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#include <asm/octeon/cvmx-pci-defs.h>
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#include "pci-common.h"
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#include <asm/octeon/pci-octeon.h>
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#define USE_OCTEON_INTERNAL_ARBITER
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@ -54,6 +53,126 @@ union octeon_pci_address {
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} s;
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};
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int __initdata (*octeon_pcibios_map_irq)(const struct pci_dev *dev,
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u8 slot, u8 pin);
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enum octeon_dma_bar_type octeon_dma_bar_type = OCTEON_DMA_BAR_TYPE_INVALID;
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/**
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* Map a PCI device to the appropriate interrupt line
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*
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* @dev: The Linux PCI device structure for the device to map
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* @slot: The slot number for this device on __BUS 0__. Linux
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* enumerates through all the bridges and figures out the
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* slot on Bus 0 where this device eventually hooks to.
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* @pin: The PCI interrupt pin read from the device, then swizzled
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* as it goes through each bridge.
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* Returns Interrupt number for the device
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*/
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int __init pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
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{
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if (octeon_pcibios_map_irq)
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return octeon_pcibios_map_irq(dev, slot, pin);
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else
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panic("octeon_pcibios_map_irq not set.");
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}
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/*
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* Called to perform platform specific PCI setup
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*/
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int pcibios_plat_dev_init(struct pci_dev *dev)
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{
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uint16_t config;
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uint32_t dconfig;
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int pos;
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/*
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* Force the Cache line setting to 64 bytes. The standard
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* Linux bus scan doesn't seem to set it. Octeon really has
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* 128 byte lines, but Intel bridges get really upset if you
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* try and set values above 64 bytes. Value is specified in
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* 32bit words.
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*/
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pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, 64 / 4);
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/* Set latency timers for all devices */
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pci_write_config_byte(dev, PCI_LATENCY_TIMER, 48);
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/* Enable reporting System errors and parity errors on all devices */
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/* Enable parity checking and error reporting */
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pci_read_config_word(dev, PCI_COMMAND, &config);
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config |= PCI_COMMAND_PARITY | PCI_COMMAND_SERR;
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pci_write_config_word(dev, PCI_COMMAND, config);
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if (dev->subordinate) {
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/* Set latency timers on sub bridges */
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pci_write_config_byte(dev, PCI_SEC_LATENCY_TIMER, 48);
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/* More bridge error detection */
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pci_read_config_word(dev, PCI_BRIDGE_CONTROL, &config);
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config |= PCI_BRIDGE_CTL_PARITY | PCI_BRIDGE_CTL_SERR;
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pci_write_config_word(dev, PCI_BRIDGE_CONTROL, config);
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}
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/* Enable the PCIe normal error reporting */
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pos = pci_find_capability(dev, PCI_CAP_ID_EXP);
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if (pos) {
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/* Update Device Control */
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pci_read_config_word(dev, pos + PCI_EXP_DEVCTL, &config);
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/* Correctable Error Reporting */
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config |= PCI_EXP_DEVCTL_CERE;
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/* Non-Fatal Error Reporting */
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config |= PCI_EXP_DEVCTL_NFERE;
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/* Fatal Error Reporting */
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config |= PCI_EXP_DEVCTL_FERE;
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/* Unsupported Request */
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config |= PCI_EXP_DEVCTL_URRE;
|
||||
pci_write_config_word(dev, pos + PCI_EXP_DEVCTL, config);
|
||||
}
|
||||
|
||||
/* Find the Advanced Error Reporting capability */
|
||||
pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ERR);
|
||||
if (pos) {
|
||||
/* Clear Uncorrectable Error Status */
|
||||
pci_read_config_dword(dev, pos + PCI_ERR_UNCOR_STATUS,
|
||||
&dconfig);
|
||||
pci_write_config_dword(dev, pos + PCI_ERR_UNCOR_STATUS,
|
||||
dconfig);
|
||||
/* Enable reporting of all uncorrectable errors */
|
||||
/* Uncorrectable Error Mask - turned on bits disable errors */
|
||||
pci_write_config_dword(dev, pos + PCI_ERR_UNCOR_MASK, 0);
|
||||
/*
|
||||
* Leave severity at HW default. This only controls if
|
||||
* errors are reported as uncorrectable or
|
||||
* correctable, not if the error is reported.
|
||||
*/
|
||||
/* PCI_ERR_UNCOR_SEVER - Uncorrectable Error Severity */
|
||||
/* Clear Correctable Error Status */
|
||||
pci_read_config_dword(dev, pos + PCI_ERR_COR_STATUS, &dconfig);
|
||||
pci_write_config_dword(dev, pos + PCI_ERR_COR_STATUS, dconfig);
|
||||
/* Enable reporting of all correctable errors */
|
||||
/* Correctable Error Mask - turned on bits disable errors */
|
||||
pci_write_config_dword(dev, pos + PCI_ERR_COR_MASK, 0);
|
||||
/* Advanced Error Capabilities */
|
||||
pci_read_config_dword(dev, pos + PCI_ERR_CAP, &dconfig);
|
||||
/* ECRC Generation Enable */
|
||||
if (config & PCI_ERR_CAP_ECRC_GENC)
|
||||
config |= PCI_ERR_CAP_ECRC_GENE;
|
||||
/* ECRC Check Enable */
|
||||
if (config & PCI_ERR_CAP_ECRC_CHKC)
|
||||
config |= PCI_ERR_CAP_ECRC_CHKE;
|
||||
pci_write_config_dword(dev, pos + PCI_ERR_CAP, dconfig);
|
||||
/* PCI_ERR_HEADER_LOG - Header Log Register (16 bytes) */
|
||||
/* Report all errors to the root complex */
|
||||
pci_write_config_dword(dev, pos + PCI_ERR_ROOT_COMMAND,
|
||||
PCI_ERR_ROOT_CMD_COR_EN |
|
||||
PCI_ERR_ROOT_CMD_NONFATAL_EN |
|
||||
PCI_ERR_ROOT_CMD_FATAL_EN);
|
||||
/* Clear the Root status register */
|
||||
pci_read_config_dword(dev, pos + PCI_ERR_ROOT_STATUS, &dconfig);
|
||||
pci_write_config_dword(dev, pos + PCI_ERR_ROOT_STATUS, dconfig);
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
/**
|
||||
* Return the mapping of PCI device number to IRQ line. Each
|
||||
* character in the return string represents the interrupt
|
||||
|
|
@ -136,9 +255,8 @@ int __init octeon_pci_pcibios_map_irq(const struct pci_dev *dev,
|
|||
}
|
||||
|
||||
|
||||
/**
|
||||
/*
|
||||
* Read a value from configuration space
|
||||
*
|
||||
*/
|
||||
static int octeon_read_config(struct pci_bus *bus, unsigned int devfn,
|
||||
int reg, int size, u32 *val)
|
||||
|
|
@ -174,15 +292,8 @@ static int octeon_read_config(struct pci_bus *bus, unsigned int devfn,
|
|||
}
|
||||
|
||||
|
||||
/**
|
||||
/*
|
||||
* Write a value to PCI configuration space
|
||||
*
|
||||
* @bus:
|
||||
* @devfn:
|
||||
* @reg:
|
||||
* @size:
|
||||
* @val:
|
||||
* Returns
|
||||
*/
|
||||
static int octeon_write_config(struct pci_bus *bus, unsigned int devfn,
|
||||
int reg, int size, u32 val)
|
||||
|
|
@ -251,10 +362,8 @@ static struct pci_controller octeon_pci_controller = {
|
|||
};
|
||||
|
||||
|
||||
/**
|
||||
/*
|
||||
* Low level initialize the Octeon PCI controller
|
||||
*
|
||||
* Returns
|
||||
*/
|
||||
static void octeon_pci_initialize(void)
|
||||
{
|
||||
|
|
@ -398,7 +507,7 @@ static void octeon_pci_initialize(void)
|
|||
pci_int_arb_cfg.s.en = 1; /* Internal arbiter enable */
|
||||
cvmx_write_csr(CVMX_NPI_PCI_INT_ARB_CFG, pci_int_arb_cfg.u64);
|
||||
}
|
||||
#endif /* USE_OCTEON_INTERNAL_ARBITER */
|
||||
#endif /* USE_OCTEON_INTERNAL_ARBITER */
|
||||
|
||||
/*
|
||||
* Preferrably written to 1 to set MLTD. [RDSATI,TRTAE,
|
||||
|
|
@ -457,10 +566,8 @@ static void octeon_pci_initialize(void)
|
|||
}
|
||||
|
||||
|
||||
/**
|
||||
/*
|
||||
* Initialize the Octeon PCI controller
|
||||
*
|
||||
* Returns
|
||||
*/
|
||||
static int __init octeon_pci_setup(void)
|
||||
{
|
||||
|
|
@ -18,8 +18,7 @@
|
|||
#include <asm/octeon/cvmx-pescx-defs.h>
|
||||
#include <asm/octeon/cvmx-pexp-defs.h>
|
||||
#include <asm/octeon/cvmx-helper-errata.h>
|
||||
|
||||
#include "pci-common.h"
|
||||
#include <asm/octeon/pci-octeon.h>
|
||||
|
||||
union cvmx_pcie_address {
|
||||
uint64_t u64;
|
||||
|
|
@ -976,13 +975,13 @@ static int cvmx_pcie_rc_initialize(int pcie_port)
|
|||
/**
|
||||
* Map a PCI device to the appropriate interrupt line
|
||||
*
|
||||
* @param dev The Linux PCI device structure for the device to map
|
||||
* @param slot The slot number for this device on __BUS 0__. Linux
|
||||
* @dev: The Linux PCI device structure for the device to map
|
||||
* @slot: The slot number for this device on __BUS 0__. Linux
|
||||
* enumerates through all the bridges and figures out the
|
||||
* slot on Bus 0 where this device eventually hooks to.
|
||||
* @param pin The PCI interrupt pin read from the device, then swizzled
|
||||
* @pin: The PCI interrupt pin read from the device, then swizzled
|
||||
* as it goes through each bridge.
|
||||
* @return Interrupt number for the device
|
||||
* Returns Interrupt number for the device
|
||||
*/
|
||||
int __init octeon_pcie_pcibios_map_irq(const struct pci_dev *dev,
|
||||
u8 slot, u8 pin)
|
||||
|
|
@ -1025,12 +1024,12 @@ int __init octeon_pcie_pcibios_map_irq(const struct pci_dev *dev,
|
|||
/**
|
||||
* Read a value from configuration space
|
||||
*
|
||||
* @param bus
|
||||
* @param devfn
|
||||
* @param reg
|
||||
* @param size
|
||||
* @param val
|
||||
* @return
|
||||
* @bus:
|
||||
* @devfn:
|
||||
* @reg:
|
||||
* @size:
|
||||
* @val:
|
||||
* Returns
|
||||
*/
|
||||
static inline int octeon_pcie_read_config(int pcie_port, struct pci_bus *bus,
|
||||
unsigned int devfn, int reg, int size,
|
||||
|
|
@ -1156,12 +1155,12 @@ static int octeon_pcie1_read_config(struct pci_bus *bus, unsigned int devfn,
|
|||
/**
|
||||
* Write a value to PCI configuration space
|
||||
*
|
||||
* @param bus
|
||||
* @param devfn
|
||||
* @param reg
|
||||
* @param size
|
||||
* @param val
|
||||
* @return
|
||||
* @bus:
|
||||
* @devfn:
|
||||
* @reg:
|
||||
* @size:
|
||||
* @val:
|
||||
* Returns
|
||||
*/
|
||||
static inline int octeon_pcie_write_config(int pcie_port, struct pci_bus *bus,
|
||||
unsigned int devfn, int reg,
|
||||
|
|
@ -1254,7 +1253,7 @@ static struct pci_controller octeon_pcie1_controller = {
|
|||
/**
|
||||
* Initialize the Octeon PCIe controllers
|
||||
*
|
||||
* @return
|
||||
* Returns
|
||||
*/
|
||||
static int __init octeon_pcie_setup(void)
|
||||
{
|
||||
Loading…
Reference in a new issue