[WATCHDOG] U300 COH 901 327 watchdog driver
This patch adds support for the U300 COH 901 327 watchdog for the U300 platform recently added to RMK:s ARM tree. Signed-off-by: Linus Walleij <linus.walleij@stericsson.com> Signed-off-by: Wim Van Sebroeck <wim@iguana.be>
This commit is contained in:
Linus Walleij
Wim Van Sebroeck
parent
33c050c586
commit
01480701d5
3 changed files with 548 additions and 0 deletions
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@ -240,6 +240,16 @@ config ORION_WATCHDOG
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To compile this driver as a module, choose M here: the
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module will be called orion_wdt.
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config COH901327_WATCHDOG
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bool "ST-Ericsson COH 901 327 watchdog"
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depends on ARCH_U300
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default y if MACH_U300
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help
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Say Y here to include Watchdog timer support for the
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watchdog embedded into the ST-Ericsson U300 series platforms.
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This watchdog is used to reset the system and thus cannot be
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compiled as a module.
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# AVR32 Architecture
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config AT32AP700X_WDT
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@ -41,6 +41,7 @@ obj-$(CONFIG_PNX4008_WATCHDOG) += pnx4008_wdt.o
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obj-$(CONFIG_IOP_WATCHDOG) += iop_wdt.o
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obj-$(CONFIG_DAVINCI_WATCHDOG) += davinci_wdt.o
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obj-$(CONFIG_ORION_WATCHDOG) += orion_wdt.o
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obj-$(CONFIG_COH901327_WATCHDOG) += coh901327_wdt.o
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# AVR32 Architecture
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obj-$(CONFIG_AT32AP700X_WDT) += at32ap700x_wdt.o
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537
drivers/watchdog/coh901327_wdt.c
Normal file
537
drivers/watchdog/coh901327_wdt.c
Normal file
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@ -0,0 +1,537 @@
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/*
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* coh901327_wdt.c
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*
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* Copyright (C) 2008-2009 ST-Ericsson AB
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* License terms: GNU General Public License (GPL) version 2
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* Watchdog driver for the ST-Ericsson AB COH 901 327 IP core
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* Author: Linus Walleij <linus.walleij@stericsson.com>
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*/
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#include <linux/module.h>
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#include <linux/types.h>
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#include <linux/fs.h>
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#include <linux/miscdevice.h>
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#include <linux/watchdog.h>
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#include <linux/interrupt.h>
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#include <linux/pm.h>
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#include <linux/platform_device.h>
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#include <linux/io.h>
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#include <linux/bitops.h>
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#include <linux/uaccess.h>
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#include <linux/clk.h>
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#define DRV_NAME "WDOG COH 901 327"
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/*
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* COH 901 327 register definitions
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*/
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/* WDOG_FEED Register 32bit (-/W) */
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#define U300_WDOG_FR 0x00
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#define U300_WDOG_FR_FEED_RESTART_TIMER 0xFEEDU
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/* WDOG_TIMEOUT Register 32bit (R/W) */
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#define U300_WDOG_TR 0x04
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#define U300_WDOG_TR_TIMEOUT_MASK 0x7FFFU
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/* WDOG_DISABLE1 Register 32bit (-/W) */
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#define U300_WDOG_D1R 0x08
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#define U300_WDOG_D1R_DISABLE1_DISABLE_TIMER 0x2BADU
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/* WDOG_DISABLE2 Register 32bit (R/W) */
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#define U300_WDOG_D2R 0x0C
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#define U300_WDOG_D2R_DISABLE2_DISABLE_TIMER 0xCAFEU
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#define U300_WDOG_D2R_DISABLE_STATUS_DISABLED 0xDABEU
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#define U300_WDOG_D2R_DISABLE_STATUS_ENABLED 0x0000U
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/* WDOG_STATUS Register 32bit (R/W) */
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#define U300_WDOG_SR 0x10
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#define U300_WDOG_SR_STATUS_TIMED_OUT 0xCFE8U
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#define U300_WDOG_SR_STATUS_NORMAL 0x0000U
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#define U300_WDOG_SR_RESET_STATUS_RESET 0xE8B4U
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/* WDOG_COUNT Register 32bit (R/-) */
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#define U300_WDOG_CR 0x14
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#define U300_WDOG_CR_VALID_IND 0x8000U
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#define U300_WDOG_CR_VALID_STABLE 0x0000U
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#define U300_WDOG_CR_COUNT_VALUE_MASK 0x7FFFU
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/* WDOG_JTAGOVR Register 32bit (R/W) */
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#define U300_WDOG_JOR 0x18
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#define U300_WDOG_JOR_JTAG_MODE_IND 0x0002U
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#define U300_WDOG_JOR_JTAG_WATCHDOG_ENABLE 0x0001U
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/* WDOG_RESTART Register 32bit (-/W) */
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#define U300_WDOG_RR 0x1C
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#define U300_WDOG_RR_RESTART_VALUE_RESUME 0xACEDU
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/* WDOG_IRQ_EVENT Register 32bit (R/W) */
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#define U300_WDOG_IER 0x20
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#define U300_WDOG_IER_WILL_BARK_IRQ_EVENT_IND 0x0001U
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#define U300_WDOG_IER_WILL_BARK_IRQ_ACK_ENABLE 0x0001U
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/* WDOG_IRQ_MASK Register 32bit (R/W) */
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#define U300_WDOG_IMR 0x24
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#define U300_WDOG_IMR_WILL_BARK_IRQ_ENABLE 0x0001U
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/* WDOG_IRQ_FORCE Register 32bit (R/W) */
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#define U300_WDOG_IFR 0x28
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#define U300_WDOG_IFR_WILL_BARK_IRQ_FORCE_ENABLE 0x0001U
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/* Default timeout in seconds = 1 minute */
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static int margin = 60;
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static resource_size_t phybase;
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static resource_size_t physize;
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static int irq;
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static void __iomem *virtbase;
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static unsigned long coh901327_users;
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static unsigned long boot_status;
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static u16 wdogenablestore;
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static u16 irqmaskstore;
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static struct device *parent;
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/*
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* The watchdog block is of course always clocked, the
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* clk_enable()/clk_disable() calls are mainly for performing reference
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* counting higher up in the clock hierarchy.
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*/
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static struct clk *clk;
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/*
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* Enabling and disabling functions.
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*/
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static void coh901327_enable(u16 timeout)
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{
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u16 val;
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clk_enable(clk);
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/* Restart timer if it is disabled */
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val = readw(virtbase + U300_WDOG_D2R);
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if (val == U300_WDOG_D2R_DISABLE_STATUS_DISABLED)
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writew(U300_WDOG_RR_RESTART_VALUE_RESUME,
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virtbase + U300_WDOG_RR);
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/* Acknowledge any pending interrupt so it doesn't just fire off */
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writew(U300_WDOG_IER_WILL_BARK_IRQ_ACK_ENABLE,
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virtbase + U300_WDOG_IER);
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/* Enable the watchdog interrupt */
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writew(U300_WDOG_IMR_WILL_BARK_IRQ_ENABLE, virtbase + U300_WDOG_IMR);
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/* Activate the watchdog timer */
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writew(timeout, virtbase + U300_WDOG_TR);
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/* Start the watchdog timer */
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writew(U300_WDOG_FR_FEED_RESTART_TIMER, virtbase + U300_WDOG_FR);
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/*
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* Extra read so that this change propagate in the watchdog.
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*/
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(void) readw(virtbase + U300_WDOG_CR);
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val = readw(virtbase + U300_WDOG_D2R);
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clk_disable(clk);
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if (val != U300_WDOG_D2R_DISABLE_STATUS_ENABLED)
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dev_err(parent,
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"%s(): watchdog not enabled! D2R value %04x\n",
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__func__, val);
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}
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static void coh901327_disable(void)
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{
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u16 val;
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clk_enable(clk);
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/* Disable the watchdog interrupt if it is active */
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writew(0x0000U, virtbase + U300_WDOG_IMR);
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/* If the watchdog is currently enabled, attempt to disable it */
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val = readw(virtbase + U300_WDOG_D2R);
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if (val != U300_WDOG_D2R_DISABLE_STATUS_DISABLED) {
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writew(U300_WDOG_D1R_DISABLE1_DISABLE_TIMER,
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virtbase + U300_WDOG_D1R);
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writew(U300_WDOG_D2R_DISABLE2_DISABLE_TIMER,
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virtbase + U300_WDOG_D2R);
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/* Write this twice (else problems occur) */
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writew(U300_WDOG_D2R_DISABLE2_DISABLE_TIMER,
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virtbase + U300_WDOG_D2R);
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}
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val = readw(virtbase + U300_WDOG_D2R);
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clk_disable(clk);
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if (val != U300_WDOG_D2R_DISABLE_STATUS_DISABLED)
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dev_err(parent,
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"%s(): watchdog not disabled! D2R value %04x\n",
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__func__, val);
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}
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static void coh901327_start(void)
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{
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coh901327_enable(margin * 100);
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}
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static void coh901327_keepalive(void)
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{
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clk_enable(clk);
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/* Feed the watchdog */
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writew(U300_WDOG_FR_FEED_RESTART_TIMER,
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virtbase + U300_WDOG_FR);
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clk_disable(clk);
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}
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static int coh901327_settimeout(int time)
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{
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/*
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* Max margin is 327 since the 10ms
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* timeout register is max
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* 0x7FFF = 327670ms ~= 327s.
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*/
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if (time <= 0 || time > 327)
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return -EINVAL;
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margin = time;
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clk_enable(clk);
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/* Set new timeout value */
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writew(margin * 100, virtbase + U300_WDOG_TR);
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/* Feed the dog */
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writew(U300_WDOG_FR_FEED_RESTART_TIMER,
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virtbase + U300_WDOG_FR);
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clk_disable(clk);
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return 0;
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}
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/*
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* This interrupt occurs 10 ms before the watchdog WILL bark.
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*/
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static irqreturn_t coh901327_interrupt(int irq, void *data)
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{
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u16 val;
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/*
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* Ack IRQ? If this occurs we're FUBAR anyway, so
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* just acknowledge, disable the interrupt and await the imminent end.
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* If you at some point need a host of callbacks to be called
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* when the system is about to watchdog-reset, add them here!
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*
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* NOTE: on future versions of this IP-block, it will be possible
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* to prevent a watchdog reset by feeding the watchdog at this
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* point.
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*/
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clk_enable(clk);
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val = readw(virtbase + U300_WDOG_IER);
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if (val == U300_WDOG_IER_WILL_BARK_IRQ_EVENT_IND)
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writew(U300_WDOG_IER_WILL_BARK_IRQ_ACK_ENABLE,
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virtbase + U300_WDOG_IER);
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writew(0x0000U, virtbase + U300_WDOG_IMR);
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clk_disable(clk);
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dev_crit(parent, "watchdog is barking!\n");
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return IRQ_HANDLED;
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}
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/*
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* Allow only one user (daemon) to open the watchdog
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*/
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static int coh901327_open(struct inode *inode, struct file *file)
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{
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if (test_and_set_bit(1, &coh901327_users))
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return -EBUSY;
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coh901327_start();
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return nonseekable_open(inode, file);
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}
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static int coh901327_release(struct inode *inode, struct file *file)
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{
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clear_bit(1, &coh901327_users);
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coh901327_disable();
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return 0;
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}
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static ssize_t coh901327_write(struct file *file, const char __user *data,
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size_t len, loff_t *ppos)
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{
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if (len)
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coh901327_keepalive();
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return len;
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}
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static long coh901327_ioctl(struct file *file, unsigned int cmd,
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unsigned long arg)
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{
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int ret = -ENOTTY;
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u16 val;
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int time;
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int new_options;
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union {
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struct watchdog_info __user *ident;
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int __user *i;
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} uarg;
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static struct watchdog_info ident = {
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.options = WDIOF_CARDRESET |
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WDIOF_SETTIMEOUT |
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WDIOF_KEEPALIVEPING,
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.identity = "COH 901 327 Watchdog",
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.firmware_version = 1,
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};
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uarg.i = (int __user *)arg;
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switch (cmd) {
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case WDIOC_GETSUPPORT:
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ret = copy_to_user(uarg.ident, &ident,
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sizeof(ident)) ? -EFAULT : 0;
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break;
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case WDIOC_GETSTATUS:
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ret = put_user(0, uarg.i);
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break;
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case WDIOC_GETBOOTSTATUS:
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ret = put_user(boot_status, uarg.i);
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break;
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case WDIOC_SETOPTIONS:
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ret = get_user(new_options, uarg.i);
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if (ret)
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break;
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if (new_options & WDIOS_DISABLECARD)
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coh901327_disable();
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if (new_options & WDIOS_ENABLECARD)
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coh901327_start();
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ret = 0;
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break;
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case WDIOC_KEEPALIVE:
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coh901327_keepalive();
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ret = 0;
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break;
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case WDIOC_SETTIMEOUT:
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ret = get_user(time, uarg.i);
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if (ret)
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break;
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ret = coh901327_settimeout(time);
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if (ret)
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break;
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/* Then fall through to return set value */
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case WDIOC_GETTIMEOUT:
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ret = put_user(margin, uarg.i);
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break;
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case WDIOC_GETTIMELEFT:
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clk_enable(clk);
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/* Read repeatedly until the value is stable! */
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val = readw(virtbase + U300_WDOG_CR);
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while (val & U300_WDOG_CR_VALID_IND)
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val = readw(virtbase + U300_WDOG_CR);
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val &= U300_WDOG_CR_COUNT_VALUE_MASK;
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clk_disable(clk);
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if (val != 0)
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val /= 100;
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ret = put_user(val, uarg.i);
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break;
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}
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return ret;
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}
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static const struct file_operations coh901327_fops = {
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.owner = THIS_MODULE,
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.llseek = no_llseek,
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.write = coh901327_write,
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.unlocked_ioctl = coh901327_ioctl,
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.open = coh901327_open,
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.release = coh901327_release,
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};
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static struct miscdevice coh901327_miscdev = {
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.minor = WATCHDOG_MINOR,
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.name = "watchdog",
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.fops = &coh901327_fops,
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};
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static int __exit coh901327_remove(struct platform_device *pdev)
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{
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misc_deregister(&coh901327_miscdev);
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coh901327_disable();
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free_irq(irq, pdev);
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clk_put(clk);
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iounmap(virtbase);
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release_mem_region(phybase, physize);
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return 0;
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}
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static int __init coh901327_probe(struct platform_device *pdev)
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{
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int ret;
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u16 val;
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struct resource *res;
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res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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if (!res)
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return -ENOENT;
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parent = &pdev->dev;
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physize = resource_size(res);
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phybase = res->start;
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if (request_mem_region(phybase, physize, DRV_NAME) == NULL) {
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ret = -EBUSY;
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goto out;
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}
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virtbase = ioremap(phybase, physize);
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if (!virtbase) {
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ret = -ENOMEM;
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goto out_no_remap;
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}
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clk = clk_get(&pdev->dev, NULL);
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if (IS_ERR(clk)) {
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ret = PTR_ERR(clk);
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dev_err(&pdev->dev, "could not get clock\n");
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goto out_no_clk;
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}
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ret = clk_enable(clk);
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if (ret) {
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dev_err(&pdev->dev, "could not enable clock\n");
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goto out_no_clk_enable;
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}
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val = readw(virtbase + U300_WDOG_SR);
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switch (val) {
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case U300_WDOG_SR_STATUS_TIMED_OUT:
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dev_info(&pdev->dev,
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"watchdog timed out since last chip reset!\n");
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boot_status = WDIOF_CARDRESET;
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/* Status will be cleared below */
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break;
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case U300_WDOG_SR_STATUS_NORMAL:
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dev_info(&pdev->dev,
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"in normal status, no timeouts have occurred.\n");
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break;
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default:
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dev_info(&pdev->dev,
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"contains an illegal status code (%08x)\n", val);
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break;
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}
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val = readw(virtbase + U300_WDOG_D2R);
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switch (val) {
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case U300_WDOG_D2R_DISABLE_STATUS_DISABLED:
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dev_info(&pdev->dev, "currently disabled.\n");
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break;
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case U300_WDOG_D2R_DISABLE_STATUS_ENABLED:
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dev_info(&pdev->dev,
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"currently enabled! (disabling it now)\n");
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coh901327_disable();
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break;
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default:
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dev_err(&pdev->dev,
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"contains an illegal enable/disable code (%08x)\n",
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val);
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break;
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}
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/* Reset the watchdog */
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writew(U300_WDOG_SR_RESET_STATUS_RESET, virtbase + U300_WDOG_SR);
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irq = platform_get_irq(pdev, 0);
|
||||
if (request_irq(irq, coh901327_interrupt, IRQF_DISABLED,
|
||||
DRV_NAME " Bark", pdev)) {
|
||||
ret = -EIO;
|
||||
goto out_no_irq;
|
||||
}
|
||||
|
||||
clk_disable(clk);
|
||||
|
||||
ret = misc_register(&coh901327_miscdev);
|
||||
if (ret == 0)
|
||||
dev_info(&pdev->dev,
|
||||
"initialized. timer margin=%d sec\n", margin);
|
||||
else
|
||||
goto out_no_wdog;
|
||||
|
||||
return 0;
|
||||
|
||||
out_no_wdog:
|
||||
free_irq(irq, pdev);
|
||||
out_no_irq:
|
||||
clk_disable(clk);
|
||||
out_no_clk_enable:
|
||||
clk_put(clk);
|
||||
out_no_clk:
|
||||
iounmap(virtbase);
|
||||
out_no_remap:
|
||||
release_mem_region(phybase, SZ_4K);
|
||||
out:
|
||||
return ret;
|
||||
}
|
||||
|
||||
#ifdef CONFIG_PM
|
||||
static int coh901327_suspend(struct platform_device *pdev, pm_message_t state)
|
||||
{
|
||||
irqmaskstore = readw(virtbase + U300_WDOG_IMR) & 0x0001U;
|
||||
wdogenablestore = readw(virtbase + U300_WDOG_D2R);
|
||||
/* If watchdog is on, disable it here and now */
|
||||
if (wdogenablestore == U300_WDOG_D2R_DISABLE_STATUS_ENABLED)
|
||||
coh901327_disable();
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int coh901327_resume(struct platform_device *pdev)
|
||||
{
|
||||
/* Restore the watchdog interrupt */
|
||||
writew(irqmaskstore, virtbase + U300_WDOG_IMR);
|
||||
if (wdogenablestore == U300_WDOG_D2R_DISABLE_STATUS_ENABLED) {
|
||||
/* Restart the watchdog timer */
|
||||
writew(U300_WDOG_RR_RESTART_VALUE_RESUME,
|
||||
virtbase + U300_WDOG_RR);
|
||||
writew(U300_WDOG_FR_FEED_RESTART_TIMER,
|
||||
virtbase + U300_WDOG_FR);
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
#else
|
||||
#define coh901327_suspend NULL
|
||||
#define coh901327_resume NULL
|
||||
#endif
|
||||
|
||||
/*
|
||||
* Mistreating the watchdog is the only way to perform a software reset of the
|
||||
* system on EMP platforms. So we implement this and export a symbol for it.
|
||||
*/
|
||||
void coh901327_watchdog_reset(void)
|
||||
{
|
||||
/* Enable even if on JTAG too */
|
||||
writew(U300_WDOG_JOR_JTAG_WATCHDOG_ENABLE,
|
||||
virtbase + U300_WDOG_JOR);
|
||||
/*
|
||||
* Timeout = 5s, we have to wait for the watchdog reset to
|
||||
* actually take place: the watchdog will be reloaded with the
|
||||
* default value immediately, so we HAVE to reboot and get back
|
||||
* into the kernel in 30s, or the device will reboot again!
|
||||
* The boot loader will typically deactivate the watchdog, so we
|
||||
* need time enough for the boot loader to get to the point of
|
||||
* deactivating the watchdog before it is shut down by it.
|
||||
*
|
||||
* NOTE: on future versions of the watchdog, this restriction is
|
||||
* gone: the watchdog will be reloaded with a defaul value (1 min)
|
||||
* instead of last value, and you can conveniently set the watchdog
|
||||
* timeout to 10ms (value = 1) without any problems.
|
||||
*/
|
||||
coh901327_enable(500);
|
||||
/* Return and await doom */
|
||||
}
|
||||
|
||||
static struct platform_driver coh901327_driver = {
|
||||
.driver = {
|
||||
.owner = THIS_MODULE,
|
||||
.name = "coh901327_wdog",
|
||||
},
|
||||
.remove = __exit_p(coh901327_remove),
|
||||
.suspend = coh901327_suspend,
|
||||
.resume = coh901327_resume,
|
||||
};
|
||||
|
||||
static int __init coh901327_init(void)
|
||||
{
|
||||
return platform_driver_probe(&coh901327_driver, coh901327_probe);
|
||||
}
|
||||
module_init(coh901327_init);
|
||||
|
||||
static void __exit coh901327_exit(void)
|
||||
{
|
||||
platform_driver_unregister(&coh901327_driver);
|
||||
}
|
||||
module_exit(coh901327_exit);
|
||||
|
||||
MODULE_AUTHOR("Linus Walleij <linus.walleij@stericsson.com>");
|
||||
MODULE_DESCRIPTION("COH 901 327 Watchdog");
|
||||
|
||||
module_param(margin, int, 0);
|
||||
MODULE_PARM_DESC(margin, "Watchdog margin in seconds (default 60s)");
|
||||
|
||||
MODULE_LICENSE("GPL");
|
||||
MODULE_ALIAS_MISCDEV(WATCHDOG_MINOR);
|
||||
Loading…
Reference in a new issue