pata_at91: SMC settings calculation bugfixes, support for t6z and IORDY
* New code correctly calculates SMC registers values, adjusts calculated to admissible ranges, enlarges cycles when required and converts values into SMC's format. * Support for TDF cycles (ATA t6z) and IORDY line added. * Eliminate need in the initial_timing structure. * Code cleanup. Signed-off-by: Igor Plyatov <plyatov@gmail.com> Signed-off-by: Jeff Garzik <jgarzik@pobox.com>
This commit is contained in:
Igor Plyatov
Jeff Garzik
parent
af649a1b56
commit
0144261fa6
1 changed files with 193 additions and 94 deletions
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@ -3,6 +3,7 @@
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* with CompactFlash interface in True IDE mode
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*
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* Copyright (C) 2009 Matyukevich Sergey
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* 2011 Igor Plyatov
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*
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* Based on:
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* * generic platform driver by Paul Mundt: drivers/ata/pata_platform.c
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@ -31,38 +32,150 @@
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#include <mach/board.h>
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#include <mach/gpio.h>
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#define DRV_NAME "pata_at91"
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#define DRV_VERSION "0.3"
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#define DRV_NAME "pata_at91"
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#define DRV_VERSION "0.2"
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#define CF_IDE_OFFSET 0x00c00000
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#define CF_ALT_IDE_OFFSET 0x00e00000
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#define CF_IDE_RES_SIZE 0x08
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#define NCS_RD_PULSE_LIMIT 0x3f /* maximal value for pulse bitfields */
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#define CF_IDE_OFFSET 0x00c00000
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#define CF_ALT_IDE_OFFSET 0x00e00000
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#define CF_IDE_RES_SIZE 0x08
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#define CS_PULSE_MAXIMUM 319
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#define ER_SMC_CALC 1
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#define ER_SMC_RECALC 2
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struct at91_ide_info {
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unsigned long mode;
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unsigned int cs;
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struct clk *mck;
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void __iomem *ide_addr;
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void __iomem *alt_addr;
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};
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static const struct ata_timing initial_timing = {
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.mode = XFER_PIO_0,
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.setup = 70,
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.act8b = 290,
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.rec8b = 240,
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.cyc8b = 600,
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.active = 165,
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.recover = 150,
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.dmack_hold = 0,
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.cycle = 600,
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.udma = 0
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/**
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* struct smc_range - range of valid values for SMC register.
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*/
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struct smc_range {
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int min;
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int max;
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};
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/**
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* adjust_smc_value - adjust value for one of SMC registers.
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* @value: adjusted value
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* @range: array of SMC ranges with valid values
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* @size: SMC ranges array size
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*
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* This returns the difference between input and output value or negative
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* in case of invalid input value.
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* If negative returned, then output value = maximal possible from ranges.
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*/
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static int adjust_smc_value(int *value, struct smc_range *range, int size)
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{
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int maximum = (range + size - 1)->max;
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int remainder;
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do {
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if (*value < range->min) {
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remainder = range->min - *value;
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*value = range->min; /* nearest valid value */
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return remainder;
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} else if ((range->min <= *value) && (*value <= range->max))
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return 0;
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range++;
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} while (--size);
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*value = maximum;
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return -1; /* invalid value */
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}
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/**
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* calc_smc_vals - calculate SMC register values
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* @dev: ATA device
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* @setup: SMC_SETUP register value
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* @pulse: SMC_PULSE register value
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* @cycle: SMC_CYCLE register value
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*
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* This returns negative in case of invalid values for SMC registers:
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* -ER_SMC_RECALC - recalculation required for SMC values,
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* -ER_SMC_CALC - calculation failed (invalid input values).
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*
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* SMC use special coding scheme, see "Coding and Range of Timing
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* Parameters" table from AT91SAM9 datasheets.
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*
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* SMC_SETUP = 128*setup[5] + setup[4:0]
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* SMC_PULSE = 256*pulse[6] + pulse[5:0]
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* SMC_CYCLE = 256*cycle[8:7] + cycle[6:0]
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*/
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static int calc_smc_vals(struct device *dev,
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int *setup, int *pulse, int *cycle, int *cs_pulse)
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{
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int ret_val;
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int err = 0;
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struct smc_range range_setup[] = { /* SMC_SETUP valid values */
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{.min = 0, .max = 31}, /* first range */
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{.min = 128, .max = 159} /* second range */
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};
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struct smc_range range_pulse[] = { /* SMC_PULSE valid values */
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{.min = 0, .max = 63}, /* first range */
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{.min = 256, .max = 319} /* second range */
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};
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struct smc_range range_cycle[] = { /* SMC_CYCLE valid values */
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{.min = 0, .max = 127}, /* first range */
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{.min = 256, .max = 383}, /* second range */
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{.min = 512, .max = 639}, /* third range */
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{.min = 768, .max = 895} /* fourth range */
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};
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ret_val = adjust_smc_value(setup, range_setup, ARRAY_SIZE(range_setup));
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if (ret_val < 0)
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dev_warn(dev, "maximal SMC Setup value\n");
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else
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*cycle += ret_val;
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ret_val = adjust_smc_value(pulse, range_pulse, ARRAY_SIZE(range_pulse));
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if (ret_val < 0)
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dev_warn(dev, "maximal SMC Pulse value\n");
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else
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*cycle += ret_val;
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ret_val = adjust_smc_value(cycle, range_cycle, ARRAY_SIZE(range_cycle));
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if (ret_val < 0)
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dev_warn(dev, "maximal SMC Cycle value\n");
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*cs_pulse = *cycle;
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if (*cs_pulse > CS_PULSE_MAXIMUM) {
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dev_err(dev, "unable to calculate valid SMC settings\n");
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return -ER_SMC_CALC;
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}
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ret_val = adjust_smc_value(cs_pulse, range_pulse,
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ARRAY_SIZE(range_pulse));
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if (ret_val < 0) {
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dev_warn(dev, "maximal SMC CS Pulse value\n");
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} else if (ret_val != 0) {
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*cycle = *cs_pulse;
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dev_warn(dev, "SMC Cycle extended\n");
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err = -ER_SMC_RECALC;
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}
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return err;
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}
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/**
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* to_smc_format - convert values into SMC format
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* @setup: SETUP value of SMC Setup Register
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* @pulse: PULSE value of SMC Pulse Register
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* @cycle: CYCLE value of SMC Cycle Register
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* @cs_pulse: NCS_PULSE value of SMC Pulse Register
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*/
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static void to_smc_format(int *setup, int *pulse, int *cycle, int *cs_pulse)
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{
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*setup = (*setup & 0x1f) | ((*setup & 0x80) >> 2);
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*pulse = (*pulse & 0x3f) | ((*pulse & 0x100) >> 2);
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*cycle = (*cycle & 0x7f) | ((*cycle & 0x300) >> 1);
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*cs_pulse = (*cs_pulse & 0x3f) | ((*cs_pulse & 0x100) >> 2);
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}
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static unsigned long calc_mck_cycles(unsigned long ns, unsigned long mck_hz)
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{
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unsigned long mul;
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@ -80,85 +193,77 @@ static unsigned long calc_mck_cycles(unsigned long ns, unsigned long mck_hz)
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return (ns * mul + 65536) >> 16; /* rounding */
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}
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static void set_smc_mode(struct at91_ide_info *info)
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{
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at91_sys_write(AT91_SMC_MODE(info->cs), info->mode);
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return;
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}
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static void set_smc_timing(struct device *dev,
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/**
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* set_smc_timing - SMC timings setup.
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* @dev: device
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* @info: AT91 IDE info
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* @ata: ATA timings
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*
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* Its assumed that write timings are same as read timings,
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* cs_setup = 0 and cs_pulse = cycle.
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*/
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static void set_smc_timing(struct device *dev, struct ata_device *adev,
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struct at91_ide_info *info, const struct ata_timing *ata)
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{
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unsigned long read_cycle, write_cycle, active, recover;
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unsigned long nrd_setup, nrd_pulse, nrd_recover;
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unsigned long nwe_setup, nwe_pulse;
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unsigned long ncs_write_setup, ncs_write_pulse;
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unsigned long ncs_read_setup, ncs_read_pulse;
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unsigned long mck_hz;
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read_cycle = ata->cyc8b;
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nrd_setup = ata->setup;
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nrd_pulse = ata->act8b;
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nrd_recover = ata->rec8b;
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int ret = 0;
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int use_iordy;
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unsigned int t6z; /* data tristate time in ns */
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unsigned int cycle; /* SMC Cycle width in MCK ticks */
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unsigned int setup; /* SMC Setup width in MCK ticks */
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unsigned int pulse; /* CFIOR and CFIOW pulse width in MCK ticks */
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unsigned int cs_setup = 0;/* CS4 or CS5 setup width in MCK ticks */
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unsigned int cs_pulse; /* CS4 or CS5 pulse width in MCK ticks*/
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unsigned int tdf_cycles; /* SMC TDF MCK ticks */
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unsigned long mck_hz; /* MCK frequency in Hz */
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t6z = (ata->mode < XFER_PIO_5) ? 30 : 20;
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mck_hz = clk_get_rate(info->mck);
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cycle = calc_mck_cycles(ata->cyc8b, mck_hz);
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setup = calc_mck_cycles(ata->setup, mck_hz);
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pulse = calc_mck_cycles(ata->act8b, mck_hz);
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tdf_cycles = calc_mck_cycles(t6z, mck_hz);
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read_cycle = calc_mck_cycles(read_cycle, mck_hz);
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nrd_setup = calc_mck_cycles(nrd_setup, mck_hz);
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nrd_pulse = calc_mck_cycles(nrd_pulse, mck_hz);
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nrd_recover = calc_mck_cycles(nrd_recover, mck_hz);
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do {
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ret = calc_smc_vals(dev, &setup, &pulse, &cycle, &cs_pulse);
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} while (ret == -ER_SMC_RECALC);
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active = nrd_setup + nrd_pulse;
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recover = read_cycle - active;
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if (ret == -ER_SMC_CALC)
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dev_err(dev, "Interface may not operate correctly\n");
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/* Need at least two cycles recovery */
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if (recover < 2)
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read_cycle = active + 2;
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dev_dbg(dev, "SMC Setup=%u, Pulse=%u, Cycle=%u, CS Pulse=%u\n",
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setup, pulse, cycle, cs_pulse);
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to_smc_format(&setup, &pulse, &cycle, &cs_pulse);
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/* disable or enable waiting for IORDY signal */
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use_iordy = ata_pio_need_iordy(adev);
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if (use_iordy)
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info->mode |= AT91_SMC_EXNWMODE_READY;
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/* (CS0, CS1, DIR, OE) <= (CFCE1, CFCE2, CFRNW, NCSX) timings */
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ncs_read_setup = 1;
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ncs_read_pulse = read_cycle - 2;
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if (ncs_read_pulse > NCS_RD_PULSE_LIMIT) {
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ncs_read_pulse = NCS_RD_PULSE_LIMIT;
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dev_warn(dev, "ncs_read_pulse limited to maximal value %lu\n",
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ncs_read_pulse);
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if (tdf_cycles > 15) {
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tdf_cycles = 15;
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dev_warn(dev, "maximal SMC TDF Cycles value\n");
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}
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/* Write timings same as read timings */
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write_cycle = read_cycle;
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nwe_setup = nrd_setup;
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nwe_pulse = nrd_pulse;
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ncs_write_setup = ncs_read_setup;
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ncs_write_pulse = ncs_read_pulse;
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dev_dbg(dev, "ATA timings: nrd_setup = %lu nrd_pulse = %lu nrd_cycle = %lu\n",
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nrd_setup, nrd_pulse, read_cycle);
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dev_dbg(dev, "ATA timings: nwe_setup = %lu nwe_pulse = %lu nwe_cycle = %lu\n",
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nwe_setup, nwe_pulse, write_cycle);
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dev_dbg(dev, "ATA timings: ncs_read_setup = %lu ncs_read_pulse = %lu\n",
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ncs_read_setup, ncs_read_pulse);
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dev_dbg(dev, "ATA timings: ncs_write_setup = %lu ncs_write_pulse = %lu\n",
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ncs_write_setup, ncs_write_pulse);
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dev_dbg(dev, "Use IORDY=%u, TDF Cycles=%u\n", use_iordy, tdf_cycles);
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info->mode |= AT91_SMC_TDF_(tdf_cycles);
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/* write SMC Setup Register */
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at91_sys_write(AT91_SMC_SETUP(info->cs),
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AT91_SMC_NWESETUP_(nwe_setup) |
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AT91_SMC_NRDSETUP_(nrd_setup) |
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AT91_SMC_NCS_WRSETUP_(ncs_write_setup) |
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AT91_SMC_NCS_RDSETUP_(ncs_read_setup));
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AT91_SMC_NWESETUP_(setup) |
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AT91_SMC_NRDSETUP_(setup) |
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AT91_SMC_NCS_WRSETUP_(cs_setup) |
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AT91_SMC_NCS_RDSETUP_(cs_setup));
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/* write SMC Pulse Register */
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at91_sys_write(AT91_SMC_PULSE(info->cs),
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AT91_SMC_NWEPULSE_(nwe_pulse) |
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AT91_SMC_NRDPULSE_(nrd_pulse) |
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AT91_SMC_NCS_WRPULSE_(ncs_write_pulse) |
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AT91_SMC_NCS_RDPULSE_(ncs_read_pulse));
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AT91_SMC_NWEPULSE_(pulse) |
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AT91_SMC_NRDPULSE_(pulse) |
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AT91_SMC_NCS_WRPULSE_(cs_pulse) |
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AT91_SMC_NCS_RDPULSE_(cs_pulse));
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/* write SMC Cycle Register */
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at91_sys_write(AT91_SMC_CYCLE(info->cs),
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AT91_SMC_NWECYCLE_(write_cycle) |
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AT91_SMC_NRDCYCLE_(read_cycle));
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return;
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AT91_SMC_NWECYCLE_(cycle) |
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AT91_SMC_NRDCYCLE_(cycle));
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/* write SMC Mode Register*/
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at91_sys_write(AT91_SMC_MODE(info->cs), info->mode);
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}
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static void pata_at91_set_piomode(struct ata_port *ap, struct ata_device *adev)
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@ -172,15 +277,9 @@ static void pata_at91_set_piomode(struct ata_port *ap, struct ata_device *adev)
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if (ret) {
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dev_warn(ap->dev, "Failed to compute ATA timing %d, "
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"set PIO_0 timing\n", ret);
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set_smc_timing(ap->dev, info, &initial_timing);
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} else {
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set_smc_timing(ap->dev, info, &timing);
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timing = *ata_timing_find_mode(XFER_PIO_0);
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}
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/* Setup SMC mode */
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set_smc_mode(info);
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return;
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set_smc_timing(ap->dev, adev, info, &timing);
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}
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static unsigned int pata_at91_data_xfer_noirq(struct ata_device *dev,
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@ -346,7 +445,7 @@ static int __devexit pata_at91_remove(struct platform_device *pdev)
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static struct platform_driver pata_at91_driver = {
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.probe = pata_at91_probe,
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.remove = __devexit_p(pata_at91_remove),
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.driver = {
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.driver = {
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.name = DRV_NAME,
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.owner = THIS_MODULE,
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},
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