2009-02-09 00:56:54 -07:00
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/*
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* Copyright (c) 2008 Atheros Communications Inc.
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*/
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#ifndef EEPROM_H
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#define EEPROM_H
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#define AH_USE_EEPROM 0x1
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#ifdef __BIG_ENDIAN
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#define AR5416_EEPROM_MAGIC 0x5aa5
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#else
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#define AR5416_EEPROM_MAGIC 0xa55a
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#endif
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#define CTRY_DEBUG 0x1ff
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#define CTRY_DEFAULT 0
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#define AR_EEPROM_EEPCAP_COMPRESS_DIS 0x0001
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#define AR_EEPROM_EEPCAP_AES_DIS 0x0002
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#define AR_EEPROM_EEPCAP_FASTFRAME_DIS 0x0004
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#define AR_EEPROM_EEPCAP_BURST_DIS 0x0008
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#define AR_EEPROM_EEPCAP_MAXQCU 0x01F0
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#define AR_EEPROM_EEPCAP_MAXQCU_S 4
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#define AR_EEPROM_EEPCAP_HEAVY_CLIP_EN 0x0200
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#define AR_EEPROM_EEPCAP_KC_ENTRIES 0xF000
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#define AR_EEPROM_EEPCAP_KC_ENTRIES_S 12
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#define AR_EEPROM_EEREGCAP_EN_FCC_MIDBAND 0x0040
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#define AR_EEPROM_EEREGCAP_EN_KK_U1_EVEN 0x0080
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#define AR_EEPROM_EEREGCAP_EN_KK_U2 0x0100
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#define AR_EEPROM_EEREGCAP_EN_KK_MIDBAND 0x0200
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#define AR_EEPROM_EEREGCAP_EN_KK_U1_ODD 0x0400
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#define AR_EEPROM_EEREGCAP_EN_KK_NEW_11A 0x0800
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#define AR_EEPROM_EEREGCAP_EN_KK_U1_ODD_PRE4_0 0x4000
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#define AR_EEPROM_EEREGCAP_EN_KK_NEW_11A_PRE4_0 0x8000
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#define AR5416_EEPROM_MAGIC_OFFSET 0x0
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#define AR5416_EEPROM_S 2
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#define AR5416_EEPROM_OFFSET 0x2000
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#define AR5416_EEPROM_MAX 0xae0
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#define AR5416_EEPROM_START_ADDR \
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(AR_SREV_9100(ah)) ? 0x1fff1000 : 0x503f1200
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#define SD_NO_CTL 0xE0
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#define NO_CTL 0xff
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#define CTL_MODE_M 7
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#define CTL_11A 0
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#define CTL_11B 1
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#define CTL_11G 2
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#define CTL_2GHT20 5
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#define CTL_5GHT20 6
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#define CTL_2GHT40 7
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#define CTL_5GHT40 8
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#define EXT_ADDITIVE (0x8000)
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#define CTL_11A_EXT (CTL_11A | EXT_ADDITIVE)
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#define CTL_11G_EXT (CTL_11G | EXT_ADDITIVE)
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#define CTL_11B_EXT (CTL_11B | EXT_ADDITIVE)
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#define SUB_NUM_CTL_MODES_AT_5G_40 2
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#define SUB_NUM_CTL_MODES_AT_2G_40 3
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#define AR_EEPROM_MAC(i) (0x1d+(i))
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#define ATH9K_POW_SM(_r, _s) (((_r) & 0x3f) << (_s))
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#define FREQ2FBIN(x, y) ((y) ? ((x) - 2300) : (((x) - 4800) / 5))
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#define ath9k_hw_use_flash(_ah) (!(_ah->ah_flags & AH_USE_EEPROM))
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#define AR_EEPROM_RFSILENT_GPIO_SEL 0x001c
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#define AR_EEPROM_RFSILENT_GPIO_SEL_S 2
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#define AR_EEPROM_RFSILENT_POLARITY 0x0002
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#define AR_EEPROM_RFSILENT_POLARITY_S 1
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#define EEP_RFSILENT_ENABLED 0x0001
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#define EEP_RFSILENT_ENABLED_S 0
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#define EEP_RFSILENT_POLARITY 0x0002
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#define EEP_RFSILENT_POLARITY_S 1
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#define EEP_RFSILENT_GPIO_SEL 0x001c
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#define EEP_RFSILENT_GPIO_SEL_S 2
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#define AR5416_OPFLAGS_11A 0x01
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#define AR5416_OPFLAGS_11G 0x02
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#define AR5416_OPFLAGS_N_5G_HT40 0x04
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#define AR5416_OPFLAGS_N_2G_HT40 0x08
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#define AR5416_OPFLAGS_N_5G_HT20 0x10
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#define AR5416_OPFLAGS_N_2G_HT20 0x20
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#define AR5416_EEP_NO_BACK_VER 0x1
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#define AR5416_EEP_VER 0xE
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#define AR5416_EEP_VER_MINOR_MASK 0x0FFF
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#define AR5416_EEP_MINOR_VER_2 0x2
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#define AR5416_EEP_MINOR_VER_3 0x3
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#define AR5416_EEP_MINOR_VER_7 0x7
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#define AR5416_EEP_MINOR_VER_9 0x9
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#define AR5416_EEP_MINOR_VER_16 0x10
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#define AR5416_EEP_MINOR_VER_17 0x11
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#define AR5416_EEP_MINOR_VER_19 0x13
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#define AR5416_EEP_MINOR_VER_20 0x14
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#define AR5416_NUM_5G_CAL_PIERS 8
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#define AR5416_NUM_2G_CAL_PIERS 4
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#define AR5416_NUM_5G_20_TARGET_POWERS 8
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#define AR5416_NUM_5G_40_TARGET_POWERS 8
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#define AR5416_NUM_2G_CCK_TARGET_POWERS 3
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#define AR5416_NUM_2G_20_TARGET_POWERS 4
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#define AR5416_NUM_2G_40_TARGET_POWERS 4
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#define AR5416_NUM_CTLS 24
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#define AR5416_NUM_BAND_EDGES 8
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#define AR5416_NUM_PD_GAINS 4
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#define AR5416_PD_GAINS_IN_MASK 4
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#define AR5416_PD_GAIN_ICEPTS 5
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#define AR5416_EEPROM_MODAL_SPURS 5
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#define AR5416_MAX_RATE_POWER 63
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#define AR5416_NUM_PDADC_VALUES 128
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#define AR5416_BCHAN_UNUSED 0xFF
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#define AR5416_MAX_PWR_RANGE_IN_HALF_DB 64
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#define AR5416_MAX_CHAINS 3
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#define AR5416_PWR_TABLE_OFFSET -5
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/* Rx gain type values */
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#define AR5416_EEP_RXGAIN_23DB_BACKOFF 0
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#define AR5416_EEP_RXGAIN_13DB_BACKOFF 1
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#define AR5416_EEP_RXGAIN_ORIG 2
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/* Tx gain type values */
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#define AR5416_EEP_TXGAIN_ORIGINAL 0
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#define AR5416_EEP_TXGAIN_HIGH_POWER 1
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#define AR5416_EEP4K_START_LOC 64
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#define AR5416_EEP4K_NUM_2G_CAL_PIERS 3
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#define AR5416_EEP4K_NUM_2G_CCK_TARGET_POWERS 3
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#define AR5416_EEP4K_NUM_2G_20_TARGET_POWERS 3
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#define AR5416_EEP4K_NUM_2G_40_TARGET_POWERS 3
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#define AR5416_EEP4K_NUM_CTLS 12
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#define AR5416_EEP4K_NUM_BAND_EDGES 4
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#define AR5416_EEP4K_NUM_PD_GAINS 2
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#define AR5416_EEP4K_PD_GAINS_IN_MASK 4
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#define AR5416_EEP4K_PD_GAIN_ICEPTS 5
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#define AR5416_EEP4K_MAX_CHAINS 1
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enum eeprom_param {
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EEP_NFTHRESH_5,
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EEP_NFTHRESH_2,
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EEP_MAC_MSW,
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EEP_MAC_MID,
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EEP_MAC_LSW,
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EEP_REG_0,
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EEP_REG_1,
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EEP_OP_CAP,
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EEP_OP_MODE,
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EEP_RF_SILENT,
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EEP_OB_5,
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EEP_DB_5,
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EEP_OB_2,
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EEP_DB_2,
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EEP_MINOR_REV,
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EEP_TX_MASK,
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EEP_RX_MASK,
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EEP_RXGAIN_TYPE,
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EEP_TXGAIN_TYPE,
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EEP_DAC_HPWR_5G,
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};
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enum ar5416_rates {
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rate6mb, rate9mb, rate12mb, rate18mb,
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rate24mb, rate36mb, rate48mb, rate54mb,
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rate1l, rate2l, rate2s, rate5_5l,
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rate5_5s, rate11l, rate11s, rateXr,
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rateHt20_0, rateHt20_1, rateHt20_2, rateHt20_3,
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rateHt20_4, rateHt20_5, rateHt20_6, rateHt20_7,
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rateHt40_0, rateHt40_1, rateHt40_2, rateHt40_3,
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rateHt40_4, rateHt40_5, rateHt40_6, rateHt40_7,
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rateDupCck, rateDupOfdm, rateExtCck, rateExtOfdm,
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Ar5416RateSize
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};
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enum ath9k_hal_freq_band {
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ATH9K_HAL_FREQ_BAND_5GHZ = 0,
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ATH9K_HAL_FREQ_BAND_2GHZ = 1
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};
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struct base_eep_header {
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u16 length;
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u16 checksum;
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u16 version;
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u8 opCapFlags;
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u8 eepMisc;
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u16 regDmn[2];
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u8 macAddr[6];
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u8 rxMask;
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u8 txMask;
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u16 rfSilent;
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u16 blueToothOptions;
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u16 deviceCap;
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u32 binBuildNumber;
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u8 deviceType;
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u8 pwdclkind;
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u8 futureBase_1[2];
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u8 rxGainType;
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u8 dacHiPwrMode_5G;
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u8 futureBase_2;
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u8 dacLpMode;
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u8 txGainType;
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u8 rcChainMask;
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u8 desiredScaleCCK;
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u8 futureBase_3[23];
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} __packed;
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struct base_eep_header_4k {
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u16 length;
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u16 checksum;
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u16 version;
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u8 opCapFlags;
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u8 eepMisc;
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u16 regDmn[2];
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u8 macAddr[6];
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u8 rxMask;
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u8 txMask;
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u16 rfSilent;
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u16 blueToothOptions;
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u16 deviceCap;
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u32 binBuildNumber;
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u8 deviceType;
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u8 futureBase[1];
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} __packed;
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struct spur_chan {
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u16 spurChan;
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u8 spurRangeLow;
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u8 spurRangeHigh;
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} __packed;
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struct modal_eep_header {
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u32 antCtrlChain[AR5416_MAX_CHAINS];
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u32 antCtrlCommon;
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u8 antennaGainCh[AR5416_MAX_CHAINS];
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u8 switchSettling;
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u8 txRxAttenCh[AR5416_MAX_CHAINS];
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u8 rxTxMarginCh[AR5416_MAX_CHAINS];
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u8 adcDesiredSize;
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u8 pgaDesiredSize;
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u8 xlnaGainCh[AR5416_MAX_CHAINS];
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u8 txEndToXpaOff;
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u8 txEndToRxOn;
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u8 txFrameToXpaOn;
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u8 thresh62;
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u8 noiseFloorThreshCh[AR5416_MAX_CHAINS];
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u8 xpdGain;
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u8 xpd;
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u8 iqCalICh[AR5416_MAX_CHAINS];
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u8 iqCalQCh[AR5416_MAX_CHAINS];
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u8 pdGainOverlap;
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u8 ob;
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u8 db;
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u8 xpaBiasLvl;
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u8 pwrDecreaseFor2Chain;
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u8 pwrDecreaseFor3Chain;
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u8 txFrameToDataStart;
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u8 txFrameToPaOn;
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u8 ht40PowerIncForPdadc;
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u8 bswAtten[AR5416_MAX_CHAINS];
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u8 bswMargin[AR5416_MAX_CHAINS];
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u8 swSettleHt40;
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u8 xatten2Db[AR5416_MAX_CHAINS];
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u8 xatten2Margin[AR5416_MAX_CHAINS];
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u8 ob_ch1;
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u8 db_ch1;
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u8 useAnt1:1,
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force_xpaon:1,
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local_bias:1,
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femBandSelectUsed:1, xlnabufin:1, xlnaisel:2, xlnabufmode:1;
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u8 miscBits;
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u16 xpaBiasLvlFreq[3];
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u8 futureModal[6];
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struct spur_chan spurChans[AR5416_EEPROM_MODAL_SPURS];
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} __packed;
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|
|
struct modal_eep_4k_header {
|
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|
|
u32 antCtrlChain[AR5416_EEP4K_MAX_CHAINS];
|
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|
|
u32 antCtrlCommon;
|
|
|
|
|
u8 antennaGainCh[AR5416_EEP4K_MAX_CHAINS];
|
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|
|
u8 switchSettling;
|
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|
|
u8 txRxAttenCh[AR5416_EEP4K_MAX_CHAINS];
|
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|
|
u8 rxTxMarginCh[AR5416_EEP4K_MAX_CHAINS];
|
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|
|
u8 adcDesiredSize;
|
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|
|
u8 pgaDesiredSize;
|
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|
|
u8 xlnaGainCh[AR5416_EEP4K_MAX_CHAINS];
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|
|
u8 txEndToXpaOff;
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|
|
u8 txEndToRxOn;
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|
|
u8 txFrameToXpaOn;
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u8 thresh62;
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u8 noiseFloorThreshCh[AR5416_EEP4K_MAX_CHAINS];
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u8 xpdGain;
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u8 xpd;
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|
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u8 iqCalICh[AR5416_EEP4K_MAX_CHAINS];
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u8 iqCalQCh[AR5416_EEP4K_MAX_CHAINS];
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|
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u8 pdGainOverlap;
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|
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u8 ob_01;
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|
|
u8 db1_01;
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u8 xpaBiasLvl;
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u8 txFrameToDataStart;
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u8 txFrameToPaOn;
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|
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u8 ht40PowerIncForPdadc;
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|
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u8 bswAtten[AR5416_EEP4K_MAX_CHAINS];
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u8 bswMargin[AR5416_EEP4K_MAX_CHAINS];
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|
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u8 swSettleHt40;
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|
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u8 xatten2Db[AR5416_EEP4K_MAX_CHAINS];
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u8 xatten2Margin[AR5416_EEP4K_MAX_CHAINS];
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u8 db2_01;
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u8 version;
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u16 ob_234;
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u16 db1_234;
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u16 db2_234;
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u8 futureModal[4];
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struct spur_chan spurChans[AR5416_EEPROM_MODAL_SPURS];
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|
|
|
} __packed;
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struct cal_data_per_freq {
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u8 pwrPdg[AR5416_NUM_PD_GAINS][AR5416_PD_GAIN_ICEPTS];
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u8 vpdPdg[AR5416_NUM_PD_GAINS][AR5416_PD_GAIN_ICEPTS];
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|
|
} __packed;
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|
struct cal_data_per_freq_4k {
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|
|
u8 pwrPdg[AR5416_EEP4K_NUM_PD_GAINS][AR5416_EEP4K_PD_GAIN_ICEPTS];
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|
|
u8 vpdPdg[AR5416_EEP4K_NUM_PD_GAINS][AR5416_EEP4K_PD_GAIN_ICEPTS];
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|
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} __packed;
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struct cal_target_power_leg {
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|
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u8 bChannel;
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|
|
u8 tPow2x[4];
|
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|
|
|
} __packed;
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|
|
struct cal_target_power_ht {
|
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|
|
u8 bChannel;
|
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|
|
u8 tPow2x[8];
|
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|
|
|
} __packed;
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
#ifdef __BIG_ENDIAN_BITFIELD
|
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|
|
struct cal_ctl_edges {
|
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|
|
u8 bChannel;
|
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|
|
u8 flag:2, tPower:6;
|
|
|
|
|
} __packed;
|
|
|
|
|
#else
|
|
|
|
|
struct cal_ctl_edges {
|
|
|
|
|
u8 bChannel;
|
|
|
|
|
u8 tPower:6, flag:2;
|
|
|
|
|
} __packed;
|
|
|
|
|
#endif
|
|
|
|
|
|
|
|
|
|
struct cal_ctl_data {
|
|
|
|
|
struct cal_ctl_edges
|
|
|
|
|
ctlEdges[AR5416_MAX_CHAINS][AR5416_NUM_BAND_EDGES];
|
|
|
|
|
} __packed;
|
|
|
|
|
|
|
|
|
|
struct cal_ctl_data_4k {
|
|
|
|
|
struct cal_ctl_edges
|
|
|
|
|
ctlEdges[AR5416_EEP4K_MAX_CHAINS][AR5416_EEP4K_NUM_BAND_EDGES];
|
|
|
|
|
} __packed;
|
|
|
|
|
|
|
|
|
|
struct ar5416_eeprom_def {
|
|
|
|
|
struct base_eep_header baseEepHeader;
|
|
|
|
|
u8 custData[64];
|
|
|
|
|
struct modal_eep_header modalHeader[2];
|
|
|
|
|
u8 calFreqPier5G[AR5416_NUM_5G_CAL_PIERS];
|
|
|
|
|
u8 calFreqPier2G[AR5416_NUM_2G_CAL_PIERS];
|
|
|
|
|
struct cal_data_per_freq
|
|
|
|
|
calPierData5G[AR5416_MAX_CHAINS][AR5416_NUM_5G_CAL_PIERS];
|
|
|
|
|
struct cal_data_per_freq
|
|
|
|
|
calPierData2G[AR5416_MAX_CHAINS][AR5416_NUM_2G_CAL_PIERS];
|
|
|
|
|
struct cal_target_power_leg
|
|
|
|
|
calTargetPower5G[AR5416_NUM_5G_20_TARGET_POWERS];
|
|
|
|
|
struct cal_target_power_ht
|
|
|
|
|
calTargetPower5GHT20[AR5416_NUM_5G_20_TARGET_POWERS];
|
|
|
|
|
struct cal_target_power_ht
|
|
|
|
|
calTargetPower5GHT40[AR5416_NUM_5G_40_TARGET_POWERS];
|
|
|
|
|
struct cal_target_power_leg
|
|
|
|
|
calTargetPowerCck[AR5416_NUM_2G_CCK_TARGET_POWERS];
|
|
|
|
|
struct cal_target_power_leg
|
|
|
|
|
calTargetPower2G[AR5416_NUM_2G_20_TARGET_POWERS];
|
|
|
|
|
struct cal_target_power_ht
|
|
|
|
|
calTargetPower2GHT20[AR5416_NUM_2G_20_TARGET_POWERS];
|
|
|
|
|
struct cal_target_power_ht
|
|
|
|
|
calTargetPower2GHT40[AR5416_NUM_2G_40_TARGET_POWERS];
|
|
|
|
|
u8 ctlIndex[AR5416_NUM_CTLS];
|
|
|
|
|
struct cal_ctl_data ctlData[AR5416_NUM_CTLS];
|
|
|
|
|
u8 padding;
|
|
|
|
|
} __packed;
|
|
|
|
|
|
|
|
|
|
struct ar5416_eeprom_4k {
|
|
|
|
|
struct base_eep_header_4k baseEepHeader;
|
|
|
|
|
u8 custData[20];
|
|
|
|
|
struct modal_eep_4k_header modalHeader;
|
|
|
|
|
u8 calFreqPier2G[AR5416_EEP4K_NUM_2G_CAL_PIERS];
|
|
|
|
|
struct cal_data_per_freq_4k
|
|
|
|
|
calPierData2G[AR5416_EEP4K_MAX_CHAINS][AR5416_EEP4K_NUM_2G_CAL_PIERS];
|
|
|
|
|
struct cal_target_power_leg
|
|
|
|
|
calTargetPowerCck[AR5416_EEP4K_NUM_2G_CCK_TARGET_POWERS];
|
|
|
|
|
struct cal_target_power_leg
|
|
|
|
|
calTargetPower2G[AR5416_EEP4K_NUM_2G_20_TARGET_POWERS];
|
|
|
|
|
struct cal_target_power_ht
|
|
|
|
|
calTargetPower2GHT20[AR5416_EEP4K_NUM_2G_20_TARGET_POWERS];
|
|
|
|
|
struct cal_target_power_ht
|
|
|
|
|
calTargetPower2GHT40[AR5416_EEP4K_NUM_2G_40_TARGET_POWERS];
|
|
|
|
|
u8 ctlIndex[AR5416_EEP4K_NUM_CTLS];
|
|
|
|
|
struct cal_ctl_data_4k ctlData[AR5416_EEP4K_NUM_CTLS];
|
|
|
|
|
u8 padding;
|
|
|
|
|
} __packed;
|
|
|
|
|
|
|
|
|
|
enum reg_ext_bitmap {
|
|
|
|
|
REG_EXT_JAPAN_MIDBAND = 1,
|
|
|
|
|
REG_EXT_FCC_DFS_HT40 = 2,
|
|
|
|
|
REG_EXT_JAPAN_NONDFS_HT40 = 3,
|
|
|
|
|
REG_EXT_JAPAN_DFS_HT40 = 4
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
struct ath9k_country_entry {
|
|
|
|
|
u16 countryCode;
|
|
|
|
|
u16 regDmnEnum;
|
|
|
|
|
u16 regDmn5G;
|
|
|
|
|
u16 regDmn2G;
|
|
|
|
|
u8 isMultidomain;
|
|
|
|
|
u8 iso[3];
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
enum hal_eep_map {
|
|
|
|
|
EEP_MAP_DEFAULT = 0x0,
|
|
|
|
|
EEP_MAP_4KBITS,
|
|
|
|
|
EEP_MAP_MAX
|
|
|
|
|
};
|
|
|
|
|
|
2009-02-09 00:57:15 -07:00
|
|
|
struct eeprom_ops {
|
|
|
|
|
int (*check_eeprom)(struct ath_hw *hw);
|
|
|
|
|
u32 (*get_eeprom)(struct ath_hw *hw, enum eeprom_param param);
|
|
|
|
|
bool (*fill_eeprom)(struct ath_hw *hw);
|
|
|
|
|
int (*get_eeprom_ver)(struct ath_hw *hw);
|
|
|
|
|
int (*get_eeprom_rev)(struct ath_hw *hw);
|
|
|
|
|
u8 (*get_num_ant_config)(struct ath_hw *hw, enum ieee80211_band band);
|
|
|
|
|
u16 (*get_eeprom_antenna_cfg)(struct ath_hw *hw,
|
|
|
|
|
struct ath9k_channel *chan);
|
|
|
|
|
bool (*set_board_values)(struct ath_hw *hw, struct ath9k_channel *chan);
|
|
|
|
|
void (*set_addac)(struct ath_hw *hw, struct ath9k_channel *chan);
|
|
|
|
|
int (*set_txpower)(struct ath_hw *hw, struct ath9k_channel *chan,
|
|
|
|
|
u16 cfgCtl, u8 twiceAntennaReduction,
|
|
|
|
|
u8 twiceMaxRegulatoryPower, u8 powerLimit);
|
|
|
|
|
u16 (*get_spur_channel)(struct ath_hw *ah, u16 i, bool is2GHz);
|
|
|
|
|
};
|
|
|
|
|
|
2009-02-09 00:56:54 -07:00
|
|
|
#define ar5416_get_ntxchains(_txchainmask) \
|
2009-02-09 00:57:24 -07:00
|
|
|
(((_txchainmask >> 2) & 1) + \
|
2009-02-09 00:56:54 -07:00
|
|
|
((_txchainmask >> 1) & 1) + (_txchainmask & 1))
|
|
|
|
|
|
2009-02-09 00:57:12 -07:00
|
|
|
int ath9k_hw_eeprom_attach(struct ath_hw *ah);
|
2009-02-09 00:56:54 -07:00
|
|
|
|
|
|
|
|
#endif /* EEPROM_H */
|
