2009-02-02 06:11:54 -07:00
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/*
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* Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved.
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*/
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/*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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2010-01-08 08:02:30 -07:00
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#ifndef __MACH_MX3x_H__
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#define __MACH_MX3x_H__
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2009-02-02 06:11:54 -07:00
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/*
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* MX31 memory map:
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*
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* Virt Phys Size What
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* ---------------------------------------------------------------------------
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* FC000000 43F00000 1M AIPS 1
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* FC100000 50000000 1M SPBA
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* FC200000 53F00000 1M AIPS 2
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* FC500000 60000000 128M ROMPATCH
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* FC400000 68000000 128M AVIC
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* 70000000 256M IPU (MAX M2)
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* 80000000 256M CSD0 SDRAM/DDR
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* 90000000 256M CSD1 SDRAM/DDR
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* A0000000 128M CS0 Flash
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* A8000000 128M CS1 Flash
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* B0000000 32M CS2
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* B2000000 32M CS3
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* F4000000 B4000000 32M CS4
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* B6000000 32M CS5
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* FC320000 B8000000 64K NAND, SDRAM, WEIM, M3IF, EMI controllers
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* C0000000 64M PCMCIA/CF
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*/
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/*
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* L2CC
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*/
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2009-11-10 13:31:30 -07:00
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#define MX3x_L2CC_BASE_ADDR 0x30000000
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#define MX3x_L2CC_SIZE SZ_1M
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2009-02-02 06:11:54 -07:00
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/*
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* AIPS 1
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*/
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2009-11-10 13:31:30 -07:00
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#define MX3x_AIPS1_BASE_ADDR 0x43f00000
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#define MX3x_AIPS1_BASE_ADDR_VIRT 0xfc000000
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#define MX3x_AIPS1_SIZE SZ_1M
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#define MX3x_MAX_BASE_ADDR (MX3x_AIPS1_BASE_ADDR + 0x04000)
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#define MX3x_EVTMON_BASE_ADDR (MX3x_AIPS1_BASE_ADDR + 0x08000)
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#define MX3x_CLKCTL_BASE_ADDR (MX3x_AIPS1_BASE_ADDR + 0x0c000)
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#define MX3x_ETB_SLOT4_BASE_ADDR (MX3x_AIPS1_BASE_ADDR + 0x10000)
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#define MX3x_ETB_SLOT5_BASE_ADDR (MX3x_AIPS1_BASE_ADDR + 0x14000)
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#define MX3x_ECT_CTIO_BASE_ADDR (MX3x_AIPS1_BASE_ADDR + 0x18000)
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#define MX3x_I2C_BASE_ADDR (MX3x_AIPS1_BASE_ADDR + 0x80000)
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#define MX3x_I2C3_BASE_ADDR (MX3x_AIPS1_BASE_ADDR + 0x84000)
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#define MX3x_UART1_BASE_ADDR (MX3x_AIPS1_BASE_ADDR + 0x90000)
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#define MX3x_UART2_BASE_ADDR (MX3x_AIPS1_BASE_ADDR + 0x94000)
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#define MX3x_I2C2_BASE_ADDR (MX3x_AIPS1_BASE_ADDR + 0x98000)
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#define MX3x_OWIRE_BASE_ADDR (MX3x_AIPS1_BASE_ADDR + 0x9c000)
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#define MX3x_SSI1_BASE_ADDR (MX3x_AIPS1_BASE_ADDR + 0xa0000)
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#define MX3x_CSPI1_BASE_ADDR (MX3x_AIPS1_BASE_ADDR + 0xa4000)
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#define MX3x_KPP_BASE_ADDR (MX3x_AIPS1_BASE_ADDR + 0xa8000)
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#define MX3x_IOMUXC_BASE_ADDR (MX3x_AIPS1_BASE_ADDR + 0xac000)
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#define MX3x_ECT_IP1_BASE_ADDR (MX3x_AIPS1_BASE_ADDR + 0xb8000)
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#define MX3x_ECT_IP2_BASE_ADDR (MX3x_AIPS1_BASE_ADDR + 0xbc000)
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2009-02-02 06:11:54 -07:00
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/*
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* SPBA global module enabled #0
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*/
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2009-11-10 13:31:30 -07:00
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#define MX3x_SPBA0_BASE_ADDR 0x50000000
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#define MX3x_SPBA0_BASE_ADDR_VIRT 0xfc100000
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#define MX3x_SPBA0_SIZE SZ_1M
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#define MX3x_UART3_BASE_ADDR (MX3x_SPBA0_BASE_ADDR + 0x0c000)
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#define MX3x_CSPI2_BASE_ADDR (MX3x_SPBA0_BASE_ADDR + 0x10000)
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#define MX3x_SSI2_BASE_ADDR (MX3x_SPBA0_BASE_ADDR + 0x14000)
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#define MX3x_ATA_DMA_BASE_ADDR (MX3x_SPBA0_BASE_ADDR + 0x20000)
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#define MX3x_MSHC1_BASE_ADDR (MX3x_SPBA0_BASE_ADDR + 0x24000)
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#define MX3x_SPBA_CTRL_BASE_ADDR (MX3x_SPBA0_BASE_ADDR + 0x3c000)
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2009-02-02 06:11:54 -07:00
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/*
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* AIPS 2
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*/
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2009-11-10 13:31:30 -07:00
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#define MX3x_AIPS2_BASE_ADDR 0x53f00000
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#define MX3x_AIPS2_BASE_ADDR_VIRT 0xfc200000
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#define MX3x_AIPS2_SIZE SZ_1M
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#define MX3x_CCM_BASE_ADDR (MX3x_AIPS2_BASE_ADDR + 0x80000)
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#define MX3x_GPT1_BASE_ADDR (MX3x_AIPS2_BASE_ADDR + 0x90000)
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#define MX3x_EPIT1_BASE_ADDR (MX3x_AIPS2_BASE_ADDR + 0x94000)
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#define MX3x_EPIT2_BASE_ADDR (MX3x_AIPS2_BASE_ADDR + 0x98000)
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#define MX3x_GPIO3_BASE_ADDR (MX3x_AIPS2_BASE_ADDR + 0xa4000)
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#define MX3x_SCC_BASE_ADDR (MX3x_AIPS2_BASE_ADDR + 0xac000)
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#define MX3x_RNGA_BASE_ADDR (MX3x_AIPS2_BASE_ADDR + 0xb0000)
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#define MX3x_IPU_CTRL_BASE_ADDR (MX3x_AIPS2_BASE_ADDR + 0xc0000)
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#define MX3x_AUDMUX_BASE_ADDR (MX3x_AIPS2_BASE_ADDR + 0xc4000)
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#define MX3x_GPIO1_BASE_ADDR (MX3x_AIPS2_BASE_ADDR + 0xcc000)
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#define MX3x_GPIO2_BASE_ADDR (MX3x_AIPS2_BASE_ADDR + 0xd0000)
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#define MX3x_SDMA_BASE_ADDR (MX3x_AIPS2_BASE_ADDR + 0xd4000)
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#define MX3x_RTC_BASE_ADDR (MX3x_AIPS2_BASE_ADDR + 0xd8000)
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#define MX3x_WDOG_BASE_ADDR (MX3x_AIPS2_BASE_ADDR + 0xdc000)
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#define MX3x_PWM_BASE_ADDR (MX3x_AIPS2_BASE_ADDR + 0xe0000)
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#define MX3x_RTIC_BASE_ADDR (MX3x_AIPS2_BASE_ADDR + 0xec000)
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2009-02-02 06:11:54 -07:00
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/*
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* ROMP and AVIC
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*/
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2009-11-10 13:31:30 -07:00
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#define MX3x_ROMP_BASE_ADDR 0x60000000
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#define MX3x_ROMP_BASE_ADDR_VIRT 0xfc500000
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#define MX3x_ROMP_SIZE SZ_1M
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2009-02-02 06:11:54 -07:00
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2009-11-10 13:31:30 -07:00
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#define MX3x_AVIC_BASE_ADDR 0x68000000
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#define MX3x_AVIC_BASE_ADDR_VIRT 0xfc400000
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#define MX3x_AVIC_SIZE SZ_1M
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2009-02-02 06:11:54 -07:00
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2009-11-10 02:20:30 -07:00
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/*
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* Memory regions and CS
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*/
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2009-11-10 13:31:30 -07:00
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#define MX3x_IPU_MEM_BASE_ADDR 0x70000000
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#define MX3x_CSD0_BASE_ADDR 0x80000000
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#define MX3x_CSD1_BASE_ADDR 0x90000000
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2009-11-10 02:20:30 -07:00
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2009-11-10 13:31:30 -07:00
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#define MX3x_CS0_BASE_ADDR 0xa0000000
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#define MX3x_CS1_BASE_ADDR 0xa8000000
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#define MX3x_CS2_BASE_ADDR 0xb0000000
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#define MX3x_CS3_BASE_ADDR 0xb2000000
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2009-11-10 02:20:30 -07:00
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2009-11-10 13:31:30 -07:00
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#define MX3x_CS4_BASE_ADDR 0xb4000000
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#define MX3x_CS4_BASE_ADDR_VIRT 0xf4000000
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#define MX3x_CS4_SIZE SZ_32M
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2009-11-10 02:20:30 -07:00
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2009-11-10 13:31:30 -07:00
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#define MX3x_CS5_BASE_ADDR 0xb6000000
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#define MX3x_CS5_BASE_ADDR_VIRT 0xf6000000
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#define MX3x_CS5_SIZE SZ_32M
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2009-11-10 02:20:30 -07:00
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2009-02-02 06:11:54 -07:00
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/*
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* NAND, SDRAM, WEIM, M3IF, EMI controllers
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*/
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2009-11-10 13:31:30 -07:00
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#define MX3x_X_MEMC_BASE_ADDR 0xb8000000
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#define MX3x_X_MEMC_BASE_ADDR_VIRT 0xfc320000
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#define MX3x_X_MEMC_SIZE SZ_64K
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#define MX3x_ESDCTL_BASE_ADDR (MX3x_X_MEMC_BASE_ADDR + 0x1000)
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#define MX3x_WEIM_BASE_ADDR (MX3x_X_MEMC_BASE_ADDR + 0x2000)
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#define MX3x_M3IF_BASE_ADDR (MX3x_X_MEMC_BASE_ADDR + 0x3000)
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#define MX3x_EMI_CTL_BASE_ADDR (MX3x_X_MEMC_BASE_ADDR + 0x4000)
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#define MX3x_PCMCIA_CTL_BASE_ADDR MX3x_EMI_CTL_BASE_ADDR
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2009-02-02 06:11:54 -07:00
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2009-11-10 13:31:30 -07:00
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#define MX3x_PCMCIA_MEM_BASE_ADDR 0xbc000000
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2009-02-02 06:11:54 -07:00
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/*!
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* This macro defines the physical to virtual address mapping for all the
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* peripheral modules. It is used by passing in the physical address as x
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* and returning the virtual address. If the physical address is not mapped,
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* it returns 0xDEADBEEF
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*/
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#define IO_ADDRESS(x) \
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2009-02-19 04:48:35 -07:00
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(void __force __iomem *) \
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2009-02-02 06:11:54 -07:00
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(((x >= AIPS1_BASE_ADDR) && (x < (AIPS1_BASE_ADDR + AIPS1_SIZE))) ? AIPS1_IO_ADDRESS(x):\
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((x >= SPBA0_BASE_ADDR) && (x < (SPBA0_BASE_ADDR + SPBA0_SIZE))) ? SPBA0_IO_ADDRESS(x):\
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((x >= AIPS2_BASE_ADDR) && (x < (AIPS2_BASE_ADDR + AIPS2_SIZE))) ? AIPS2_IO_ADDRESS(x):\
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((x >= ROMP_BASE_ADDR) && (x < (ROMP_BASE_ADDR + ROMP_SIZE))) ? ROMP_IO_ADDRESS(x):\
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((x >= AVIC_BASE_ADDR) && (x < (AVIC_BASE_ADDR + AVIC_SIZE))) ? AVIC_IO_ADDRESS(x):\
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((x >= CS4_BASE_ADDR) && (x < (CS4_BASE_ADDR + CS4_SIZE))) ? CS4_IO_ADDRESS(x):\
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((x >= X_MEMC_BASE_ADDR) && (x < (X_MEMC_BASE_ADDR + X_MEMC_SIZE))) ? X_MEMC_IO_ADDRESS(x):\
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0xDEADBEEF)
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/*
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* define the address mapping macros: in physical address order
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*/
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#define L2CC_IO_ADDRESS(x) \
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(((x) - L2CC_BASE_ADDR) + L2CC_BASE_ADDR_VIRT)
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#define AIPS1_IO_ADDRESS(x) \
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(((x) - AIPS1_BASE_ADDR) + AIPS1_BASE_ADDR_VIRT)
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#define SPBA0_IO_ADDRESS(x) \
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(((x) - SPBA0_BASE_ADDR) + SPBA0_BASE_ADDR_VIRT)
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#define AIPS2_IO_ADDRESS(x) \
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(((x) - AIPS2_BASE_ADDR) + AIPS2_BASE_ADDR_VIRT)
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#define ROMP_IO_ADDRESS(x) \
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(((x) - ROMP_BASE_ADDR) + ROMP_BASE_ADDR_VIRT)
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#define AVIC_IO_ADDRESS(x) \
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(((x) - AVIC_BASE_ADDR) + AVIC_BASE_ADDR_VIRT)
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#define CS4_IO_ADDRESS(x) \
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(((x) - CS4_BASE_ADDR) + CS4_BASE_ADDR_VIRT)
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2009-05-17 12:18:08 -06:00
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#define CS5_IO_ADDRESS(x) \
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(((x) - CS5_BASE_ADDR) + CS5_BASE_ADDR_VIRT)
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2009-02-02 06:11:54 -07:00
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#define X_MEMC_IO_ADDRESS(x) \
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(((x) - X_MEMC_BASE_ADDR) + X_MEMC_BASE_ADDR_VIRT)
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#define PCMCIA_IO_ADDRESS(x) \
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(((x) - X_MEMC_BASE_ADDR) + X_MEMC_BASE_ADDR_VIRT)
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/*
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* Interrupt numbers
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*/
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2009-11-10 13:31:30 -07:00
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#define MX3x_INT_I2C3 3
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#define MX3x_INT_I2C2 4
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#define MX3x_INT_RTIC 6
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#define MX3x_INT_I2C 10
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#define MX3x_INT_CSPI2 13
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#define MX3x_INT_CSPI1 14
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#define MX3x_INT_ATA 15
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#define MX3x_INT_UART3 18
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#define MX3x_INT_IIM 19
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#define MX3x_INT_RNGA 22
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#define MX3x_INT_EVTMON 23
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#define MX3x_INT_KPP 24
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#define MX3x_INT_RTC 25
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#define MX3x_INT_PWM 26
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#define MX3x_INT_EPIT2 27
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#define MX3x_INT_EPIT1 28
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#define MX3x_INT_GPT 29
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#define MX3x_INT_POWER_FAIL 30
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#define MX3x_INT_UART2 32
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#define MX3x_INT_NANDFC 33
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#define MX3x_INT_SDMA 34
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#define MX3x_INT_MSHC1 39
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#define MX3x_INT_IPU_ERR 41
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#define MX3x_INT_IPU_SYN 42
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#define MX3x_INT_UART1 45
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#define MX3x_INT_ECT 48
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#define MX3x_INT_SCC_SCM 49
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#define MX3x_INT_SCC_SMN 50
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#define MX3x_INT_GPIO2 51
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#define MX3x_INT_GPIO1 52
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#define MX3x_INT_WDOG 55
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#define MX3x_INT_GPIO3 56
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#define MX3x_INT_EXT_POWER 58
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#define MX3x_INT_EXT_TEMPER 59
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#define MX3x_INT_EXT_SENSOR60 60
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#define MX3x_INT_EXT_SENSOR61 61
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#define MX3x_INT_EXT_WDOG 62
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#define MX3x_INT_EXT_TV 63
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#define MX3x_PROD_SIGNATURE 0x1 /* For MX31 */
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2009-02-02 06:11:54 -07:00
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/* silicon revisions specific to i.MX31 */
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2009-11-10 13:31:30 -07:00
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#define MX3x_CHIP_REV_1_0 0x10
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#define MX3x_CHIP_REV_1_1 0x11
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#define MX3x_CHIP_REV_1_2 0x12
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#define MX3x_CHIP_REV_1_3 0x13
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#define MX3x_CHIP_REV_2_0 0x20
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#define MX3x_CHIP_REV_2_1 0x21
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#define MX3x_CHIP_REV_2_2 0x22
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#define MX3x_CHIP_REV_2_3 0x23
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#define MX3x_CHIP_REV_3_0 0x30
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#define MX3x_CHIP_REV_3_1 0x31
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#define MX3x_CHIP_REV_3_2 0x32
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#define MX3x_SYSTEM_REV_MIN MX3x_CHIP_REV_1_0
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#define MX3x_SYSTEM_REV_NUM 3
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2009-02-02 06:11:54 -07:00
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/* Mandatory defines used globally */
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#if !defined(__ASSEMBLY__) && !defined(__MXC_BOOT_UNCOMPRESS)
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2009-11-21 12:17:18 -07:00
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extern unsigned int mx31_cpu_rev;
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extern void mx31_read_cpu_rev(void);
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2009-02-02 06:11:54 -07:00
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static inline int mx31_revision(void)
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{
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2009-11-21 12:17:18 -07:00
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return mx31_cpu_rev;
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2009-02-02 06:11:54 -07:00
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}
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#endif
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2009-12-17 09:17:54 -07:00
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#ifdef IMX_NEEDS_DEPRECATED_SYMBOLS
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2009-11-10 13:31:30 -07:00
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/* these should go away */
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#define L2CC_BASE_ADDR MX3x_L2CC_BASE_ADDR
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#define L2CC_SIZE MX3x_L2CC_SIZE
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#define AIPS1_BASE_ADDR MX3x_AIPS1_BASE_ADDR
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#define AIPS1_BASE_ADDR_VIRT MX3x_AIPS1_BASE_ADDR_VIRT
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#define AIPS1_SIZE MX3x_AIPS1_SIZE
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#define MAX_BASE_ADDR MX3x_MAX_BASE_ADDR
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#define EVTMON_BASE_ADDR MX3x_EVTMON_BASE_ADDR
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#define CLKCTL_BASE_ADDR MX3x_CLKCTL_BASE_ADDR
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#define ETB_SLOT4_BASE_ADDR MX3x_ETB_SLOT4_BASE_ADDR
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#define ETB_SLOT5_BASE_ADDR MX3x_ETB_SLOT5_BASE_ADDR
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#define ECT_CTIO_BASE_ADDR MX3x_ECT_CTIO_BASE_ADDR
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#define I2C_BASE_ADDR MX3x_I2C_BASE_ADDR
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#define I2C3_BASE_ADDR MX3x_I2C3_BASE_ADDR
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#define UART1_BASE_ADDR MX3x_UART1_BASE_ADDR
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#define UART2_BASE_ADDR MX3x_UART2_BASE_ADDR
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#define I2C2_BASE_ADDR MX3x_I2C2_BASE_ADDR
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#define OWIRE_BASE_ADDR MX3x_OWIRE_BASE_ADDR
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#define SSI1_BASE_ADDR MX3x_SSI1_BASE_ADDR
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#define CSPI1_BASE_ADDR MX3x_CSPI1_BASE_ADDR
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#define KPP_BASE_ADDR MX3x_KPP_BASE_ADDR
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#define IOMUXC_BASE_ADDR MX3x_IOMUXC_BASE_ADDR
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#define ECT_IP1_BASE_ADDR MX3x_ECT_IP1_BASE_ADDR
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#define ECT_IP2_BASE_ADDR MX3x_ECT_IP2_BASE_ADDR
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#define SPBA0_BASE_ADDR MX3x_SPBA0_BASE_ADDR
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#define SPBA0_BASE_ADDR_VIRT MX3x_SPBA0_BASE_ADDR_VIRT
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#define SPBA0_SIZE MX3x_SPBA0_SIZE
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#define UART3_BASE_ADDR MX3x_UART3_BASE_ADDR
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#define CSPI2_BASE_ADDR MX3x_CSPI2_BASE_ADDR
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#define SSI2_BASE_ADDR MX3x_SSI2_BASE_ADDR
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#define ATA_DMA_BASE_ADDR MX3x_ATA_DMA_BASE_ADDR
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#define MSHC1_BASE_ADDR MX3x_MSHC1_BASE_ADDR
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#define SPBA_CTRL_BASE_ADDR MX3x_SPBA_CTRL_BASE_ADDR
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#define AIPS2_BASE_ADDR MX3x_AIPS2_BASE_ADDR
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#define AIPS2_BASE_ADDR_VIRT MX3x_AIPS2_BASE_ADDR_VIRT
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#define AIPS2_SIZE MX3x_AIPS2_SIZE
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#define CCM_BASE_ADDR MX3x_CCM_BASE_ADDR
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#define GPT1_BASE_ADDR MX3x_GPT1_BASE_ADDR
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#define EPIT1_BASE_ADDR MX3x_EPIT1_BASE_ADDR
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#define EPIT2_BASE_ADDR MX3x_EPIT2_BASE_ADDR
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#define GPIO3_BASE_ADDR MX3x_GPIO3_BASE_ADDR
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#define SCC_BASE_ADDR MX3x_SCC_BASE_ADDR
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#define RNGA_BASE_ADDR MX3x_RNGA_BASE_ADDR
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#define IPU_CTRL_BASE_ADDR MX3x_IPU_CTRL_BASE_ADDR
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#define AUDMUX_BASE_ADDR MX3x_AUDMUX_BASE_ADDR
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#define GPIO1_BASE_ADDR MX3x_GPIO1_BASE_ADDR
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#define GPIO2_BASE_ADDR MX3x_GPIO2_BASE_ADDR
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#define SDMA_BASE_ADDR MX3x_SDMA_BASE_ADDR
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#define RTC_BASE_ADDR MX3x_RTC_BASE_ADDR
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#define WDOG_BASE_ADDR MX3x_WDOG_BASE_ADDR
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#define PWM_BASE_ADDR MX3x_PWM_BASE_ADDR
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#define RTIC_BASE_ADDR MX3x_RTIC_BASE_ADDR
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#define ROMP_BASE_ADDR MX3x_ROMP_BASE_ADDR
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#define ROMP_BASE_ADDR_VIRT MX3x_ROMP_BASE_ADDR_VIRT
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#define ROMP_SIZE MX3x_ROMP_SIZE
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#define AVIC_BASE_ADDR MX3x_AVIC_BASE_ADDR
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#define AVIC_BASE_ADDR_VIRT MX3x_AVIC_BASE_ADDR_VIRT
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#define AVIC_SIZE MX3x_AVIC_SIZE
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#define IPU_MEM_BASE_ADDR MX3x_IPU_MEM_BASE_ADDR
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#define CSD0_BASE_ADDR MX3x_CSD0_BASE_ADDR
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#define CSD1_BASE_ADDR MX3x_CSD1_BASE_ADDR
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#define CS0_BASE_ADDR MX3x_CS0_BASE_ADDR
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#define CS1_BASE_ADDR MX3x_CS1_BASE_ADDR
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#define CS2_BASE_ADDR MX3x_CS2_BASE_ADDR
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#define CS3_BASE_ADDR MX3x_CS3_BASE_ADDR
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#define CS4_BASE_ADDR MX3x_CS4_BASE_ADDR
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#define CS4_BASE_ADDR_VIRT MX3x_CS4_BASE_ADDR_VIRT
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#define CS4_SIZE MX3x_CS4_SIZE
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#define CS5_BASE_ADDR MX3x_CS5_BASE_ADDR
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#define CS5_BASE_ADDR_VIRT MX3x_CS5_BASE_ADDR_VIRT
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#define CS5_SIZE MX3x_CS5_SIZE
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#define X_MEMC_BASE_ADDR MX3x_X_MEMC_BASE_ADDR
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#define X_MEMC_BASE_ADDR_VIRT MX3x_X_MEMC_BASE_ADDR_VIRT
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#define X_MEMC_SIZE MX3x_X_MEMC_SIZE
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#define ESDCTL_BASE_ADDR MX3x_ESDCTL_BASE_ADDR
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#define WEIM_BASE_ADDR MX3x_WEIM_BASE_ADDR
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#define M3IF_BASE_ADDR MX3x_M3IF_BASE_ADDR
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#define EMI_CTL_BASE_ADDR MX3x_EMI_CTL_BASE_ADDR
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#define PCMCIA_CTL_BASE_ADDR MX3x_PCMCIA_CTL_BASE_ADDR
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#define PCMCIA_MEM_BASE_ADDR MX3x_PCMCIA_MEM_BASE_ADDR
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#define MXC_INT_I2C3 MX3x_INT_I2C3
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#define MXC_INT_I2C2 MX3x_INT_I2C2
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#define MXC_INT_RTIC MX3x_INT_RTIC
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#define MXC_INT_I2C MX3x_INT_I2C
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#define MXC_INT_CSPI2 MX3x_INT_CSPI2
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#define MXC_INT_CSPI1 MX3x_INT_CSPI1
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#define MXC_INT_ATA MX3x_INT_ATA
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#define MXC_INT_UART3 MX3x_INT_UART3
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#define MXC_INT_IIM MX3x_INT_IIM
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#define MXC_INT_RNGA MX3x_INT_RNGA
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#define MXC_INT_EVTMON MX3x_INT_EVTMON
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#define MXC_INT_KPP MX3x_INT_KPP
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#define MXC_INT_RTC MX3x_INT_RTC
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#define MXC_INT_PWM MX3x_INT_PWM
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#define MXC_INT_EPIT2 MX3x_INT_EPIT2
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#define MXC_INT_EPIT1 MX3x_INT_EPIT1
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#define MXC_INT_GPT MX3x_INT_GPT
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#define MXC_INT_POWER_FAIL MX3x_INT_POWER_FAIL
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#define MXC_INT_UART2 MX3x_INT_UART2
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#define MXC_INT_NANDFC MX3x_INT_NANDFC
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#define MXC_INT_SDMA MX3x_INT_SDMA
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#define MXC_INT_MSHC1 MX3x_INT_MSHC1
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#define MXC_INT_IPU_ERR MX3x_INT_IPU_ERR
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#define MXC_INT_IPU_SYN MX3x_INT_IPU_SYN
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#define MXC_INT_UART1 MX3x_INT_UART1
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#define MXC_INT_ECT MX3x_INT_ECT
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#define MXC_INT_SCC_SCM MX3x_INT_SCC_SCM
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#define MXC_INT_SCC_SMN MX3x_INT_SCC_SMN
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#define MXC_INT_GPIO2 MX3x_INT_GPIO2
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#define MXC_INT_GPIO1 MX3x_INT_GPIO1
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#define MXC_INT_WDOG MX3x_INT_WDOG
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#define MXC_INT_GPIO3 MX3x_INT_GPIO3
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#define MXC_INT_EXT_POWER MX3x_INT_EXT_POWER
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#define MXC_INT_EXT_TEMPER MX3x_INT_EXT_TEMPER
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#define MXC_INT_EXT_SENSOR60 MX3x_INT_EXT_SENSOR60
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#define MXC_INT_EXT_SENSOR61 MX3x_INT_EXT_SENSOR61
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#define MXC_INT_EXT_WDOG MX3x_INT_EXT_WDOG
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#define MXC_INT_EXT_TV MX3x_INT_EXT_TV
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#define PROD_SIGNATURE MX3x_PROD_SIGNATURE
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#define CHIP_REV_1_0 MX3x_CHIP_REV_1_0
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#define CHIP_REV_1_1 MX3x_CHIP_REV_1_1
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#define CHIP_REV_1_2 MX3x_CHIP_REV_1_2
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#define CHIP_REV_1_3 MX3x_CHIP_REV_1_3
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#define CHIP_REV_2_0 MX3x_CHIP_REV_2_0
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#define CHIP_REV_2_1 MX3x_CHIP_REV_2_1
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#define CHIP_REV_2_2 MX3x_CHIP_REV_2_2
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#define CHIP_REV_2_3 MX3x_CHIP_REV_2_3
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#define CHIP_REV_3_0 MX3x_CHIP_REV_3_0
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#define CHIP_REV_3_1 MX3x_CHIP_REV_3_1
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#define CHIP_REV_3_2 MX3x_CHIP_REV_3_2
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|
#define SYSTEM_REV_MIN MX3x_SYSTEM_REV_MIN
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|
#define SYSTEM_REV_NUM MX3x_SYSTEM_REV_NUM
|
2009-12-17 09:17:54 -07:00
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|
#endif
|
2009-11-10 13:31:30 -07:00
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|
2010-01-08 08:02:30 -07:00
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|
#endif /* ifndef __MACH_MX3x_H__ */
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