blackfin architecture
This adds support for the Analog Devices Blackfin processor architecture, and
currently supports the BF533, BF532, BF531, BF537, BF536, BF534, and BF561
(Dual Core) devices, with a variety of development platforms including those
avaliable from Analog Devices (BF533-EZKit, BF533-STAMP, BF537-STAMP,
BF561-EZKIT), and Bluetechnix! Tinyboards.
The Blackfin architecture was jointly developed by Intel and Analog Devices
Inc. (ADI) as the Micro Signal Architecture (MSA) core and introduced it in
December of 2000. Since then ADI has put this core into its Blackfin
processor family of devices. The Blackfin core has the advantages of a clean,
orthogonal,RISC-like microprocessor instruction set. It combines a dual-MAC
(Multiply/Accumulate), state-of-the-art signal processing engine and
single-instruction, multiple-data (SIMD) multimedia capabilities into a single
instruction-set architecture.
The Blackfin architecture, including the instruction set, is described by the
ADSP-BF53x/BF56x Blackfin Processor Programming Reference
http://blackfin.uclinux.org/gf/download/frsrelease/29/2549/Blackfin_PRM.pdf
The Blackfin processor is already supported by major releases of gcc, and
there are binary and source rpms/tarballs for many architectures at:
http://blackfin.uclinux.org/gf/project/toolchain/frs There is complete
documentation, including "getting started" guides available at:
http://docs.blackfin.uclinux.org/ which provides links to the sources and
patches you will need in order to set up a cross-compiling environment for
bfin-linux-uclibc
This patch, as well as the other patches (toolchain, distribution,
uClibc) are actively supported by Analog Devices Inc, at:
http://blackfin.uclinux.org/
We have tested this on LTP, and our test plan (including pass/fails) can
be found at:
http://docs.blackfin.uclinux.org/doku.php?id=testing_the_linux_kernel
[m.kozlowski@tuxland.pl: balance parenthesis in blackfin header files]
Signed-off-by: Bryan Wu <bryan.wu@analog.com>
Signed-off-by: Mariusz Kozlowski <m.kozlowski@tuxland.pl>
Signed-off-by: Aubrey Li <aubrey.li@analog.com>
Signed-off-by: Jie Zhang <jie.zhang@analog.com>
Signed-off-by: Andrew Morton <akpm@linux-foundation.org>
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
2007-05-06 15:50:22 -06:00
|
|
|
/*
|
2012-03-18 23:50:27 -06:00
|
|
|
* bfin_dma.c - Blackfin DMA implementation
|
blackfin architecture
This adds support for the Analog Devices Blackfin processor architecture, and
currently supports the BF533, BF532, BF531, BF537, BF536, BF534, and BF561
(Dual Core) devices, with a variety of development platforms including those
avaliable from Analog Devices (BF533-EZKit, BF533-STAMP, BF537-STAMP,
BF561-EZKIT), and Bluetechnix! Tinyboards.
The Blackfin architecture was jointly developed by Intel and Analog Devices
Inc. (ADI) as the Micro Signal Architecture (MSA) core and introduced it in
December of 2000. Since then ADI has put this core into its Blackfin
processor family of devices. The Blackfin core has the advantages of a clean,
orthogonal,RISC-like microprocessor instruction set. It combines a dual-MAC
(Multiply/Accumulate), state-of-the-art signal processing engine and
single-instruction, multiple-data (SIMD) multimedia capabilities into a single
instruction-set architecture.
The Blackfin architecture, including the instruction set, is described by the
ADSP-BF53x/BF56x Blackfin Processor Programming Reference
http://blackfin.uclinux.org/gf/download/frsrelease/29/2549/Blackfin_PRM.pdf
The Blackfin processor is already supported by major releases of gcc, and
there are binary and source rpms/tarballs for many architectures at:
http://blackfin.uclinux.org/gf/project/toolchain/frs There is complete
documentation, including "getting started" guides available at:
http://docs.blackfin.uclinux.org/ which provides links to the sources and
patches you will need in order to set up a cross-compiling environment for
bfin-linux-uclibc
This patch, as well as the other patches (toolchain, distribution,
uClibc) are actively supported by Analog Devices Inc, at:
http://blackfin.uclinux.org/
We have tested this on LTP, and our test plan (including pass/fails) can
be found at:
http://docs.blackfin.uclinux.org/doku.php?id=testing_the_linux_kernel
[m.kozlowski@tuxland.pl: balance parenthesis in blackfin header files]
Signed-off-by: Bryan Wu <bryan.wu@analog.com>
Signed-off-by: Mariusz Kozlowski <m.kozlowski@tuxland.pl>
Signed-off-by: Aubrey Li <aubrey.li@analog.com>
Signed-off-by: Jie Zhang <jie.zhang@analog.com>
Signed-off-by: Andrew Morton <akpm@linux-foundation.org>
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
2007-05-06 15:50:22 -06:00
|
|
|
*
|
2009-01-07 08:14:39 -07:00
|
|
|
* Copyright 2004-2008 Analog Devices Inc.
|
2009-09-24 08:11:24 -06:00
|
|
|
*
|
2009-01-07 08:14:39 -07:00
|
|
|
* Licensed under the GPL-2 or later.
|
blackfin architecture
This adds support for the Analog Devices Blackfin processor architecture, and
currently supports the BF533, BF532, BF531, BF537, BF536, BF534, and BF561
(Dual Core) devices, with a variety of development platforms including those
avaliable from Analog Devices (BF533-EZKit, BF533-STAMP, BF537-STAMP,
BF561-EZKIT), and Bluetechnix! Tinyboards.
The Blackfin architecture was jointly developed by Intel and Analog Devices
Inc. (ADI) as the Micro Signal Architecture (MSA) core and introduced it in
December of 2000. Since then ADI has put this core into its Blackfin
processor family of devices. The Blackfin core has the advantages of a clean,
orthogonal,RISC-like microprocessor instruction set. It combines a dual-MAC
(Multiply/Accumulate), state-of-the-art signal processing engine and
single-instruction, multiple-data (SIMD) multimedia capabilities into a single
instruction-set architecture.
The Blackfin architecture, including the instruction set, is described by the
ADSP-BF53x/BF56x Blackfin Processor Programming Reference
http://blackfin.uclinux.org/gf/download/frsrelease/29/2549/Blackfin_PRM.pdf
The Blackfin processor is already supported by major releases of gcc, and
there are binary and source rpms/tarballs for many architectures at:
http://blackfin.uclinux.org/gf/project/toolchain/frs There is complete
documentation, including "getting started" guides available at:
http://docs.blackfin.uclinux.org/ which provides links to the sources and
patches you will need in order to set up a cross-compiling environment for
bfin-linux-uclibc
This patch, as well as the other patches (toolchain, distribution,
uClibc) are actively supported by Analog Devices Inc, at:
http://blackfin.uclinux.org/
We have tested this on LTP, and our test plan (including pass/fails) can
be found at:
http://docs.blackfin.uclinux.org/doku.php?id=testing_the_linux_kernel
[m.kozlowski@tuxland.pl: balance parenthesis in blackfin header files]
Signed-off-by: Bryan Wu <bryan.wu@analog.com>
Signed-off-by: Mariusz Kozlowski <m.kozlowski@tuxland.pl>
Signed-off-by: Aubrey Li <aubrey.li@analog.com>
Signed-off-by: Jie Zhang <jie.zhang@analog.com>
Signed-off-by: Andrew Morton <akpm@linux-foundation.org>
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
2007-05-06 15:50:22 -06:00
|
|
|
*/
|
|
|
|
|
|
|
|
#include <linux/errno.h>
|
2009-01-07 08:14:39 -07:00
|
|
|
#include <linux/interrupt.h>
|
|
|
|
#include <linux/kernel.h>
|
blackfin architecture
This adds support for the Analog Devices Blackfin processor architecture, and
currently supports the BF533, BF532, BF531, BF537, BF536, BF534, and BF561
(Dual Core) devices, with a variety of development platforms including those
avaliable from Analog Devices (BF533-EZKit, BF533-STAMP, BF537-STAMP,
BF561-EZKIT), and Bluetechnix! Tinyboards.
The Blackfin architecture was jointly developed by Intel and Analog Devices
Inc. (ADI) as the Micro Signal Architecture (MSA) core and introduced it in
December of 2000. Since then ADI has put this core into its Blackfin
processor family of devices. The Blackfin core has the advantages of a clean,
orthogonal,RISC-like microprocessor instruction set. It combines a dual-MAC
(Multiply/Accumulate), state-of-the-art signal processing engine and
single-instruction, multiple-data (SIMD) multimedia capabilities into a single
instruction-set architecture.
The Blackfin architecture, including the instruction set, is described by the
ADSP-BF53x/BF56x Blackfin Processor Programming Reference
http://blackfin.uclinux.org/gf/download/frsrelease/29/2549/Blackfin_PRM.pdf
The Blackfin processor is already supported by major releases of gcc, and
there are binary and source rpms/tarballs for many architectures at:
http://blackfin.uclinux.org/gf/project/toolchain/frs There is complete
documentation, including "getting started" guides available at:
http://docs.blackfin.uclinux.org/ which provides links to the sources and
patches you will need in order to set up a cross-compiling environment for
bfin-linux-uclibc
This patch, as well as the other patches (toolchain, distribution,
uClibc) are actively supported by Analog Devices Inc, at:
http://blackfin.uclinux.org/
We have tested this on LTP, and our test plan (including pass/fails) can
be found at:
http://docs.blackfin.uclinux.org/doku.php?id=testing_the_linux_kernel
[m.kozlowski@tuxland.pl: balance parenthesis in blackfin header files]
Signed-off-by: Bryan Wu <bryan.wu@analog.com>
Signed-off-by: Mariusz Kozlowski <m.kozlowski@tuxland.pl>
Signed-off-by: Aubrey Li <aubrey.li@analog.com>
Signed-off-by: Jie Zhang <jie.zhang@analog.com>
Signed-off-by: Andrew Morton <akpm@linux-foundation.org>
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
2007-05-06 15:50:22 -06:00
|
|
|
#include <linux/module.h>
|
2009-01-07 08:14:39 -07:00
|
|
|
#include <linux/param.h>
|
2009-01-07 08:14:39 -07:00
|
|
|
#include <linux/proc_fs.h>
|
blackfin architecture
This adds support for the Analog Devices Blackfin processor architecture, and
currently supports the BF533, BF532, BF531, BF537, BF536, BF534, and BF561
(Dual Core) devices, with a variety of development platforms including those
avaliable from Analog Devices (BF533-EZKit, BF533-STAMP, BF537-STAMP,
BF561-EZKIT), and Bluetechnix! Tinyboards.
The Blackfin architecture was jointly developed by Intel and Analog Devices
Inc. (ADI) as the Micro Signal Architecture (MSA) core and introduced it in
December of 2000. Since then ADI has put this core into its Blackfin
processor family of devices. The Blackfin core has the advantages of a clean,
orthogonal,RISC-like microprocessor instruction set. It combines a dual-MAC
(Multiply/Accumulate), state-of-the-art signal processing engine and
single-instruction, multiple-data (SIMD) multimedia capabilities into a single
instruction-set architecture.
The Blackfin architecture, including the instruction set, is described by the
ADSP-BF53x/BF56x Blackfin Processor Programming Reference
http://blackfin.uclinux.org/gf/download/frsrelease/29/2549/Blackfin_PRM.pdf
The Blackfin processor is already supported by major releases of gcc, and
there are binary and source rpms/tarballs for many architectures at:
http://blackfin.uclinux.org/gf/project/toolchain/frs There is complete
documentation, including "getting started" guides available at:
http://docs.blackfin.uclinux.org/ which provides links to the sources and
patches you will need in order to set up a cross-compiling environment for
bfin-linux-uclibc
This patch, as well as the other patches (toolchain, distribution,
uClibc) are actively supported by Analog Devices Inc, at:
http://blackfin.uclinux.org/
We have tested this on LTP, and our test plan (including pass/fails) can
be found at:
http://docs.blackfin.uclinux.org/doku.php?id=testing_the_linux_kernel
[m.kozlowski@tuxland.pl: balance parenthesis in blackfin header files]
Signed-off-by: Bryan Wu <bryan.wu@analog.com>
Signed-off-by: Mariusz Kozlowski <m.kozlowski@tuxland.pl>
Signed-off-by: Aubrey Li <aubrey.li@analog.com>
Signed-off-by: Jie Zhang <jie.zhang@analog.com>
Signed-off-by: Andrew Morton <akpm@linux-foundation.org>
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
2007-05-06 15:50:22 -06:00
|
|
|
#include <linux/sched.h>
|
2009-01-07 08:14:39 -07:00
|
|
|
#include <linux/seq_file.h>
|
2009-01-07 08:14:39 -07:00
|
|
|
#include <linux/spinlock.h>
|
blackfin architecture
This adds support for the Analog Devices Blackfin processor architecture, and
currently supports the BF533, BF532, BF531, BF537, BF536, BF534, and BF561
(Dual Core) devices, with a variety of development platforms including those
avaliable from Analog Devices (BF533-EZKit, BF533-STAMP, BF537-STAMP,
BF561-EZKIT), and Bluetechnix! Tinyboards.
The Blackfin architecture was jointly developed by Intel and Analog Devices
Inc. (ADI) as the Micro Signal Architecture (MSA) core and introduced it in
December of 2000. Since then ADI has put this core into its Blackfin
processor family of devices. The Blackfin core has the advantages of a clean,
orthogonal,RISC-like microprocessor instruction set. It combines a dual-MAC
(Multiply/Accumulate), state-of-the-art signal processing engine and
single-instruction, multiple-data (SIMD) multimedia capabilities into a single
instruction-set architecture.
The Blackfin architecture, including the instruction set, is described by the
ADSP-BF53x/BF56x Blackfin Processor Programming Reference
http://blackfin.uclinux.org/gf/download/frsrelease/29/2549/Blackfin_PRM.pdf
The Blackfin processor is already supported by major releases of gcc, and
there are binary and source rpms/tarballs for many architectures at:
http://blackfin.uclinux.org/gf/project/toolchain/frs There is complete
documentation, including "getting started" guides available at:
http://docs.blackfin.uclinux.org/ which provides links to the sources and
patches you will need in order to set up a cross-compiling environment for
bfin-linux-uclibc
This patch, as well as the other patches (toolchain, distribution,
uClibc) are actively supported by Analog Devices Inc, at:
http://blackfin.uclinux.org/
We have tested this on LTP, and our test plan (including pass/fails) can
be found at:
http://docs.blackfin.uclinux.org/doku.php?id=testing_the_linux_kernel
[m.kozlowski@tuxland.pl: balance parenthesis in blackfin header files]
Signed-off-by: Bryan Wu <bryan.wu@analog.com>
Signed-off-by: Mariusz Kozlowski <m.kozlowski@tuxland.pl>
Signed-off-by: Aubrey Li <aubrey.li@analog.com>
Signed-off-by: Jie Zhang <jie.zhang@analog.com>
Signed-off-by: Andrew Morton <akpm@linux-foundation.org>
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
2007-05-06 15:50:22 -06:00
|
|
|
|
2007-07-12 08:41:45 -06:00
|
|
|
#include <asm/blackfin.h>
|
blackfin architecture
This adds support for the Analog Devices Blackfin processor architecture, and
currently supports the BF533, BF532, BF531, BF537, BF536, BF534, and BF561
(Dual Core) devices, with a variety of development platforms including those
avaliable from Analog Devices (BF533-EZKit, BF533-STAMP, BF537-STAMP,
BF561-EZKIT), and Bluetechnix! Tinyboards.
The Blackfin architecture was jointly developed by Intel and Analog Devices
Inc. (ADI) as the Micro Signal Architecture (MSA) core and introduced it in
December of 2000. Since then ADI has put this core into its Blackfin
processor family of devices. The Blackfin core has the advantages of a clean,
orthogonal,RISC-like microprocessor instruction set. It combines a dual-MAC
(Multiply/Accumulate), state-of-the-art signal processing engine and
single-instruction, multiple-data (SIMD) multimedia capabilities into a single
instruction-set architecture.
The Blackfin architecture, including the instruction set, is described by the
ADSP-BF53x/BF56x Blackfin Processor Programming Reference
http://blackfin.uclinux.org/gf/download/frsrelease/29/2549/Blackfin_PRM.pdf
The Blackfin processor is already supported by major releases of gcc, and
there are binary and source rpms/tarballs for many architectures at:
http://blackfin.uclinux.org/gf/project/toolchain/frs There is complete
documentation, including "getting started" guides available at:
http://docs.blackfin.uclinux.org/ which provides links to the sources and
patches you will need in order to set up a cross-compiling environment for
bfin-linux-uclibc
This patch, as well as the other patches (toolchain, distribution,
uClibc) are actively supported by Analog Devices Inc, at:
http://blackfin.uclinux.org/
We have tested this on LTP, and our test plan (including pass/fails) can
be found at:
http://docs.blackfin.uclinux.org/doku.php?id=testing_the_linux_kernel
[m.kozlowski@tuxland.pl: balance parenthesis in blackfin header files]
Signed-off-by: Bryan Wu <bryan.wu@analog.com>
Signed-off-by: Mariusz Kozlowski <m.kozlowski@tuxland.pl>
Signed-off-by: Aubrey Li <aubrey.li@analog.com>
Signed-off-by: Jie Zhang <jie.zhang@analog.com>
Signed-off-by: Andrew Morton <akpm@linux-foundation.org>
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
2007-05-06 15:50:22 -06:00
|
|
|
#include <asm/cacheflush.h>
|
2009-01-07 08:14:39 -07:00
|
|
|
#include <asm/dma.h>
|
|
|
|
#include <asm/uaccess.h>
|
2009-07-07 14:17:09 -06:00
|
|
|
#include <asm/early_printk.h>
|
blackfin architecture
This adds support for the Analog Devices Blackfin processor architecture, and
currently supports the BF533, BF532, BF531, BF537, BF536, BF534, and BF561
(Dual Core) devices, with a variety of development platforms including those
avaliable from Analog Devices (BF533-EZKit, BF533-STAMP, BF537-STAMP,
BF561-EZKIT), and Bluetechnix! Tinyboards.
The Blackfin architecture was jointly developed by Intel and Analog Devices
Inc. (ADI) as the Micro Signal Architecture (MSA) core and introduced it in
December of 2000. Since then ADI has put this core into its Blackfin
processor family of devices. The Blackfin core has the advantages of a clean,
orthogonal,RISC-like microprocessor instruction set. It combines a dual-MAC
(Multiply/Accumulate), state-of-the-art signal processing engine and
single-instruction, multiple-data (SIMD) multimedia capabilities into a single
instruction-set architecture.
The Blackfin architecture, including the instruction set, is described by the
ADSP-BF53x/BF56x Blackfin Processor Programming Reference
http://blackfin.uclinux.org/gf/download/frsrelease/29/2549/Blackfin_PRM.pdf
The Blackfin processor is already supported by major releases of gcc, and
there are binary and source rpms/tarballs for many architectures at:
http://blackfin.uclinux.org/gf/project/toolchain/frs There is complete
documentation, including "getting started" guides available at:
http://docs.blackfin.uclinux.org/ which provides links to the sources and
patches you will need in order to set up a cross-compiling environment for
bfin-linux-uclibc
This patch, as well as the other patches (toolchain, distribution,
uClibc) are actively supported by Analog Devices Inc, at:
http://blackfin.uclinux.org/
We have tested this on LTP, and our test plan (including pass/fails) can
be found at:
http://docs.blackfin.uclinux.org/doku.php?id=testing_the_linux_kernel
[m.kozlowski@tuxland.pl: balance parenthesis in blackfin header files]
Signed-off-by: Bryan Wu <bryan.wu@analog.com>
Signed-off-by: Mariusz Kozlowski <m.kozlowski@tuxland.pl>
Signed-off-by: Aubrey Li <aubrey.li@analog.com>
Signed-off-by: Jie Zhang <jie.zhang@analog.com>
Signed-off-by: Andrew Morton <akpm@linux-foundation.org>
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
2007-05-06 15:50:22 -06:00
|
|
|
|
2009-04-23 14:56:42 -06:00
|
|
|
/*
|
|
|
|
* To make sure we work around 05000119 - we always check DMA_DONE bit,
|
|
|
|
* never the DMA_RUN bit
|
|
|
|
*/
|
|
|
|
|
2009-01-07 08:14:39 -07:00
|
|
|
struct dma_channel dma_ch[MAX_DMA_CHANNELS];
|
|
|
|
EXPORT_SYMBOL(dma_ch);
|
blackfin architecture
This adds support for the Analog Devices Blackfin processor architecture, and
currently supports the BF533, BF532, BF531, BF537, BF536, BF534, and BF561
(Dual Core) devices, with a variety of development platforms including those
avaliable from Analog Devices (BF533-EZKit, BF533-STAMP, BF537-STAMP,
BF561-EZKIT), and Bluetechnix! Tinyboards.
The Blackfin architecture was jointly developed by Intel and Analog Devices
Inc. (ADI) as the Micro Signal Architecture (MSA) core and introduced it in
December of 2000. Since then ADI has put this core into its Blackfin
processor family of devices. The Blackfin core has the advantages of a clean,
orthogonal,RISC-like microprocessor instruction set. It combines a dual-MAC
(Multiply/Accumulate), state-of-the-art signal processing engine and
single-instruction, multiple-data (SIMD) multimedia capabilities into a single
instruction-set architecture.
The Blackfin architecture, including the instruction set, is described by the
ADSP-BF53x/BF56x Blackfin Processor Programming Reference
http://blackfin.uclinux.org/gf/download/frsrelease/29/2549/Blackfin_PRM.pdf
The Blackfin processor is already supported by major releases of gcc, and
there are binary and source rpms/tarballs for many architectures at:
http://blackfin.uclinux.org/gf/project/toolchain/frs There is complete
documentation, including "getting started" guides available at:
http://docs.blackfin.uclinux.org/ which provides links to the sources and
patches you will need in order to set up a cross-compiling environment for
bfin-linux-uclibc
This patch, as well as the other patches (toolchain, distribution,
uClibc) are actively supported by Analog Devices Inc, at:
http://blackfin.uclinux.org/
We have tested this on LTP, and our test plan (including pass/fails) can
be found at:
http://docs.blackfin.uclinux.org/doku.php?id=testing_the_linux_kernel
[m.kozlowski@tuxland.pl: balance parenthesis in blackfin header files]
Signed-off-by: Bryan Wu <bryan.wu@analog.com>
Signed-off-by: Mariusz Kozlowski <m.kozlowski@tuxland.pl>
Signed-off-by: Aubrey Li <aubrey.li@analog.com>
Signed-off-by: Jie Zhang <jie.zhang@analog.com>
Signed-off-by: Andrew Morton <akpm@linux-foundation.org>
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
2007-05-06 15:50:22 -06:00
|
|
|
|
2007-05-21 04:09:14 -06:00
|
|
|
static int __init blackfin_dma_init(void)
|
blackfin architecture
This adds support for the Analog Devices Blackfin processor architecture, and
currently supports the BF533, BF532, BF531, BF537, BF536, BF534, and BF561
(Dual Core) devices, with a variety of development platforms including those
avaliable from Analog Devices (BF533-EZKit, BF533-STAMP, BF537-STAMP,
BF561-EZKIT), and Bluetechnix! Tinyboards.
The Blackfin architecture was jointly developed by Intel and Analog Devices
Inc. (ADI) as the Micro Signal Architecture (MSA) core and introduced it in
December of 2000. Since then ADI has put this core into its Blackfin
processor family of devices. The Blackfin core has the advantages of a clean,
orthogonal,RISC-like microprocessor instruction set. It combines a dual-MAC
(Multiply/Accumulate), state-of-the-art signal processing engine and
single-instruction, multiple-data (SIMD) multimedia capabilities into a single
instruction-set architecture.
The Blackfin architecture, including the instruction set, is described by the
ADSP-BF53x/BF56x Blackfin Processor Programming Reference
http://blackfin.uclinux.org/gf/download/frsrelease/29/2549/Blackfin_PRM.pdf
The Blackfin processor is already supported by major releases of gcc, and
there are binary and source rpms/tarballs for many architectures at:
http://blackfin.uclinux.org/gf/project/toolchain/frs There is complete
documentation, including "getting started" guides available at:
http://docs.blackfin.uclinux.org/ which provides links to the sources and
patches you will need in order to set up a cross-compiling environment for
bfin-linux-uclibc
This patch, as well as the other patches (toolchain, distribution,
uClibc) are actively supported by Analog Devices Inc, at:
http://blackfin.uclinux.org/
We have tested this on LTP, and our test plan (including pass/fails) can
be found at:
http://docs.blackfin.uclinux.org/doku.php?id=testing_the_linux_kernel
[m.kozlowski@tuxland.pl: balance parenthesis in blackfin header files]
Signed-off-by: Bryan Wu <bryan.wu@analog.com>
Signed-off-by: Mariusz Kozlowski <m.kozlowski@tuxland.pl>
Signed-off-by: Aubrey Li <aubrey.li@analog.com>
Signed-off-by: Jie Zhang <jie.zhang@analog.com>
Signed-off-by: Andrew Morton <akpm@linux-foundation.org>
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
2007-05-06 15:50:22 -06:00
|
|
|
{
|
|
|
|
int i;
|
|
|
|
|
|
|
|
printk(KERN_INFO "Blackfin DMA Controller\n");
|
|
|
|
|
2011-05-05 00:14:48 -06:00
|
|
|
|
|
|
|
#if ANOMALY_05000480
|
|
|
|
bfin_write_DMAC_TC_PER(0x0111);
|
|
|
|
#endif
|
|
|
|
|
2009-01-07 08:14:39 -07:00
|
|
|
for (i = 0; i < MAX_DMA_CHANNELS; i++) {
|
2009-10-09 16:18:12 -06:00
|
|
|
atomic_set(&dma_ch[i].chan_status, 0);
|
2008-04-23 15:31:18 -06:00
|
|
|
dma_ch[i].regs = dma_io_base_addr[i];
|
blackfin architecture
This adds support for the Analog Devices Blackfin processor architecture, and
currently supports the BF533, BF532, BF531, BF537, BF536, BF534, and BF561
(Dual Core) devices, with a variety of development platforms including those
avaliable from Analog Devices (BF533-EZKit, BF533-STAMP, BF537-STAMP,
BF561-EZKIT), and Bluetechnix! Tinyboards.
The Blackfin architecture was jointly developed by Intel and Analog Devices
Inc. (ADI) as the Micro Signal Architecture (MSA) core and introduced it in
December of 2000. Since then ADI has put this core into its Blackfin
processor family of devices. The Blackfin core has the advantages of a clean,
orthogonal,RISC-like microprocessor instruction set. It combines a dual-MAC
(Multiply/Accumulate), state-of-the-art signal processing engine and
single-instruction, multiple-data (SIMD) multimedia capabilities into a single
instruction-set architecture.
The Blackfin architecture, including the instruction set, is described by the
ADSP-BF53x/BF56x Blackfin Processor Programming Reference
http://blackfin.uclinux.org/gf/download/frsrelease/29/2549/Blackfin_PRM.pdf
The Blackfin processor is already supported by major releases of gcc, and
there are binary and source rpms/tarballs for many architectures at:
http://blackfin.uclinux.org/gf/project/toolchain/frs There is complete
documentation, including "getting started" guides available at:
http://docs.blackfin.uclinux.org/ which provides links to the sources and
patches you will need in order to set up a cross-compiling environment for
bfin-linux-uclibc
This patch, as well as the other patches (toolchain, distribution,
uClibc) are actively supported by Analog Devices Inc, at:
http://blackfin.uclinux.org/
We have tested this on LTP, and our test plan (including pass/fails) can
be found at:
http://docs.blackfin.uclinux.org/doku.php?id=testing_the_linux_kernel
[m.kozlowski@tuxland.pl: balance parenthesis in blackfin header files]
Signed-off-by: Bryan Wu <bryan.wu@analog.com>
Signed-off-by: Mariusz Kozlowski <m.kozlowski@tuxland.pl>
Signed-off-by: Aubrey Li <aubrey.li@analog.com>
Signed-off-by: Jie Zhang <jie.zhang@analog.com>
Signed-off-by: Andrew Morton <akpm@linux-foundation.org>
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
2007-05-06 15:50:22 -06:00
|
|
|
}
|
2012-05-24 21:32:03 -06:00
|
|
|
#if defined(CH_MEM_STREAM3_SRC) && defined(CONFIG_BF60x)
|
2012-05-16 03:37:24 -06:00
|
|
|
/* Mark MEMDMA Channel 3 as requested since we're using it internally */
|
|
|
|
request_dma(CH_MEM_STREAM3_DEST, "Blackfin dma_memcpy");
|
|
|
|
request_dma(CH_MEM_STREAM3_SRC, "Blackfin dma_memcpy");
|
|
|
|
#else
|
2007-05-21 04:09:17 -06:00
|
|
|
/* Mark MEMDMA Channel 0 as requested since we're using it internally */
|
2009-01-07 08:14:39 -07:00
|
|
|
request_dma(CH_MEM_STREAM0_DEST, "Blackfin dma_memcpy");
|
|
|
|
request_dma(CH_MEM_STREAM0_SRC, "Blackfin dma_memcpy");
|
2012-05-16 03:37:24 -06:00
|
|
|
#endif
|
2007-08-03 03:43:29 -06:00
|
|
|
|
|
|
|
#if defined(CONFIG_DEB_DMA_URGENT)
|
|
|
|
bfin_write_EBIU_DDRQUE(bfin_read_EBIU_DDRQUE()
|
|
|
|
| DEB1_URGENT | DEB2_URGENT | DEB3_URGENT);
|
|
|
|
#endif
|
2009-01-07 08:14:39 -07:00
|
|
|
|
blackfin architecture
This adds support for the Analog Devices Blackfin processor architecture, and
currently supports the BF533, BF532, BF531, BF537, BF536, BF534, and BF561
(Dual Core) devices, with a variety of development platforms including those
avaliable from Analog Devices (BF533-EZKit, BF533-STAMP, BF537-STAMP,
BF561-EZKIT), and Bluetechnix! Tinyboards.
The Blackfin architecture was jointly developed by Intel and Analog Devices
Inc. (ADI) as the Micro Signal Architecture (MSA) core and introduced it in
December of 2000. Since then ADI has put this core into its Blackfin
processor family of devices. The Blackfin core has the advantages of a clean,
orthogonal,RISC-like microprocessor instruction set. It combines a dual-MAC
(Multiply/Accumulate), state-of-the-art signal processing engine and
single-instruction, multiple-data (SIMD) multimedia capabilities into a single
instruction-set architecture.
The Blackfin architecture, including the instruction set, is described by the
ADSP-BF53x/BF56x Blackfin Processor Programming Reference
http://blackfin.uclinux.org/gf/download/frsrelease/29/2549/Blackfin_PRM.pdf
The Blackfin processor is already supported by major releases of gcc, and
there are binary and source rpms/tarballs for many architectures at:
http://blackfin.uclinux.org/gf/project/toolchain/frs There is complete
documentation, including "getting started" guides available at:
http://docs.blackfin.uclinux.org/ which provides links to the sources and
patches you will need in order to set up a cross-compiling environment for
bfin-linux-uclibc
This patch, as well as the other patches (toolchain, distribution,
uClibc) are actively supported by Analog Devices Inc, at:
http://blackfin.uclinux.org/
We have tested this on LTP, and our test plan (including pass/fails) can
be found at:
http://docs.blackfin.uclinux.org/doku.php?id=testing_the_linux_kernel
[m.kozlowski@tuxland.pl: balance parenthesis in blackfin header files]
Signed-off-by: Bryan Wu <bryan.wu@analog.com>
Signed-off-by: Mariusz Kozlowski <m.kozlowski@tuxland.pl>
Signed-off-by: Aubrey Li <aubrey.li@analog.com>
Signed-off-by: Jie Zhang <jie.zhang@analog.com>
Signed-off-by: Andrew Morton <akpm@linux-foundation.org>
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
2007-05-06 15:50:22 -06:00
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
arch_initcall(blackfin_dma_init);
|
|
|
|
|
2009-01-07 08:14:39 -07:00
|
|
|
#ifdef CONFIG_PROC_FS
|
|
|
|
static int proc_dma_show(struct seq_file *m, void *v)
|
|
|
|
{
|
|
|
|
int i;
|
|
|
|
|
2009-01-07 08:14:39 -07:00
|
|
|
for (i = 0; i < MAX_DMA_CHANNELS; ++i)
|
2009-10-09 16:18:12 -06:00
|
|
|
if (dma_channel_active(i))
|
2009-01-07 08:14:39 -07:00
|
|
|
seq_printf(m, "%2d: %s\n", i, dma_ch[i].device_id);
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int proc_dma_open(struct inode *inode, struct file *file)
|
|
|
|
{
|
|
|
|
return single_open(file, proc_dma_show, NULL);
|
|
|
|
}
|
|
|
|
|
|
|
|
static const struct file_operations proc_dma_operations = {
|
|
|
|
.open = proc_dma_open,
|
|
|
|
.read = seq_read,
|
|
|
|
.llseek = seq_lseek,
|
|
|
|
.release = single_release,
|
|
|
|
};
|
|
|
|
|
|
|
|
static int __init proc_dma_init(void)
|
|
|
|
{
|
2012-05-03 01:40:26 -06:00
|
|
|
proc_create("dma", 0, NULL, &proc_dma_operations);
|
|
|
|
return 0;
|
2009-01-07 08:14:39 -07:00
|
|
|
}
|
|
|
|
late_initcall(proc_dma_init);
|
|
|
|
#endif
|
|
|
|
|
2010-10-22 02:48:41 -06:00
|
|
|
static void set_dma_peripheral_map(unsigned int channel, const char *device_id)
|
|
|
|
{
|
|
|
|
#ifdef CONFIG_BF54x
|
|
|
|
unsigned int per_map;
|
|
|
|
|
|
|
|
switch (channel) {
|
|
|
|
case CH_UART2_RX: per_map = 0xC << 12; break;
|
|
|
|
case CH_UART2_TX: per_map = 0xD << 12; break;
|
|
|
|
case CH_UART3_RX: per_map = 0xE << 12; break;
|
|
|
|
case CH_UART3_TX: per_map = 0xF << 12; break;
|
|
|
|
default: return;
|
|
|
|
}
|
|
|
|
|
|
|
|
if (strncmp(device_id, "BFIN_UART", 9) == 0)
|
|
|
|
dma_ch[channel].regs->peripheral_map = per_map;
|
|
|
|
#endif
|
|
|
|
}
|
|
|
|
|
2009-01-07 08:14:39 -07:00
|
|
|
/**
|
|
|
|
* request_dma - request a DMA channel
|
|
|
|
*
|
|
|
|
* Request the specific DMA channel from the system if it's available.
|
|
|
|
*/
|
2009-01-07 08:14:38 -07:00
|
|
|
int request_dma(unsigned int channel, const char *device_id)
|
blackfin architecture
This adds support for the Analog Devices Blackfin processor architecture, and
currently supports the BF533, BF532, BF531, BF537, BF536, BF534, and BF561
(Dual Core) devices, with a variety of development platforms including those
avaliable from Analog Devices (BF533-EZKit, BF533-STAMP, BF537-STAMP,
BF561-EZKIT), and Bluetechnix! Tinyboards.
The Blackfin architecture was jointly developed by Intel and Analog Devices
Inc. (ADI) as the Micro Signal Architecture (MSA) core and introduced it in
December of 2000. Since then ADI has put this core into its Blackfin
processor family of devices. The Blackfin core has the advantages of a clean,
orthogonal,RISC-like microprocessor instruction set. It combines a dual-MAC
(Multiply/Accumulate), state-of-the-art signal processing engine and
single-instruction, multiple-data (SIMD) multimedia capabilities into a single
instruction-set architecture.
The Blackfin architecture, including the instruction set, is described by the
ADSP-BF53x/BF56x Blackfin Processor Programming Reference
http://blackfin.uclinux.org/gf/download/frsrelease/29/2549/Blackfin_PRM.pdf
The Blackfin processor is already supported by major releases of gcc, and
there are binary and source rpms/tarballs for many architectures at:
http://blackfin.uclinux.org/gf/project/toolchain/frs There is complete
documentation, including "getting started" guides available at:
http://docs.blackfin.uclinux.org/ which provides links to the sources and
patches you will need in order to set up a cross-compiling environment for
bfin-linux-uclibc
This patch, as well as the other patches (toolchain, distribution,
uClibc) are actively supported by Analog Devices Inc, at:
http://blackfin.uclinux.org/
We have tested this on LTP, and our test plan (including pass/fails) can
be found at:
http://docs.blackfin.uclinux.org/doku.php?id=testing_the_linux_kernel
[m.kozlowski@tuxland.pl: balance parenthesis in blackfin header files]
Signed-off-by: Bryan Wu <bryan.wu@analog.com>
Signed-off-by: Mariusz Kozlowski <m.kozlowski@tuxland.pl>
Signed-off-by: Aubrey Li <aubrey.li@analog.com>
Signed-off-by: Jie Zhang <jie.zhang@analog.com>
Signed-off-by: Andrew Morton <akpm@linux-foundation.org>
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
2007-05-06 15:50:22 -06:00
|
|
|
{
|
2010-02-06 10:47:18 -07:00
|
|
|
pr_debug("request_dma() : BEGIN\n");
|
2009-01-07 08:14:39 -07:00
|
|
|
|
|
|
|
if (device_id == NULL)
|
|
|
|
printk(KERN_WARNING "request_dma(%u): no device_id given\n", channel);
|
2008-05-17 01:57:01 -06:00
|
|
|
|
|
|
|
#if defined(CONFIG_BF561) && ANOMALY_05000182
|
|
|
|
if (channel >= CH_IMEM_STREAM0_DEST && channel <= CH_IMEM_STREAM1_DEST) {
|
|
|
|
if (get_cclk() > 500000000) {
|
|
|
|
printk(KERN_WARNING
|
|
|
|
"Request IMDMA failed due to ANOMALY 05000182\n");
|
|
|
|
return -EFAULT;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
#endif
|
|
|
|
|
2009-10-09 16:18:12 -06:00
|
|
|
if (atomic_cmpxchg(&dma_ch[channel].chan_status, 0, 1)) {
|
2010-02-06 10:47:18 -07:00
|
|
|
pr_debug("DMA CHANNEL IN USE\n");
|
blackfin architecture
This adds support for the Analog Devices Blackfin processor architecture, and
currently supports the BF533, BF532, BF531, BF537, BF536, BF534, and BF561
(Dual Core) devices, with a variety of development platforms including those
avaliable from Analog Devices (BF533-EZKit, BF533-STAMP, BF537-STAMP,
BF561-EZKIT), and Bluetechnix! Tinyboards.
The Blackfin architecture was jointly developed by Intel and Analog Devices
Inc. (ADI) as the Micro Signal Architecture (MSA) core and introduced it in
December of 2000. Since then ADI has put this core into its Blackfin
processor family of devices. The Blackfin core has the advantages of a clean,
orthogonal,RISC-like microprocessor instruction set. It combines a dual-MAC
(Multiply/Accumulate), state-of-the-art signal processing engine and
single-instruction, multiple-data (SIMD) multimedia capabilities into a single
instruction-set architecture.
The Blackfin architecture, including the instruction set, is described by the
ADSP-BF53x/BF56x Blackfin Processor Programming Reference
http://blackfin.uclinux.org/gf/download/frsrelease/29/2549/Blackfin_PRM.pdf
The Blackfin processor is already supported by major releases of gcc, and
there are binary and source rpms/tarballs for many architectures at:
http://blackfin.uclinux.org/gf/project/toolchain/frs There is complete
documentation, including "getting started" guides available at:
http://docs.blackfin.uclinux.org/ which provides links to the sources and
patches you will need in order to set up a cross-compiling environment for
bfin-linux-uclibc
This patch, as well as the other patches (toolchain, distribution,
uClibc) are actively supported by Analog Devices Inc, at:
http://blackfin.uclinux.org/
We have tested this on LTP, and our test plan (including pass/fails) can
be found at:
http://docs.blackfin.uclinux.org/doku.php?id=testing_the_linux_kernel
[m.kozlowski@tuxland.pl: balance parenthesis in blackfin header files]
Signed-off-by: Bryan Wu <bryan.wu@analog.com>
Signed-off-by: Mariusz Kozlowski <m.kozlowski@tuxland.pl>
Signed-off-by: Aubrey Li <aubrey.li@analog.com>
Signed-off-by: Jie Zhang <jie.zhang@analog.com>
Signed-off-by: Andrew Morton <akpm@linux-foundation.org>
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
2007-05-06 15:50:22 -06:00
|
|
|
return -EBUSY;
|
|
|
|
}
|
|
|
|
|
2010-10-22 02:48:41 -06:00
|
|
|
set_dma_peripheral_map(channel, device_id);
|
blackfin architecture
This adds support for the Analog Devices Blackfin processor architecture, and
currently supports the BF533, BF532, BF531, BF537, BF536, BF534, and BF561
(Dual Core) devices, with a variety of development platforms including those
avaliable from Analog Devices (BF533-EZKit, BF533-STAMP, BF537-STAMP,
BF561-EZKIT), and Bluetechnix! Tinyboards.
The Blackfin architecture was jointly developed by Intel and Analog Devices
Inc. (ADI) as the Micro Signal Architecture (MSA) core and introduced it in
December of 2000. Since then ADI has put this core into its Blackfin
processor family of devices. The Blackfin core has the advantages of a clean,
orthogonal,RISC-like microprocessor instruction set. It combines a dual-MAC
(Multiply/Accumulate), state-of-the-art signal processing engine and
single-instruction, multiple-data (SIMD) multimedia capabilities into a single
instruction-set architecture.
The Blackfin architecture, including the instruction set, is described by the
ADSP-BF53x/BF56x Blackfin Processor Programming Reference
http://blackfin.uclinux.org/gf/download/frsrelease/29/2549/Blackfin_PRM.pdf
The Blackfin processor is already supported by major releases of gcc, and
there are binary and source rpms/tarballs for many architectures at:
http://blackfin.uclinux.org/gf/project/toolchain/frs There is complete
documentation, including "getting started" guides available at:
http://docs.blackfin.uclinux.org/ which provides links to the sources and
patches you will need in order to set up a cross-compiling environment for
bfin-linux-uclibc
This patch, as well as the other patches (toolchain, distribution,
uClibc) are actively supported by Analog Devices Inc, at:
http://blackfin.uclinux.org/
We have tested this on LTP, and our test plan (including pass/fails) can
be found at:
http://docs.blackfin.uclinux.org/doku.php?id=testing_the_linux_kernel
[m.kozlowski@tuxland.pl: balance parenthesis in blackfin header files]
Signed-off-by: Bryan Wu <bryan.wu@analog.com>
Signed-off-by: Mariusz Kozlowski <m.kozlowski@tuxland.pl>
Signed-off-by: Aubrey Li <aubrey.li@analog.com>
Signed-off-by: Jie Zhang <jie.zhang@analog.com>
Signed-off-by: Andrew Morton <akpm@linux-foundation.org>
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
2007-05-06 15:50:22 -06:00
|
|
|
dma_ch[channel].device_id = device_id;
|
2009-01-07 08:14:38 -07:00
|
|
|
dma_ch[channel].irq = 0;
|
blackfin architecture
This adds support for the Analog Devices Blackfin processor architecture, and
currently supports the BF533, BF532, BF531, BF537, BF536, BF534, and BF561
(Dual Core) devices, with a variety of development platforms including those
avaliable from Analog Devices (BF533-EZKit, BF533-STAMP, BF537-STAMP,
BF561-EZKIT), and Bluetechnix! Tinyboards.
The Blackfin architecture was jointly developed by Intel and Analog Devices
Inc. (ADI) as the Micro Signal Architecture (MSA) core and introduced it in
December of 2000. Since then ADI has put this core into its Blackfin
processor family of devices. The Blackfin core has the advantages of a clean,
orthogonal,RISC-like microprocessor instruction set. It combines a dual-MAC
(Multiply/Accumulate), state-of-the-art signal processing engine and
single-instruction, multiple-data (SIMD) multimedia capabilities into a single
instruction-set architecture.
The Blackfin architecture, including the instruction set, is described by the
ADSP-BF53x/BF56x Blackfin Processor Programming Reference
http://blackfin.uclinux.org/gf/download/frsrelease/29/2549/Blackfin_PRM.pdf
The Blackfin processor is already supported by major releases of gcc, and
there are binary and source rpms/tarballs for many architectures at:
http://blackfin.uclinux.org/gf/project/toolchain/frs There is complete
documentation, including "getting started" guides available at:
http://docs.blackfin.uclinux.org/ which provides links to the sources and
patches you will need in order to set up a cross-compiling environment for
bfin-linux-uclibc
This patch, as well as the other patches (toolchain, distribution,
uClibc) are actively supported by Analog Devices Inc, at:
http://blackfin.uclinux.org/
We have tested this on LTP, and our test plan (including pass/fails) can
be found at:
http://docs.blackfin.uclinux.org/doku.php?id=testing_the_linux_kernel
[m.kozlowski@tuxland.pl: balance parenthesis in blackfin header files]
Signed-off-by: Bryan Wu <bryan.wu@analog.com>
Signed-off-by: Mariusz Kozlowski <m.kozlowski@tuxland.pl>
Signed-off-by: Aubrey Li <aubrey.li@analog.com>
Signed-off-by: Jie Zhang <jie.zhang@analog.com>
Signed-off-by: Andrew Morton <akpm@linux-foundation.org>
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
2007-05-06 15:50:22 -06:00
|
|
|
|
|
|
|
/* This is to be enabled by putting a restriction -
|
|
|
|
* you have to request DMA, before doing any operations on
|
|
|
|
* descriptor/channel
|
|
|
|
*/
|
2010-02-06 10:47:18 -07:00
|
|
|
pr_debug("request_dma() : END\n");
|
2009-01-07 08:14:39 -07:00
|
|
|
return 0;
|
blackfin architecture
This adds support for the Analog Devices Blackfin processor architecture, and
currently supports the BF533, BF532, BF531, BF537, BF536, BF534, and BF561
(Dual Core) devices, with a variety of development platforms including those
avaliable from Analog Devices (BF533-EZKit, BF533-STAMP, BF537-STAMP,
BF561-EZKIT), and Bluetechnix! Tinyboards.
The Blackfin architecture was jointly developed by Intel and Analog Devices
Inc. (ADI) as the Micro Signal Architecture (MSA) core and introduced it in
December of 2000. Since then ADI has put this core into its Blackfin
processor family of devices. The Blackfin core has the advantages of a clean,
orthogonal,RISC-like microprocessor instruction set. It combines a dual-MAC
(Multiply/Accumulate), state-of-the-art signal processing engine and
single-instruction, multiple-data (SIMD) multimedia capabilities into a single
instruction-set architecture.
The Blackfin architecture, including the instruction set, is described by the
ADSP-BF53x/BF56x Blackfin Processor Programming Reference
http://blackfin.uclinux.org/gf/download/frsrelease/29/2549/Blackfin_PRM.pdf
The Blackfin processor is already supported by major releases of gcc, and
there are binary and source rpms/tarballs for many architectures at:
http://blackfin.uclinux.org/gf/project/toolchain/frs There is complete
documentation, including "getting started" guides available at:
http://docs.blackfin.uclinux.org/ which provides links to the sources and
patches you will need in order to set up a cross-compiling environment for
bfin-linux-uclibc
This patch, as well as the other patches (toolchain, distribution,
uClibc) are actively supported by Analog Devices Inc, at:
http://blackfin.uclinux.org/
We have tested this on LTP, and our test plan (including pass/fails) can
be found at:
http://docs.blackfin.uclinux.org/doku.php?id=testing_the_linux_kernel
[m.kozlowski@tuxland.pl: balance parenthesis in blackfin header files]
Signed-off-by: Bryan Wu <bryan.wu@analog.com>
Signed-off-by: Mariusz Kozlowski <m.kozlowski@tuxland.pl>
Signed-off-by: Aubrey Li <aubrey.li@analog.com>
Signed-off-by: Jie Zhang <jie.zhang@analog.com>
Signed-off-by: Andrew Morton <akpm@linux-foundation.org>
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
2007-05-06 15:50:22 -06:00
|
|
|
}
|
|
|
|
EXPORT_SYMBOL(request_dma);
|
|
|
|
|
2009-01-07 08:14:38 -07:00
|
|
|
int set_dma_callback(unsigned int channel, irq_handler_t callback, void *data)
|
blackfin architecture
This adds support for the Analog Devices Blackfin processor architecture, and
currently supports the BF533, BF532, BF531, BF537, BF536, BF534, and BF561
(Dual Core) devices, with a variety of development platforms including those
avaliable from Analog Devices (BF533-EZKit, BF533-STAMP, BF537-STAMP,
BF561-EZKIT), and Bluetechnix! Tinyboards.
The Blackfin architecture was jointly developed by Intel and Analog Devices
Inc. (ADI) as the Micro Signal Architecture (MSA) core and introduced it in
December of 2000. Since then ADI has put this core into its Blackfin
processor family of devices. The Blackfin core has the advantages of a clean,
orthogonal,RISC-like microprocessor instruction set. It combines a dual-MAC
(Multiply/Accumulate), state-of-the-art signal processing engine and
single-instruction, multiple-data (SIMD) multimedia capabilities into a single
instruction-set architecture.
The Blackfin architecture, including the instruction set, is described by the
ADSP-BF53x/BF56x Blackfin Processor Programming Reference
http://blackfin.uclinux.org/gf/download/frsrelease/29/2549/Blackfin_PRM.pdf
The Blackfin processor is already supported by major releases of gcc, and
there are binary and source rpms/tarballs for many architectures at:
http://blackfin.uclinux.org/gf/project/toolchain/frs There is complete
documentation, including "getting started" guides available at:
http://docs.blackfin.uclinux.org/ which provides links to the sources and
patches you will need in order to set up a cross-compiling environment for
bfin-linux-uclibc
This patch, as well as the other patches (toolchain, distribution,
uClibc) are actively supported by Analog Devices Inc, at:
http://blackfin.uclinux.org/
We have tested this on LTP, and our test plan (including pass/fails) can
be found at:
http://docs.blackfin.uclinux.org/doku.php?id=testing_the_linux_kernel
[m.kozlowski@tuxland.pl: balance parenthesis in blackfin header files]
Signed-off-by: Bryan Wu <bryan.wu@analog.com>
Signed-off-by: Mariusz Kozlowski <m.kozlowski@tuxland.pl>
Signed-off-by: Aubrey Li <aubrey.li@analog.com>
Signed-off-by: Jie Zhang <jie.zhang@analog.com>
Signed-off-by: Andrew Morton <akpm@linux-foundation.org>
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
2007-05-06 15:50:22 -06:00
|
|
|
{
|
2009-11-24 11:36:36 -07:00
|
|
|
int ret;
|
|
|
|
unsigned int irq;
|
|
|
|
|
|
|
|
BUG_ON(channel >= MAX_DMA_CHANNELS || !callback ||
|
2009-10-09 16:18:12 -06:00
|
|
|
!atomic_read(&dma_ch[channel].chan_status));
|
blackfin architecture
This adds support for the Analog Devices Blackfin processor architecture, and
currently supports the BF533, BF532, BF531, BF537, BF536, BF534, and BF561
(Dual Core) devices, with a variety of development platforms including those
avaliable from Analog Devices (BF533-EZKit, BF533-STAMP, BF537-STAMP,
BF561-EZKIT), and Bluetechnix! Tinyboards.
The Blackfin architecture was jointly developed by Intel and Analog Devices
Inc. (ADI) as the Micro Signal Architecture (MSA) core and introduced it in
December of 2000. Since then ADI has put this core into its Blackfin
processor family of devices. The Blackfin core has the advantages of a clean,
orthogonal,RISC-like microprocessor instruction set. It combines a dual-MAC
(Multiply/Accumulate), state-of-the-art signal processing engine and
single-instruction, multiple-data (SIMD) multimedia capabilities into a single
instruction-set architecture.
The Blackfin architecture, including the instruction set, is described by the
ADSP-BF53x/BF56x Blackfin Processor Programming Reference
http://blackfin.uclinux.org/gf/download/frsrelease/29/2549/Blackfin_PRM.pdf
The Blackfin processor is already supported by major releases of gcc, and
there are binary and source rpms/tarballs for many architectures at:
http://blackfin.uclinux.org/gf/project/toolchain/frs There is complete
documentation, including "getting started" guides available at:
http://docs.blackfin.uclinux.org/ which provides links to the sources and
patches you will need in order to set up a cross-compiling environment for
bfin-linux-uclibc
This patch, as well as the other patches (toolchain, distribution,
uClibc) are actively supported by Analog Devices Inc, at:
http://blackfin.uclinux.org/
We have tested this on LTP, and our test plan (including pass/fails) can
be found at:
http://docs.blackfin.uclinux.org/doku.php?id=testing_the_linux_kernel
[m.kozlowski@tuxland.pl: balance parenthesis in blackfin header files]
Signed-off-by: Bryan Wu <bryan.wu@analog.com>
Signed-off-by: Mariusz Kozlowski <m.kozlowski@tuxland.pl>
Signed-off-by: Aubrey Li <aubrey.li@analog.com>
Signed-off-by: Jie Zhang <jie.zhang@analog.com>
Signed-off-by: Andrew Morton <akpm@linux-foundation.org>
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
2007-05-06 15:50:22 -06:00
|
|
|
|
2009-11-24 11:36:36 -07:00
|
|
|
irq = channel2irq(channel);
|
|
|
|
ret = request_irq(irq, callback, 0, dma_ch[channel].device_id, data);
|
|
|
|
if (ret)
|
|
|
|
return ret;
|
blackfin architecture
This adds support for the Analog Devices Blackfin processor architecture, and
currently supports the BF533, BF532, BF531, BF537, BF536, BF534, and BF561
(Dual Core) devices, with a variety of development platforms including those
avaliable from Analog Devices (BF533-EZKit, BF533-STAMP, BF537-STAMP,
BF561-EZKIT), and Bluetechnix! Tinyboards.
The Blackfin architecture was jointly developed by Intel and Analog Devices
Inc. (ADI) as the Micro Signal Architecture (MSA) core and introduced it in
December of 2000. Since then ADI has put this core into its Blackfin
processor family of devices. The Blackfin core has the advantages of a clean,
orthogonal,RISC-like microprocessor instruction set. It combines a dual-MAC
(Multiply/Accumulate), state-of-the-art signal processing engine and
single-instruction, multiple-data (SIMD) multimedia capabilities into a single
instruction-set architecture.
The Blackfin architecture, including the instruction set, is described by the
ADSP-BF53x/BF56x Blackfin Processor Programming Reference
http://blackfin.uclinux.org/gf/download/frsrelease/29/2549/Blackfin_PRM.pdf
The Blackfin processor is already supported by major releases of gcc, and
there are binary and source rpms/tarballs for many architectures at:
http://blackfin.uclinux.org/gf/project/toolchain/frs There is complete
documentation, including "getting started" guides available at:
http://docs.blackfin.uclinux.org/ which provides links to the sources and
patches you will need in order to set up a cross-compiling environment for
bfin-linux-uclibc
This patch, as well as the other patches (toolchain, distribution,
uClibc) are actively supported by Analog Devices Inc, at:
http://blackfin.uclinux.org/
We have tested this on LTP, and our test plan (including pass/fails) can
be found at:
http://docs.blackfin.uclinux.org/doku.php?id=testing_the_linux_kernel
[m.kozlowski@tuxland.pl: balance parenthesis in blackfin header files]
Signed-off-by: Bryan Wu <bryan.wu@analog.com>
Signed-off-by: Mariusz Kozlowski <m.kozlowski@tuxland.pl>
Signed-off-by: Aubrey Li <aubrey.li@analog.com>
Signed-off-by: Jie Zhang <jie.zhang@analog.com>
Signed-off-by: Andrew Morton <akpm@linux-foundation.org>
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
2007-05-06 15:50:22 -06:00
|
|
|
|
2009-11-24 11:36:36 -07:00
|
|
|
dma_ch[channel].irq = irq;
|
|
|
|
dma_ch[channel].data = data;
|
2009-01-07 08:14:39 -07:00
|
|
|
|
blackfin architecture
This adds support for the Analog Devices Blackfin processor architecture, and
currently supports the BF533, BF532, BF531, BF537, BF536, BF534, and BF561
(Dual Core) devices, with a variety of development platforms including those
avaliable from Analog Devices (BF533-EZKit, BF533-STAMP, BF537-STAMP,
BF561-EZKIT), and Bluetechnix! Tinyboards.
The Blackfin architecture was jointly developed by Intel and Analog Devices
Inc. (ADI) as the Micro Signal Architecture (MSA) core and introduced it in
December of 2000. Since then ADI has put this core into its Blackfin
processor family of devices. The Blackfin core has the advantages of a clean,
orthogonal,RISC-like microprocessor instruction set. It combines a dual-MAC
(Multiply/Accumulate), state-of-the-art signal processing engine and
single-instruction, multiple-data (SIMD) multimedia capabilities into a single
instruction-set architecture.
The Blackfin architecture, including the instruction set, is described by the
ADSP-BF53x/BF56x Blackfin Processor Programming Reference
http://blackfin.uclinux.org/gf/download/frsrelease/29/2549/Blackfin_PRM.pdf
The Blackfin processor is already supported by major releases of gcc, and
there are binary and source rpms/tarballs for many architectures at:
http://blackfin.uclinux.org/gf/project/toolchain/frs There is complete
documentation, including "getting started" guides available at:
http://docs.blackfin.uclinux.org/ which provides links to the sources and
patches you will need in order to set up a cross-compiling environment for
bfin-linux-uclibc
This patch, as well as the other patches (toolchain, distribution,
uClibc) are actively supported by Analog Devices Inc, at:
http://blackfin.uclinux.org/
We have tested this on LTP, and our test plan (including pass/fails) can
be found at:
http://docs.blackfin.uclinux.org/doku.php?id=testing_the_linux_kernel
[m.kozlowski@tuxland.pl: balance parenthesis in blackfin header files]
Signed-off-by: Bryan Wu <bryan.wu@analog.com>
Signed-off-by: Mariusz Kozlowski <m.kozlowski@tuxland.pl>
Signed-off-by: Aubrey Li <aubrey.li@analog.com>
Signed-off-by: Jie Zhang <jie.zhang@analog.com>
Signed-off-by: Andrew Morton <akpm@linux-foundation.org>
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
2007-05-06 15:50:22 -06:00
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
EXPORT_SYMBOL(set_dma_callback);
|
|
|
|
|
2009-01-07 08:14:39 -07:00
|
|
|
/**
|
|
|
|
* clear_dma_buffer - clear DMA fifos for specified channel
|
|
|
|
*
|
|
|
|
* Set the Buffer Clear bit in the Configuration register of specific DMA
|
|
|
|
* channel. This will stop the descriptor based DMA operation.
|
|
|
|
*/
|
|
|
|
static void clear_dma_buffer(unsigned int channel)
|
|
|
|
{
|
|
|
|
dma_ch[channel].regs->cfg |= RESTART;
|
|
|
|
SSYNC();
|
|
|
|
dma_ch[channel].regs->cfg &= ~RESTART;
|
|
|
|
}
|
|
|
|
|
blackfin architecture
This adds support for the Analog Devices Blackfin processor architecture, and
currently supports the BF533, BF532, BF531, BF537, BF536, BF534, and BF561
(Dual Core) devices, with a variety of development platforms including those
avaliable from Analog Devices (BF533-EZKit, BF533-STAMP, BF537-STAMP,
BF561-EZKIT), and Bluetechnix! Tinyboards.
The Blackfin architecture was jointly developed by Intel and Analog Devices
Inc. (ADI) as the Micro Signal Architecture (MSA) core and introduced it in
December of 2000. Since then ADI has put this core into its Blackfin
processor family of devices. The Blackfin core has the advantages of a clean,
orthogonal,RISC-like microprocessor instruction set. It combines a dual-MAC
(Multiply/Accumulate), state-of-the-art signal processing engine and
single-instruction, multiple-data (SIMD) multimedia capabilities into a single
instruction-set architecture.
The Blackfin architecture, including the instruction set, is described by the
ADSP-BF53x/BF56x Blackfin Processor Programming Reference
http://blackfin.uclinux.org/gf/download/frsrelease/29/2549/Blackfin_PRM.pdf
The Blackfin processor is already supported by major releases of gcc, and
there are binary and source rpms/tarballs for many architectures at:
http://blackfin.uclinux.org/gf/project/toolchain/frs There is complete
documentation, including "getting started" guides available at:
http://docs.blackfin.uclinux.org/ which provides links to the sources and
patches you will need in order to set up a cross-compiling environment for
bfin-linux-uclibc
This patch, as well as the other patches (toolchain, distribution,
uClibc) are actively supported by Analog Devices Inc, at:
http://blackfin.uclinux.org/
We have tested this on LTP, and our test plan (including pass/fails) can
be found at:
http://docs.blackfin.uclinux.org/doku.php?id=testing_the_linux_kernel
[m.kozlowski@tuxland.pl: balance parenthesis in blackfin header files]
Signed-off-by: Bryan Wu <bryan.wu@analog.com>
Signed-off-by: Mariusz Kozlowski <m.kozlowski@tuxland.pl>
Signed-off-by: Aubrey Li <aubrey.li@analog.com>
Signed-off-by: Jie Zhang <jie.zhang@analog.com>
Signed-off-by: Andrew Morton <akpm@linux-foundation.org>
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
2007-05-06 15:50:22 -06:00
|
|
|
void free_dma(unsigned int channel)
|
|
|
|
{
|
2010-02-06 10:47:18 -07:00
|
|
|
pr_debug("freedma() : BEGIN\n");
|
2009-08-02 06:26:48 -06:00
|
|
|
BUG_ON(channel >= MAX_DMA_CHANNELS ||
|
2009-10-09 16:18:12 -06:00
|
|
|
!atomic_read(&dma_ch[channel].chan_status));
|
blackfin architecture
This adds support for the Analog Devices Blackfin processor architecture, and
currently supports the BF533, BF532, BF531, BF537, BF536, BF534, and BF561
(Dual Core) devices, with a variety of development platforms including those
avaliable from Analog Devices (BF533-EZKit, BF533-STAMP, BF537-STAMP,
BF561-EZKIT), and Bluetechnix! Tinyboards.
The Blackfin architecture was jointly developed by Intel and Analog Devices
Inc. (ADI) as the Micro Signal Architecture (MSA) core and introduced it in
December of 2000. Since then ADI has put this core into its Blackfin
processor family of devices. The Blackfin core has the advantages of a clean,
orthogonal,RISC-like microprocessor instruction set. It combines a dual-MAC
(Multiply/Accumulate), state-of-the-art signal processing engine and
single-instruction, multiple-data (SIMD) multimedia capabilities into a single
instruction-set architecture.
The Blackfin architecture, including the instruction set, is described by the
ADSP-BF53x/BF56x Blackfin Processor Programming Reference
http://blackfin.uclinux.org/gf/download/frsrelease/29/2549/Blackfin_PRM.pdf
The Blackfin processor is already supported by major releases of gcc, and
there are binary and source rpms/tarballs for many architectures at:
http://blackfin.uclinux.org/gf/project/toolchain/frs There is complete
documentation, including "getting started" guides available at:
http://docs.blackfin.uclinux.org/ which provides links to the sources and
patches you will need in order to set up a cross-compiling environment for
bfin-linux-uclibc
This patch, as well as the other patches (toolchain, distribution,
uClibc) are actively supported by Analog Devices Inc, at:
http://blackfin.uclinux.org/
We have tested this on LTP, and our test plan (including pass/fails) can
be found at:
http://docs.blackfin.uclinux.org/doku.php?id=testing_the_linux_kernel
[m.kozlowski@tuxland.pl: balance parenthesis in blackfin header files]
Signed-off-by: Bryan Wu <bryan.wu@analog.com>
Signed-off-by: Mariusz Kozlowski <m.kozlowski@tuxland.pl>
Signed-off-by: Aubrey Li <aubrey.li@analog.com>
Signed-off-by: Jie Zhang <jie.zhang@analog.com>
Signed-off-by: Andrew Morton <akpm@linux-foundation.org>
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
2007-05-06 15:50:22 -06:00
|
|
|
|
|
|
|
/* Halt the DMA */
|
|
|
|
disable_dma(channel);
|
|
|
|
clear_dma_buffer(channel);
|
|
|
|
|
2009-01-07 08:14:38 -07:00
|
|
|
if (dma_ch[channel].irq)
|
2008-10-28 04:19:29 -06:00
|
|
|
free_irq(dma_ch[channel].irq, dma_ch[channel].data);
|
blackfin architecture
This adds support for the Analog Devices Blackfin processor architecture, and
currently supports the BF533, BF532, BF531, BF537, BF536, BF534, and BF561
(Dual Core) devices, with a variety of development platforms including those
avaliable from Analog Devices (BF533-EZKit, BF533-STAMP, BF537-STAMP,
BF561-EZKIT), and Bluetechnix! Tinyboards.
The Blackfin architecture was jointly developed by Intel and Analog Devices
Inc. (ADI) as the Micro Signal Architecture (MSA) core and introduced it in
December of 2000. Since then ADI has put this core into its Blackfin
processor family of devices. The Blackfin core has the advantages of a clean,
orthogonal,RISC-like microprocessor instruction set. It combines a dual-MAC
(Multiply/Accumulate), state-of-the-art signal processing engine and
single-instruction, multiple-data (SIMD) multimedia capabilities into a single
instruction-set architecture.
The Blackfin architecture, including the instruction set, is described by the
ADSP-BF53x/BF56x Blackfin Processor Programming Reference
http://blackfin.uclinux.org/gf/download/frsrelease/29/2549/Blackfin_PRM.pdf
The Blackfin processor is already supported by major releases of gcc, and
there are binary and source rpms/tarballs for many architectures at:
http://blackfin.uclinux.org/gf/project/toolchain/frs There is complete
documentation, including "getting started" guides available at:
http://docs.blackfin.uclinux.org/ which provides links to the sources and
patches you will need in order to set up a cross-compiling environment for
bfin-linux-uclibc
This patch, as well as the other patches (toolchain, distribution,
uClibc) are actively supported by Analog Devices Inc, at:
http://blackfin.uclinux.org/
We have tested this on LTP, and our test plan (including pass/fails) can
be found at:
http://docs.blackfin.uclinux.org/doku.php?id=testing_the_linux_kernel
[m.kozlowski@tuxland.pl: balance parenthesis in blackfin header files]
Signed-off-by: Bryan Wu <bryan.wu@analog.com>
Signed-off-by: Mariusz Kozlowski <m.kozlowski@tuxland.pl>
Signed-off-by: Aubrey Li <aubrey.li@analog.com>
Signed-off-by: Jie Zhang <jie.zhang@analog.com>
Signed-off-by: Andrew Morton <akpm@linux-foundation.org>
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
2007-05-06 15:50:22 -06:00
|
|
|
|
|
|
|
/* Clear the DMA Variable in the Channel */
|
2009-10-09 16:18:12 -06:00
|
|
|
atomic_set(&dma_ch[channel].chan_status, 0);
|
blackfin architecture
This adds support for the Analog Devices Blackfin processor architecture, and
currently supports the BF533, BF532, BF531, BF537, BF536, BF534, and BF561
(Dual Core) devices, with a variety of development platforms including those
avaliable from Analog Devices (BF533-EZKit, BF533-STAMP, BF537-STAMP,
BF561-EZKIT), and Bluetechnix! Tinyboards.
The Blackfin architecture was jointly developed by Intel and Analog Devices
Inc. (ADI) as the Micro Signal Architecture (MSA) core and introduced it in
December of 2000. Since then ADI has put this core into its Blackfin
processor family of devices. The Blackfin core has the advantages of a clean,
orthogonal,RISC-like microprocessor instruction set. It combines a dual-MAC
(Multiply/Accumulate), state-of-the-art signal processing engine and
single-instruction, multiple-data (SIMD) multimedia capabilities into a single
instruction-set architecture.
The Blackfin architecture, including the instruction set, is described by the
ADSP-BF53x/BF56x Blackfin Processor Programming Reference
http://blackfin.uclinux.org/gf/download/frsrelease/29/2549/Blackfin_PRM.pdf
The Blackfin processor is already supported by major releases of gcc, and
there are binary and source rpms/tarballs for many architectures at:
http://blackfin.uclinux.org/gf/project/toolchain/frs There is complete
documentation, including "getting started" guides available at:
http://docs.blackfin.uclinux.org/ which provides links to the sources and
patches you will need in order to set up a cross-compiling environment for
bfin-linux-uclibc
This patch, as well as the other patches (toolchain, distribution,
uClibc) are actively supported by Analog Devices Inc, at:
http://blackfin.uclinux.org/
We have tested this on LTP, and our test plan (including pass/fails) can
be found at:
http://docs.blackfin.uclinux.org/doku.php?id=testing_the_linux_kernel
[m.kozlowski@tuxland.pl: balance parenthesis in blackfin header files]
Signed-off-by: Bryan Wu <bryan.wu@analog.com>
Signed-off-by: Mariusz Kozlowski <m.kozlowski@tuxland.pl>
Signed-off-by: Aubrey Li <aubrey.li@analog.com>
Signed-off-by: Jie Zhang <jie.zhang@analog.com>
Signed-off-by: Andrew Morton <akpm@linux-foundation.org>
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
2007-05-06 15:50:22 -06:00
|
|
|
|
2010-02-06 10:47:18 -07:00
|
|
|
pr_debug("freedma() : END\n");
|
blackfin architecture
This adds support for the Analog Devices Blackfin processor architecture, and
currently supports the BF533, BF532, BF531, BF537, BF536, BF534, and BF561
(Dual Core) devices, with a variety of development platforms including those
avaliable from Analog Devices (BF533-EZKit, BF533-STAMP, BF537-STAMP,
BF561-EZKIT), and Bluetechnix! Tinyboards.
The Blackfin architecture was jointly developed by Intel and Analog Devices
Inc. (ADI) as the Micro Signal Architecture (MSA) core and introduced it in
December of 2000. Since then ADI has put this core into its Blackfin
processor family of devices. The Blackfin core has the advantages of a clean,
orthogonal,RISC-like microprocessor instruction set. It combines a dual-MAC
(Multiply/Accumulate), state-of-the-art signal processing engine and
single-instruction, multiple-data (SIMD) multimedia capabilities into a single
instruction-set architecture.
The Blackfin architecture, including the instruction set, is described by the
ADSP-BF53x/BF56x Blackfin Processor Programming Reference
http://blackfin.uclinux.org/gf/download/frsrelease/29/2549/Blackfin_PRM.pdf
The Blackfin processor is already supported by major releases of gcc, and
there are binary and source rpms/tarballs for many architectures at:
http://blackfin.uclinux.org/gf/project/toolchain/frs There is complete
documentation, including "getting started" guides available at:
http://docs.blackfin.uclinux.org/ which provides links to the sources and
patches you will need in order to set up a cross-compiling environment for
bfin-linux-uclibc
This patch, as well as the other patches (toolchain, distribution,
uClibc) are actively supported by Analog Devices Inc, at:
http://blackfin.uclinux.org/
We have tested this on LTP, and our test plan (including pass/fails) can
be found at:
http://docs.blackfin.uclinux.org/doku.php?id=testing_the_linux_kernel
[m.kozlowski@tuxland.pl: balance parenthesis in blackfin header files]
Signed-off-by: Bryan Wu <bryan.wu@analog.com>
Signed-off-by: Mariusz Kozlowski <m.kozlowski@tuxland.pl>
Signed-off-by: Aubrey Li <aubrey.li@analog.com>
Signed-off-by: Jie Zhang <jie.zhang@analog.com>
Signed-off-by: Andrew Morton <akpm@linux-foundation.org>
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
2007-05-06 15:50:22 -06:00
|
|
|
}
|
|
|
|
EXPORT_SYMBOL(free_dma);
|
|
|
|
|
2008-07-19 02:57:32 -06:00
|
|
|
#ifdef CONFIG_PM
|
2009-01-07 08:14:39 -07:00
|
|
|
# ifndef MAX_DMA_SUSPEND_CHANNELS
|
|
|
|
# define MAX_DMA_SUSPEND_CHANNELS MAX_DMA_CHANNELS
|
|
|
|
# endif
|
2012-05-16 03:37:24 -06:00
|
|
|
# ifndef CONFIG_BF60x
|
2008-07-19 02:57:32 -06:00
|
|
|
int blackfin_dma_suspend(void)
|
|
|
|
{
|
|
|
|
int i;
|
|
|
|
|
2009-10-09 16:18:12 -06:00
|
|
|
for (i = 0; i < MAX_DMA_CHANNELS; ++i) {
|
|
|
|
if (dma_ch[i].regs->cfg & DMAEN) {
|
2008-07-19 02:57:32 -06:00
|
|
|
printk(KERN_ERR "DMA Channel %d failed to suspend\n", i);
|
|
|
|
return -EBUSY;
|
|
|
|
}
|
2009-10-09 16:18:12 -06:00
|
|
|
if (i < MAX_DMA_SUSPEND_CHANNELS)
|
|
|
|
dma_ch[i].saved_peripheral_map = dma_ch[i].regs->peripheral_map;
|
2008-07-19 02:57:32 -06:00
|
|
|
}
|
|
|
|
|
2012-03-18 23:50:27 -06:00
|
|
|
#if ANOMALY_05000480
|
|
|
|
bfin_write_DMAC_TC_PER(0x0);
|
|
|
|
#endif
|
2008-07-19 02:57:32 -06:00
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
void blackfin_dma_resume(void)
|
|
|
|
{
|
|
|
|
int i;
|
2009-10-20 07:38:04 -06:00
|
|
|
|
|
|
|
for (i = 0; i < MAX_DMA_CHANNELS; ++i) {
|
|
|
|
dma_ch[i].regs->cfg = 0;
|
|
|
|
if (i < MAX_DMA_SUSPEND_CHANNELS)
|
|
|
|
dma_ch[i].regs->peripheral_map = dma_ch[i].saved_peripheral_map;
|
|
|
|
}
|
2012-03-18 23:50:27 -06:00
|
|
|
#if ANOMALY_05000480
|
|
|
|
bfin_write_DMAC_TC_PER(0x0111);
|
|
|
|
#endif
|
2008-07-19 02:57:32 -06:00
|
|
|
}
|
2012-05-16 03:37:24 -06:00
|
|
|
# else
|
|
|
|
int blackfin_dma_suspend(void)
|
|
|
|
{
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
void blackfin_dma_resume(void)
|
|
|
|
{
|
|
|
|
}
|
|
|
|
#endif
|
2008-07-19 02:57:32 -06:00
|
|
|
#endif
|
|
|
|
|
2009-01-07 08:14:39 -07:00
|
|
|
/**
|
|
|
|
* blackfin_dma_early_init - minimal DMA init
|
|
|
|
*
|
|
|
|
* Setup a few DMA registers so we can safely do DMA transfers early on in
|
|
|
|
* the kernel booting process. Really this just means using dma_memcpy().
|
|
|
|
*/
|
|
|
|
void __init blackfin_dma_early_init(void)
|
blackfin architecture
This adds support for the Analog Devices Blackfin processor architecture, and
currently supports the BF533, BF532, BF531, BF537, BF536, BF534, and BF561
(Dual Core) devices, with a variety of development platforms including those
avaliable from Analog Devices (BF533-EZKit, BF533-STAMP, BF537-STAMP,
BF561-EZKIT), and Bluetechnix! Tinyboards.
The Blackfin architecture was jointly developed by Intel and Analog Devices
Inc. (ADI) as the Micro Signal Architecture (MSA) core and introduced it in
December of 2000. Since then ADI has put this core into its Blackfin
processor family of devices. The Blackfin core has the advantages of a clean,
orthogonal,RISC-like microprocessor instruction set. It combines a dual-MAC
(Multiply/Accumulate), state-of-the-art signal processing engine and
single-instruction, multiple-data (SIMD) multimedia capabilities into a single
instruction-set architecture.
The Blackfin architecture, including the instruction set, is described by the
ADSP-BF53x/BF56x Blackfin Processor Programming Reference
http://blackfin.uclinux.org/gf/download/frsrelease/29/2549/Blackfin_PRM.pdf
The Blackfin processor is already supported by major releases of gcc, and
there are binary and source rpms/tarballs for many architectures at:
http://blackfin.uclinux.org/gf/project/toolchain/frs There is complete
documentation, including "getting started" guides available at:
http://docs.blackfin.uclinux.org/ which provides links to the sources and
patches you will need in order to set up a cross-compiling environment for
bfin-linux-uclibc
This patch, as well as the other patches (toolchain, distribution,
uClibc) are actively supported by Analog Devices Inc, at:
http://blackfin.uclinux.org/
We have tested this on LTP, and our test plan (including pass/fails) can
be found at:
http://docs.blackfin.uclinux.org/doku.php?id=testing_the_linux_kernel
[m.kozlowski@tuxland.pl: balance parenthesis in blackfin header files]
Signed-off-by: Bryan Wu <bryan.wu@analog.com>
Signed-off-by: Mariusz Kozlowski <m.kozlowski@tuxland.pl>
Signed-off-by: Aubrey Li <aubrey.li@analog.com>
Signed-off-by: Jie Zhang <jie.zhang@analog.com>
Signed-off-by: Andrew Morton <akpm@linux-foundation.org>
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
2007-05-06 15:50:22 -06:00
|
|
|
{
|
2009-07-07 14:17:09 -06:00
|
|
|
early_shadow_stamp();
|
blackfin architecture
This adds support for the Analog Devices Blackfin processor architecture, and
currently supports the BF533, BF532, BF531, BF537, BF536, BF534, and BF561
(Dual Core) devices, with a variety of development platforms including those
avaliable from Analog Devices (BF533-EZKit, BF533-STAMP, BF537-STAMP,
BF561-EZKIT), and Bluetechnix! Tinyboards.
The Blackfin architecture was jointly developed by Intel and Analog Devices
Inc. (ADI) as the Micro Signal Architecture (MSA) core and introduced it in
December of 2000. Since then ADI has put this core into its Blackfin
processor family of devices. The Blackfin core has the advantages of a clean,
orthogonal,RISC-like microprocessor instruction set. It combines a dual-MAC
(Multiply/Accumulate), state-of-the-art signal processing engine and
single-instruction, multiple-data (SIMD) multimedia capabilities into a single
instruction-set architecture.
The Blackfin architecture, including the instruction set, is described by the
ADSP-BF53x/BF56x Blackfin Processor Programming Reference
http://blackfin.uclinux.org/gf/download/frsrelease/29/2549/Blackfin_PRM.pdf
The Blackfin processor is already supported by major releases of gcc, and
there are binary and source rpms/tarballs for many architectures at:
http://blackfin.uclinux.org/gf/project/toolchain/frs There is complete
documentation, including "getting started" guides available at:
http://docs.blackfin.uclinux.org/ which provides links to the sources and
patches you will need in order to set up a cross-compiling environment for
bfin-linux-uclibc
This patch, as well as the other patches (toolchain, distribution,
uClibc) are actively supported by Analog Devices Inc, at:
http://blackfin.uclinux.org/
We have tested this on LTP, and our test plan (including pass/fails) can
be found at:
http://docs.blackfin.uclinux.org/doku.php?id=testing_the_linux_kernel
[m.kozlowski@tuxland.pl: balance parenthesis in blackfin header files]
Signed-off-by: Bryan Wu <bryan.wu@analog.com>
Signed-off-by: Mariusz Kozlowski <m.kozlowski@tuxland.pl>
Signed-off-by: Aubrey Li <aubrey.li@analog.com>
Signed-off-by: Jie Zhang <jie.zhang@analog.com>
Signed-off-by: Andrew Morton <akpm@linux-foundation.org>
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
2007-05-06 15:50:22 -06:00
|
|
|
bfin_write_MDMA_S0_CONFIG(0);
|
2009-04-23 14:49:43 -06:00
|
|
|
bfin_write_MDMA_S1_CONFIG(0);
|
|
|
|
}
|
|
|
|
|
|
|
|
void __init early_dma_memcpy(void *pdst, const void *psrc, size_t size)
|
|
|
|
{
|
|
|
|
unsigned long dst = (unsigned long)pdst;
|
|
|
|
unsigned long src = (unsigned long)psrc;
|
|
|
|
struct dma_register *dst_ch, *src_ch;
|
|
|
|
|
2009-07-07 14:17:09 -06:00
|
|
|
early_shadow_stamp();
|
|
|
|
|
2009-04-23 14:49:43 -06:00
|
|
|
/* We assume that everything is 4 byte aligned, so include
|
|
|
|
* a basic sanity check
|
|
|
|
*/
|
|
|
|
BUG_ON(dst % 4);
|
|
|
|
BUG_ON(src % 4);
|
|
|
|
BUG_ON(size % 4);
|
|
|
|
|
|
|
|
src_ch = 0;
|
|
|
|
/* Find an avalible memDMA channel */
|
|
|
|
while (1) {
|
2009-06-29 16:45:50 -06:00
|
|
|
if (src_ch == (struct dma_register *)MDMA_S0_NEXT_DESC_PTR) {
|
2009-04-23 14:49:43 -06:00
|
|
|
dst_ch = (struct dma_register *)MDMA_D1_NEXT_DESC_PTR;
|
|
|
|
src_ch = (struct dma_register *)MDMA_S1_NEXT_DESC_PTR;
|
2009-06-29 16:45:50 -06:00
|
|
|
} else {
|
|
|
|
dst_ch = (struct dma_register *)MDMA_D0_NEXT_DESC_PTR;
|
|
|
|
src_ch = (struct dma_register *)MDMA_S0_NEXT_DESC_PTR;
|
2009-04-23 14:49:43 -06:00
|
|
|
}
|
|
|
|
|
2012-05-16 03:37:24 -06:00
|
|
|
if (!DMA_MMR_READ(&src_ch->cfg))
|
2009-06-29 16:45:50 -06:00
|
|
|
break;
|
2012-05-16 03:37:24 -06:00
|
|
|
else if (DMA_MMR_READ(&dst_ch->irq_status) & DMA_DONE) {
|
|
|
|
DMA_MMR_WRITE(&src_ch->cfg, 0);
|
2009-04-23 14:49:43 -06:00
|
|
|
break;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2009-06-29 16:45:50 -06:00
|
|
|
/* Force a sync in case a previous config reset on this channel
|
|
|
|
* occurred. This is needed so subsequent writes to DMA registers
|
|
|
|
* are not spuriously lost/corrupted.
|
|
|
|
*/
|
|
|
|
__builtin_bfin_ssync();
|
|
|
|
|
2009-04-23 14:49:43 -06:00
|
|
|
/* Destination */
|
|
|
|
bfin_write32(&dst_ch->start_addr, dst);
|
2012-05-16 03:37:24 -06:00
|
|
|
DMA_MMR_WRITE(&dst_ch->x_count, size >> 2);
|
|
|
|
DMA_MMR_WRITE(&dst_ch->x_modify, 1 << 2);
|
|
|
|
DMA_MMR_WRITE(&dst_ch->irq_status, DMA_DONE | DMA_ERR);
|
2009-04-23 14:49:43 -06:00
|
|
|
|
|
|
|
/* Source */
|
|
|
|
bfin_write32(&src_ch->start_addr, src);
|
2012-05-16 03:37:24 -06:00
|
|
|
DMA_MMR_WRITE(&src_ch->x_count, size >> 2);
|
|
|
|
DMA_MMR_WRITE(&src_ch->x_modify, 1 << 2);
|
|
|
|
DMA_MMR_WRITE(&src_ch->irq_status, DMA_DONE | DMA_ERR);
|
2009-04-23 14:49:43 -06:00
|
|
|
|
|
|
|
/* Enable */
|
2012-05-16 03:37:24 -06:00
|
|
|
DMA_MMR_WRITE(&src_ch->cfg, DMAEN | WDSIZE_32);
|
|
|
|
DMA_MMR_WRITE(&dst_ch->cfg, WNR | DI_EN_X | DMAEN | WDSIZE_32);
|
2009-04-23 14:49:43 -06:00
|
|
|
|
|
|
|
/* Since we are atomic now, don't use the workaround ssync */
|
|
|
|
__builtin_bfin_ssync();
|
2012-05-16 03:37:24 -06:00
|
|
|
|
|
|
|
#ifdef CONFIG_BF60x
|
|
|
|
/* Work around a possible MDMA anomaly. Running 2 MDMA channels to
|
|
|
|
* transfer DDR data to L1 SRAM may corrupt data.
|
|
|
|
* Should be reverted after this issue is root caused.
|
|
|
|
*/
|
|
|
|
while (!(DMA_MMR_READ(&dst_ch->irq_status) & DMA_DONE))
|
|
|
|
continue;
|
|
|
|
#endif
|
2009-04-23 14:49:43 -06:00
|
|
|
}
|
|
|
|
|
|
|
|
void __init early_dma_memcpy_done(void)
|
|
|
|
{
|
2009-07-07 14:17:09 -06:00
|
|
|
early_shadow_stamp();
|
|
|
|
|
2009-04-23 14:49:43 -06:00
|
|
|
while ((bfin_read_MDMA_S0_CONFIG() && !(bfin_read_MDMA_D0_IRQ_STATUS() & DMA_DONE)) ||
|
|
|
|
(bfin_read_MDMA_S1_CONFIG() && !(bfin_read_MDMA_D1_IRQ_STATUS() & DMA_DONE)))
|
|
|
|
continue;
|
|
|
|
|
|
|
|
bfin_write_MDMA_D0_IRQ_STATUS(DMA_DONE | DMA_ERR);
|
|
|
|
bfin_write_MDMA_D1_IRQ_STATUS(DMA_DONE | DMA_ERR);
|
|
|
|
/*
|
|
|
|
* Now that DMA is done, we would normally flush cache, but
|
|
|
|
* i/d cache isn't running this early, so we don't bother,
|
|
|
|
* and just clear out the DMA channel for next time
|
|
|
|
*/
|
|
|
|
bfin_write_MDMA_S0_CONFIG(0);
|
|
|
|
bfin_write_MDMA_S1_CONFIG(0);
|
|
|
|
bfin_write_MDMA_D0_CONFIG(0);
|
|
|
|
bfin_write_MDMA_D1_CONFIG(0);
|
|
|
|
|
|
|
|
__builtin_bfin_ssync();
|
blackfin architecture
This adds support for the Analog Devices Blackfin processor architecture, and
currently supports the BF533, BF532, BF531, BF537, BF536, BF534, and BF561
(Dual Core) devices, with a variety of development platforms including those
avaliable from Analog Devices (BF533-EZKit, BF533-STAMP, BF537-STAMP,
BF561-EZKIT), and Bluetechnix! Tinyboards.
The Blackfin architecture was jointly developed by Intel and Analog Devices
Inc. (ADI) as the Micro Signal Architecture (MSA) core and introduced it in
December of 2000. Since then ADI has put this core into its Blackfin
processor family of devices. The Blackfin core has the advantages of a clean,
orthogonal,RISC-like microprocessor instruction set. It combines a dual-MAC
(Multiply/Accumulate), state-of-the-art signal processing engine and
single-instruction, multiple-data (SIMD) multimedia capabilities into a single
instruction-set architecture.
The Blackfin architecture, including the instruction set, is described by the
ADSP-BF53x/BF56x Blackfin Processor Programming Reference
http://blackfin.uclinux.org/gf/download/frsrelease/29/2549/Blackfin_PRM.pdf
The Blackfin processor is already supported by major releases of gcc, and
there are binary and source rpms/tarballs for many architectures at:
http://blackfin.uclinux.org/gf/project/toolchain/frs There is complete
documentation, including "getting started" guides available at:
http://docs.blackfin.uclinux.org/ which provides links to the sources and
patches you will need in order to set up a cross-compiling environment for
bfin-linux-uclibc
This patch, as well as the other patches (toolchain, distribution,
uClibc) are actively supported by Analog Devices Inc, at:
http://blackfin.uclinux.org/
We have tested this on LTP, and our test plan (including pass/fails) can
be found at:
http://docs.blackfin.uclinux.org/doku.php?id=testing_the_linux_kernel
[m.kozlowski@tuxland.pl: balance parenthesis in blackfin header files]
Signed-off-by: Bryan Wu <bryan.wu@analog.com>
Signed-off-by: Mariusz Kozlowski <m.kozlowski@tuxland.pl>
Signed-off-by: Aubrey Li <aubrey.li@analog.com>
Signed-off-by: Jie Zhang <jie.zhang@analog.com>
Signed-off-by: Andrew Morton <akpm@linux-foundation.org>
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
2007-05-06 15:50:22 -06:00
|
|
|
}
|
2007-05-21 04:09:28 -06:00
|
|
|
|
2012-05-24 21:32:03 -06:00
|
|
|
#if defined(CH_MEM_STREAM3_SRC) && defined(CONFIG_BF60x)
|
2012-05-16 03:37:24 -06:00
|
|
|
#define bfin_read_MDMA_S_CONFIG bfin_read_MDMA_S3_CONFIG
|
|
|
|
#define bfin_write_MDMA_S_CONFIG bfin_write_MDMA_S3_CONFIG
|
|
|
|
#define bfin_write_MDMA_S_START_ADDR bfin_write_MDMA_S3_START_ADDR
|
|
|
|
#define bfin_write_MDMA_S_IRQ_STATUS bfin_write_MDMA_S3_IRQ_STATUS
|
|
|
|
#define bfin_write_MDMA_S_X_COUNT bfin_write_MDMA_S3_X_COUNT
|
|
|
|
#define bfin_write_MDMA_S_X_MODIFY bfin_write_MDMA_S3_X_MODIFY
|
|
|
|
#define bfin_write_MDMA_S_Y_COUNT bfin_write_MDMA_S3_Y_COUNT
|
|
|
|
#define bfin_write_MDMA_S_Y_MODIFY bfin_write_MDMA_S3_Y_MODIFY
|
|
|
|
#define bfin_write_MDMA_D_CONFIG bfin_write_MDMA_D3_CONFIG
|
|
|
|
#define bfin_write_MDMA_D_START_ADDR bfin_write_MDMA_D3_START_ADDR
|
|
|
|
#define bfin_read_MDMA_D_IRQ_STATUS bfin_read_MDMA_D3_IRQ_STATUS
|
|
|
|
#define bfin_write_MDMA_D_IRQ_STATUS bfin_write_MDMA_D3_IRQ_STATUS
|
|
|
|
#define bfin_write_MDMA_D_X_COUNT bfin_write_MDMA_D3_X_COUNT
|
|
|
|
#define bfin_write_MDMA_D_X_MODIFY bfin_write_MDMA_D3_X_MODIFY
|
|
|
|
#define bfin_write_MDMA_D_Y_COUNT bfin_write_MDMA_D3_Y_COUNT
|
|
|
|
#define bfin_write_MDMA_D_Y_MODIFY bfin_write_MDMA_D3_Y_MODIFY
|
|
|
|
#else
|
|
|
|
#define bfin_read_MDMA_S_CONFIG bfin_read_MDMA_S0_CONFIG
|
|
|
|
#define bfin_write_MDMA_S_CONFIG bfin_write_MDMA_S0_CONFIG
|
|
|
|
#define bfin_write_MDMA_S_START_ADDR bfin_write_MDMA_S0_START_ADDR
|
|
|
|
#define bfin_write_MDMA_S_IRQ_STATUS bfin_write_MDMA_S0_IRQ_STATUS
|
|
|
|
#define bfin_write_MDMA_S_X_COUNT bfin_write_MDMA_S0_X_COUNT
|
|
|
|
#define bfin_write_MDMA_S_X_MODIFY bfin_write_MDMA_S0_X_MODIFY
|
|
|
|
#define bfin_write_MDMA_S_Y_COUNT bfin_write_MDMA_S0_Y_COUNT
|
|
|
|
#define bfin_write_MDMA_S_Y_MODIFY bfin_write_MDMA_S0_Y_MODIFY
|
|
|
|
#define bfin_write_MDMA_D_CONFIG bfin_write_MDMA_D0_CONFIG
|
|
|
|
#define bfin_write_MDMA_D_START_ADDR bfin_write_MDMA_D0_START_ADDR
|
|
|
|
#define bfin_read_MDMA_D_IRQ_STATUS bfin_read_MDMA_D0_IRQ_STATUS
|
|
|
|
#define bfin_write_MDMA_D_IRQ_STATUS bfin_write_MDMA_D0_IRQ_STATUS
|
|
|
|
#define bfin_write_MDMA_D_X_COUNT bfin_write_MDMA_D0_X_COUNT
|
|
|
|
#define bfin_write_MDMA_D_X_MODIFY bfin_write_MDMA_D0_X_MODIFY
|
|
|
|
#define bfin_write_MDMA_D_Y_COUNT bfin_write_MDMA_D0_Y_COUNT
|
|
|
|
#define bfin_write_MDMA_D_Y_MODIFY bfin_write_MDMA_D0_Y_MODIFY
|
|
|
|
#endif
|
|
|
|
|
2009-01-07 08:14:38 -07:00
|
|
|
/**
|
2009-01-07 08:14:39 -07:00
|
|
|
* __dma_memcpy - program the MDMA registers
|
2009-01-07 08:14:38 -07:00
|
|
|
*
|
2009-01-07 08:14:39 -07:00
|
|
|
* Actually program MDMA0 and wait for the transfer to finish. Disable IRQs
|
|
|
|
* while programming registers so that everything is fully configured. Wait
|
|
|
|
* for DMA to finish with IRQs enabled. If interrupted, the initial DMA_DONE
|
|
|
|
* check will make sure we don't clobber any existing transfer.
|
2009-01-07 08:14:38 -07:00
|
|
|
*/
|
2009-01-07 08:14:39 -07:00
|
|
|
static void __dma_memcpy(u32 daddr, s16 dmod, u32 saddr, s16 smod, size_t cnt, u32 conf)
|
2007-05-21 04:09:17 -06:00
|
|
|
{
|
2009-01-07 08:14:39 -07:00
|
|
|
static DEFINE_SPINLOCK(mdma_lock);
|
2007-05-21 04:09:17 -06:00
|
|
|
unsigned long flags;
|
2007-07-12 08:58:21 -06:00
|
|
|
|
2009-01-07 08:14:39 -07:00
|
|
|
spin_lock_irqsave(&mdma_lock, flags);
|
|
|
|
|
2009-02-04 01:49:45 -07:00
|
|
|
/* Force a sync in case a previous config reset on this channel
|
|
|
|
* occurred. This is needed so subsequent writes to DMA registers
|
|
|
|
* are not spuriously lost/corrupted. Do it under irq lock and
|
|
|
|
* without the anomaly version (because we are atomic already).
|
|
|
|
*/
|
|
|
|
__builtin_bfin_ssync();
|
|
|
|
|
2012-05-16 03:37:24 -06:00
|
|
|
if (bfin_read_MDMA_S_CONFIG())
|
|
|
|
while (!(bfin_read_MDMA_D_IRQ_STATUS() & DMA_DONE))
|
2009-01-07 08:14:39 -07:00
|
|
|
continue;
|
|
|
|
|
|
|
|
if (conf & DMA2D) {
|
|
|
|
/* For larger bit sizes, we've already divided down cnt so it
|
|
|
|
* is no longer a multiple of 64k. So we have to break down
|
|
|
|
* the limit here so it is a multiple of the incoming size.
|
|
|
|
* There is no limitation here in terms of total size other
|
|
|
|
* than the hardware though as the bits lost in the shift are
|
|
|
|
* made up by MODIFY (== we can hit the whole address space).
|
|
|
|
* X: (2^(16 - 0)) * 1 == (2^(16 - 1)) * 2 == (2^(16 - 2)) * 4
|
|
|
|
*/
|
|
|
|
u32 shift = abs(dmod) >> 1;
|
|
|
|
size_t ycnt = cnt >> (16 - shift);
|
|
|
|
cnt = 1 << (16 - shift);
|
2012-05-16 03:37:24 -06:00
|
|
|
bfin_write_MDMA_D_Y_COUNT(ycnt);
|
|
|
|
bfin_write_MDMA_S_Y_COUNT(ycnt);
|
|
|
|
bfin_write_MDMA_D_Y_MODIFY(dmod);
|
|
|
|
bfin_write_MDMA_S_Y_MODIFY(smod);
|
2009-01-07 08:14:39 -07:00
|
|
|
}
|
2007-07-12 08:58:21 -06:00
|
|
|
|
2012-05-16 03:37:24 -06:00
|
|
|
bfin_write_MDMA_D_START_ADDR(daddr);
|
|
|
|
bfin_write_MDMA_D_X_COUNT(cnt);
|
|
|
|
bfin_write_MDMA_D_X_MODIFY(dmod);
|
|
|
|
bfin_write_MDMA_D_IRQ_STATUS(DMA_DONE | DMA_ERR);
|
2007-05-21 04:09:17 -06:00
|
|
|
|
2012-05-16 03:37:24 -06:00
|
|
|
bfin_write_MDMA_S_START_ADDR(saddr);
|
|
|
|
bfin_write_MDMA_S_X_COUNT(cnt);
|
|
|
|
bfin_write_MDMA_S_X_MODIFY(smod);
|
|
|
|
bfin_write_MDMA_S_IRQ_STATUS(DMA_DONE | DMA_ERR);
|
2007-05-21 04:09:17 -06:00
|
|
|
|
2012-05-16 03:37:24 -06:00
|
|
|
bfin_write_MDMA_S_CONFIG(DMAEN | conf);
|
|
|
|
if (conf & DMA2D)
|
|
|
|
bfin_write_MDMA_D_CONFIG(WNR | DI_EN_Y | DMAEN | conf);
|
|
|
|
else
|
|
|
|
bfin_write_MDMA_D_CONFIG(WNR | DI_EN_X | DMAEN | conf);
|
2009-01-07 08:14:39 -07:00
|
|
|
|
|
|
|
spin_unlock_irqrestore(&mdma_lock, flags);
|
2007-05-21 04:09:17 -06:00
|
|
|
|
2007-10-10 03:42:55 -06:00
|
|
|
SSYNC();
|
|
|
|
|
2012-05-16 03:37:24 -06:00
|
|
|
while (!(bfin_read_MDMA_D_IRQ_STATUS() & DMA_DONE))
|
|
|
|
if (bfin_read_MDMA_S_CONFIG())
|
2009-01-07 08:14:39 -07:00
|
|
|
continue;
|
|
|
|
else
|
|
|
|
return;
|
2007-05-21 04:09:17 -06:00
|
|
|
|
2012-05-16 03:37:24 -06:00
|
|
|
bfin_write_MDMA_D_IRQ_STATUS(DMA_DONE | DMA_ERR);
|
2007-05-21 04:09:17 -06:00
|
|
|
|
2012-05-16 03:37:24 -06:00
|
|
|
bfin_write_MDMA_S_CONFIG(0);
|
|
|
|
bfin_write_MDMA_D_CONFIG(0);
|
2007-05-21 04:09:17 -06:00
|
|
|
}
|
|
|
|
|
2009-01-07 08:14:39 -07:00
|
|
|
/**
|
|
|
|
* _dma_memcpy - translate C memcpy settings into MDMA settings
|
|
|
|
*
|
|
|
|
* Handle all the high level steps before we touch the MDMA registers. So
|
2009-01-07 08:14:39 -07:00
|
|
|
* handle direction, tweaking of sizes, and formatting of addresses.
|
2009-01-07 08:14:39 -07:00
|
|
|
*/
|
|
|
|
static void *_dma_memcpy(void *pdst, const void *psrc, size_t size)
|
2007-05-21 04:09:17 -06:00
|
|
|
{
|
2009-01-07 08:14:39 -07:00
|
|
|
u32 conf, shift;
|
|
|
|
s16 mod;
|
|
|
|
unsigned long dst = (unsigned long)pdst;
|
|
|
|
unsigned long src = (unsigned long)psrc;
|
2007-07-12 08:58:21 -06:00
|
|
|
|
2009-01-07 08:14:39 -07:00
|
|
|
if (size == 0)
|
|
|
|
return NULL;
|
2007-10-10 03:42:55 -06:00
|
|
|
|
2009-01-07 08:14:39 -07:00
|
|
|
if (dst % 4 == 0 && src % 4 == 0 && size % 4 == 0) {
|
|
|
|
conf = WDSIZE_32;
|
|
|
|
shift = 2;
|
|
|
|
} else if (dst % 2 == 0 && src % 2 == 0 && size % 2 == 0) {
|
|
|
|
conf = WDSIZE_16;
|
|
|
|
shift = 1;
|
|
|
|
} else {
|
|
|
|
conf = WDSIZE_8;
|
|
|
|
shift = 0;
|
|
|
|
}
|
2007-05-21 04:09:17 -06:00
|
|
|
|
2009-01-07 08:14:39 -07:00
|
|
|
/* If the two memory regions have a chance of overlapping, make
|
|
|
|
* sure the memcpy still works as expected. Do this by having the
|
|
|
|
* copy run backwards instead.
|
|
|
|
*/
|
|
|
|
mod = 1 << shift;
|
|
|
|
if (src < dst) {
|
|
|
|
mod *= -1;
|
|
|
|
dst += size + mod;
|
|
|
|
src += size + mod;
|
|
|
|
}
|
|
|
|
size >>= shift;
|
2007-05-21 04:09:17 -06:00
|
|
|
|
2012-05-16 03:37:24 -06:00
|
|
|
#ifndef DMA_MMR_SIZE_32
|
2009-01-07 08:14:39 -07:00
|
|
|
if (size > 0x10000)
|
|
|
|
conf |= DMA2D;
|
2012-05-16 03:37:24 -06:00
|
|
|
#endif
|
2007-05-21 04:09:17 -06:00
|
|
|
|
2009-01-07 08:14:39 -07:00
|
|
|
__dma_memcpy(dst, mod, src, mod, size, conf);
|
2007-05-21 04:09:17 -06:00
|
|
|
|
2009-01-07 08:14:39 -07:00
|
|
|
return pdst;
|
2007-05-21 04:09:17 -06:00
|
|
|
}
|
|
|
|
|
2009-01-07 08:14:39 -07:00
|
|
|
/**
|
|
|
|
* dma_memcpy - DMA memcpy under mutex lock
|
|
|
|
*
|
|
|
|
* Do not check arguments before starting the DMA memcpy. Break the transfer
|
|
|
|
* up into two pieces. The first transfer is in multiples of 64k and the
|
|
|
|
* second transfer is the piece smaller than 64k.
|
|
|
|
*/
|
2009-01-07 08:14:39 -07:00
|
|
|
void *dma_memcpy(void *pdst, const void *psrc, size_t size)
|
2007-05-21 04:09:17 -06:00
|
|
|
{
|
2009-01-07 08:14:39 -07:00
|
|
|
unsigned long dst = (unsigned long)pdst;
|
|
|
|
unsigned long src = (unsigned long)psrc;
|
|
|
|
|
2009-06-10 00:26:26 -06:00
|
|
|
if (bfin_addr_dcacheable(src))
|
2009-01-07 08:14:39 -07:00
|
|
|
blackfin_dcache_flush_range(src, src + size);
|
|
|
|
|
2009-06-10 00:26:26 -06:00
|
|
|
if (bfin_addr_dcacheable(dst))
|
2009-01-07 08:14:39 -07:00
|
|
|
blackfin_dcache_invalidate_range(dst, dst + size);
|
|
|
|
|
2010-06-16 03:12:10 -06:00
|
|
|
return dma_memcpy_nocache(pdst, psrc, size);
|
|
|
|
}
|
|
|
|
EXPORT_SYMBOL(dma_memcpy);
|
|
|
|
|
|
|
|
/**
|
|
|
|
* dma_memcpy_nocache - DMA memcpy under mutex lock
|
|
|
|
* - No cache flush/invalidate
|
|
|
|
*
|
|
|
|
* Do not check arguments before starting the DMA memcpy. Break the transfer
|
|
|
|
* up into two pieces. The first transfer is in multiples of 64k and the
|
|
|
|
* second transfer is the piece smaller than 64k.
|
|
|
|
*/
|
|
|
|
void *dma_memcpy_nocache(void *pdst, const void *psrc, size_t size)
|
|
|
|
{
|
2012-05-16 03:37:24 -06:00
|
|
|
#ifdef DMA_MMR_SIZE_32
|
|
|
|
_dma_memcpy(pdst, psrc, size);
|
|
|
|
#else
|
2010-06-16 03:12:10 -06:00
|
|
|
size_t bulk, rest;
|
|
|
|
|
2009-01-07 08:14:39 -07:00
|
|
|
bulk = size & ~0xffff;
|
|
|
|
rest = size - bulk;
|
|
|
|
if (bulk)
|
2009-01-07 08:14:39 -07:00
|
|
|
_dma_memcpy(pdst, psrc, bulk);
|
|
|
|
_dma_memcpy(pdst + bulk, psrc + bulk, rest);
|
2012-05-16 03:37:24 -06:00
|
|
|
#endif
|
2009-01-07 08:14:39 -07:00
|
|
|
return pdst;
|
2007-05-21 04:09:17 -06:00
|
|
|
}
|
2010-06-16 03:12:10 -06:00
|
|
|
EXPORT_SYMBOL(dma_memcpy_nocache);
|
2007-05-21 04:09:17 -06:00
|
|
|
|
2009-01-07 08:14:39 -07:00
|
|
|
/**
|
|
|
|
* safe_dma_memcpy - DMA memcpy w/argument checking
|
|
|
|
*
|
|
|
|
* Verify arguments are safe before heading to dma_memcpy().
|
|
|
|
*/
|
|
|
|
void *safe_dma_memcpy(void *dst, const void *src, size_t size)
|
2007-05-21 04:09:17 -06:00
|
|
|
{
|
2009-01-07 08:14:39 -07:00
|
|
|
if (!access_ok(VERIFY_WRITE, dst, size))
|
|
|
|
return NULL;
|
|
|
|
if (!access_ok(VERIFY_READ, src, size))
|
|
|
|
return NULL;
|
|
|
|
return dma_memcpy(dst, src, size);
|
2007-05-21 04:09:17 -06:00
|
|
|
}
|
2009-01-07 08:14:39 -07:00
|
|
|
EXPORT_SYMBOL(safe_dma_memcpy);
|
2007-05-21 04:09:17 -06:00
|
|
|
|
2012-05-16 03:37:24 -06:00
|
|
|
static void _dma_out(unsigned long addr, unsigned long buf, unsigned DMA_MMR_SIZE_TYPE len,
|
2009-01-07 08:14:39 -07:00
|
|
|
u16 size, u16 dma_size)
|
2007-05-21 04:09:17 -06:00
|
|
|
{
|
2009-01-07 08:14:39 -07:00
|
|
|
blackfin_dcache_flush_range(buf, buf + len * size);
|
|
|
|
__dma_memcpy(addr, 0, buf, size, len, dma_size);
|
2007-05-21 04:09:17 -06:00
|
|
|
}
|
|
|
|
|
2012-05-16 03:37:24 -06:00
|
|
|
static void _dma_in(unsigned long addr, unsigned long buf, unsigned DMA_MMR_SIZE_TYPE len,
|
2009-01-07 08:14:39 -07:00
|
|
|
u16 size, u16 dma_size)
|
2007-05-21 04:09:17 -06:00
|
|
|
{
|
2009-01-07 08:14:39 -07:00
|
|
|
blackfin_dcache_invalidate_range(buf, buf + len * size);
|
|
|
|
__dma_memcpy(buf, size, addr, 0, len, dma_size);
|
2007-05-21 04:09:17 -06:00
|
|
|
}
|
2009-01-07 08:14:39 -07:00
|
|
|
|
|
|
|
#define MAKE_DMA_IO(io, bwl, isize, dmasize, cnst) \
|
2012-05-16 03:37:24 -06:00
|
|
|
void dma_##io##s##bwl(unsigned long addr, cnst void *buf, unsigned DMA_MMR_SIZE_TYPE len) \
|
2009-01-07 08:14:39 -07:00
|
|
|
{ \
|
|
|
|
_dma_##io(addr, (unsigned long)buf, len, isize, WDSIZE_##dmasize); \
|
|
|
|
} \
|
|
|
|
EXPORT_SYMBOL(dma_##io##s##bwl)
|
|
|
|
MAKE_DMA_IO(out, b, 1, 8, const);
|
|
|
|
MAKE_DMA_IO(in, b, 1, 8, );
|
|
|
|
MAKE_DMA_IO(out, w, 2, 16, const);
|
|
|
|
MAKE_DMA_IO(in, w, 2, 16, );
|
|
|
|
MAKE_DMA_IO(out, l, 4, 32, const);
|
|
|
|
MAKE_DMA_IO(in, l, 4, 32, );
|