355 lines
9.8 KiB
C
355 lines
9.8 KiB
C
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/*
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* ATI Rage XL Initialization. Support for Xpert98 and Victoria
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* PCI cards.
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*
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* Copyright (C) 2002 MontaVista Software Inc.
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* Author: MontaVista Software, Inc.
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* stevel@mvista.com or source@mvista.com
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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*
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* THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
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* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
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* NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
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* USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
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* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* You should have received a copy of the GNU General Public License along
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* with this program; if not, write to the Free Software Foundation, Inc.,
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* 675 Mass Ave, Cambridge, MA 02139, USA.
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*/
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#include <linux/config.h>
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#include <linux/module.h>
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#include <linux/kernel.h>
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#include <linux/errno.h>
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#include <linux/string.h>
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#include <linux/mm.h>
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#include <linux/slab.h>
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#include <linux/vmalloc.h>
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#include <linux/delay.h>
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#include <linux/fb.h>
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#include <linux/init.h>
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#include <linux/pci.h>
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#include <asm/io.h>
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#include <video/mach64.h>
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#include "atyfb.h"
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#define MPLL_GAIN 0xad
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#define VPLL_GAIN 0xd5
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enum {
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VICTORIA = 0,
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XPERT98,
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NUM_XL_CARDS
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};
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extern const struct aty_pll_ops aty_pll_ct;
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#define DEFAULT_CARD XPERT98
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static int xl_card = DEFAULT_CARD;
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static const struct xl_card_cfg_t {
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int ref_crystal; // 10^4 Hz
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int mem_type;
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int mem_size;
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u32 mem_cntl;
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u32 ext_mem_cntl;
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u32 mem_addr_config;
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u32 bus_cntl;
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u32 dac_cntl;
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u32 hw_debug;
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u32 custom_macro_cntl;
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u8 dll2_cntl;
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u8 pll_yclk_cntl;
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} card_cfg[NUM_XL_CARDS] = {
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// VICTORIA
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{ 2700, SDRAM, 0x800000,
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0x10757A3B, 0x64000C81, 0x00110202, 0x7b33A040,
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0x82010102, 0x48803800, 0x005E0179,
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0x50, 0x25
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},
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// XPERT98
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{ 1432, WRAM, 0x800000,
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0x00165A2B, 0xE0000CF1, 0x00200213, 0x7333A001,
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0x8000000A, 0x48833800, 0x007F0779,
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0x10, 0x19
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}
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};
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typedef struct {
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u8 lcd_reg;
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u32 val;
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} lcd_tbl_t;
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static const lcd_tbl_t lcd_tbl[] = {
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{ 0x01, 0x000520C0 },
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{ 0x08, 0x02000408 },
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{ 0x03, 0x00000F00 },
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{ 0x00, 0x00000000 },
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{ 0x02, 0x00000000 },
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{ 0x04, 0x00000000 },
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{ 0x05, 0x00000000 },
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{ 0x06, 0x00000000 },
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{ 0x33, 0x00000000 },
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{ 0x34, 0x00000000 },
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{ 0x35, 0x00000000 },
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{ 0x36, 0x00000000 },
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{ 0x37, 0x00000000 }
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};
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static void reset_gui(struct atyfb_par *par)
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{
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aty_st_8(GEN_TEST_CNTL+1, 0x01, par);
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aty_st_8(GEN_TEST_CNTL+1, 0x00, par);
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aty_st_8(GEN_TEST_CNTL+1, 0x02, par);
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mdelay(5);
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}
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static void reset_sdram(struct atyfb_par *par)
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{
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u8 temp;
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temp = aty_ld_8(EXT_MEM_CNTL, par);
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temp |= 0x02;
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aty_st_8(EXT_MEM_CNTL, temp, par); // MEM_SDRAM_RESET = 1b
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temp |= 0x08;
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aty_st_8(EXT_MEM_CNTL, temp, par); // MEM_CYC_TEST = 10b
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temp |= 0x0c;
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aty_st_8(EXT_MEM_CNTL, temp, par); // MEM_CYC_TEST = 11b
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mdelay(5);
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temp &= 0xf3;
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aty_st_8(EXT_MEM_CNTL, temp, par); // MEM_CYC_TEST = 00b
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temp &= 0xfd;
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aty_st_8(EXT_MEM_CNTL, temp, par); // MEM_SDRAM_REST = 0b
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mdelay(5);
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}
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static void init_dll(struct atyfb_par *par)
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{
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// enable DLL
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aty_st_pll_ct(PLL_GEN_CNTL,
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aty_ld_pll_ct(PLL_GEN_CNTL, par) & 0x7f,
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par);
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// reset DLL
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aty_st_pll_ct(DLL_CNTL, 0x82, par);
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aty_st_pll_ct(DLL_CNTL, 0xE2, par);
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mdelay(5);
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aty_st_pll_ct(DLL_CNTL, 0x82, par);
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mdelay(6);
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}
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static void reset_clocks(struct atyfb_par *par, struct pll_ct *pll,
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int hsync_enb)
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{
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reset_gui(par);
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aty_st_pll_ct(MCLK_FB_DIV, pll->mclk_fb_div, par);
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aty_st_pll_ct(SCLK_FB_DIV, pll->sclk_fb_div, par);
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mdelay(15);
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init_dll(par);
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aty_st_8(GEN_TEST_CNTL+1, 0x00, par);
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mdelay(5);
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aty_st_8(CRTC_GEN_CNTL+3, 0x04, par);
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mdelay(6);
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reset_sdram(par);
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aty_st_8(CRTC_GEN_CNTL+3,
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hsync_enb ? 0x00 : 0x04, par);
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aty_st_pll_ct(SPLL_CNTL2, pll->spll_cntl2, par);
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aty_st_pll_ct(PLL_GEN_CNTL, pll->pll_gen_cntl, par);
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aty_st_pll_ct(PLL_VCLK_CNTL, pll->pll_vclk_cntl, par);
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}
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int atyfb_xl_init(struct fb_info *info)
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{
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const struct xl_card_cfg_t * card = &card_cfg[xl_card];
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struct atyfb_par *par = (struct atyfb_par *) info->par;
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union aty_pll pll;
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int i, err;
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u32 temp;
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aty_st_8(CONFIG_STAT0, 0x85, par);
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mdelay(10);
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/*
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* The following needs to be set before the call
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* to var_to_pll() below. They'll be re-set again
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* to the same values in aty_init().
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*/
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par->ref_clk_per = 100000000UL/card->ref_crystal;
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par->ram_type = card->mem_type;
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info->fix.smem_len = card->mem_size;
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if (xl_card == VICTORIA) {
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// the MCLK, XCLK are 120MHz on victoria card
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par->mclk_per = 1000000/120;
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par->xclk_per = 1000000/120;
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par->features &= ~M64F_MFB_FORCE_4;
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}
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/*
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* Calculate mclk and xclk dividers, etc. The passed
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* pixclock and bpp values don't matter yet, the vclk
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* isn't programmed until later.
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*/
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if ((err = aty_pll_ct.var_to_pll(info, 39726, 8, &pll)))
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return err;
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aty_st_pll_ct(LVDS_CNTL0, 0x00, par);
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aty_st_pll_ct(DLL2_CNTL, card->dll2_cntl, par);
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aty_st_pll_ct(V2PLL_CNTL, 0x10, par);
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aty_st_pll_ct(MPLL_CNTL, MPLL_GAIN, par);
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aty_st_pll_ct(VPLL_CNTL, VPLL_GAIN, par);
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aty_st_pll_ct(PLL_VCLK_CNTL, 0x00, par);
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aty_st_pll_ct(VFC_CNTL, 0x1B, par);
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aty_st_pll_ct(PLL_REF_DIV, pll.ct.pll_ref_div, par);
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aty_st_pll_ct(PLL_EXT_CNTL, pll.ct.pll_ext_cntl, par);
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aty_st_pll_ct(SPLL_CNTL2, 0x03, par);
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aty_st_pll_ct(PLL_GEN_CNTL, 0x44, par);
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reset_clocks(par, &pll.ct, 0);
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mdelay(10);
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aty_st_pll_ct(VCLK_POST_DIV, 0x03, par);
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aty_st_pll_ct(VCLK0_FB_DIV, 0xDA, par);
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aty_st_pll_ct(VCLK_POST_DIV, 0x0F, par);
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aty_st_pll_ct(VCLK1_FB_DIV, 0xF5, par);
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aty_st_pll_ct(VCLK_POST_DIV, 0x3F, par);
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aty_st_pll_ct(PLL_EXT_CNTL, 0x40 | pll.ct.pll_ext_cntl, par);
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aty_st_pll_ct(VCLK2_FB_DIV, 0x00, par);
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aty_st_pll_ct(VCLK_POST_DIV, 0xFF, par);
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aty_st_pll_ct(PLL_EXT_CNTL, 0xC0 | pll.ct.pll_ext_cntl, par);
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aty_st_pll_ct(VCLK3_FB_DIV, 0x00, par);
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aty_st_8(BUS_CNTL, 0x01, par);
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aty_st_le32(BUS_CNTL, card->bus_cntl | 0x08000000, par);
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aty_st_le32(CRTC_GEN_CNTL, 0x04000200, par);
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aty_st_le16(CONFIG_STAT0, 0x0020, par);
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aty_st_le32(MEM_CNTL, 0x10151A33, par);
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aty_st_le32(EXT_MEM_CNTL, 0xE0000C01, par);
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aty_st_le16(CRTC_GEN_CNTL+2, 0x0000, par);
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aty_st_le32(DAC_CNTL, card->dac_cntl, par);
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aty_st_le16(GEN_TEST_CNTL, 0x0100, par);
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aty_st_le32(CUSTOM_MACRO_CNTL, 0x003C0171, par);
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aty_st_le32(MEM_BUF_CNTL, 0x00382848, par);
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aty_st_le32(HW_DEBUG, card->hw_debug, par);
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aty_st_le16(MEM_ADDR_CONFIG, 0x0000, par);
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aty_st_le16(GP_IO+2, 0x0000, par);
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aty_st_le16(GEN_TEST_CNTL, 0x0000, par);
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aty_st_le16(EXT_DAC_REGS+2, 0x0000, par);
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aty_st_le32(CRTC_INT_CNTL, 0x00000000, par);
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aty_st_le32(TIMER_CONFIG, 0x00000000, par);
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aty_st_le32(0xEC, 0x00000000, par);
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aty_st_le32(0xFC, 0x00000000, par);
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for (i=0; i<sizeof(lcd_tbl)/sizeof(lcd_tbl_t); i++) {
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aty_st_lcd(lcd_tbl[i].lcd_reg, lcd_tbl[i].val, par);
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}
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aty_st_le16(CONFIG_STAT0, 0x00A4, par);
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mdelay(10);
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aty_st_8(BUS_CNTL+1, 0xA0, par);
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mdelay(10);
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reset_clocks(par, &pll.ct, 1);
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mdelay(10);
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// something about power management
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aty_st_8(LCD_INDEX, 0x08, par);
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aty_st_8(LCD_DATA, 0x0A, par);
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aty_st_8(LCD_INDEX, 0x08, par);
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aty_st_8(LCD_DATA+3, 0x02, par);
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aty_st_8(LCD_INDEX, 0x08, par);
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aty_st_8(LCD_DATA, 0x0B, par);
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mdelay(2);
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// enable display requests, enable CRTC
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aty_st_8(CRTC_GEN_CNTL+3, 0x02, par);
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// disable display
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aty_st_8(CRTC_GEN_CNTL, 0x40, par);
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// disable display requests, disable CRTC
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aty_st_8(CRTC_GEN_CNTL+3, 0x04, par);
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mdelay(10);
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aty_st_pll_ct(PLL_YCLK_CNTL, 0x25, par);
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aty_st_le16(CUSTOM_MACRO_CNTL, 0x0179, par);
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aty_st_le16(CUSTOM_MACRO_CNTL+2, 0x005E, par);
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aty_st_le16(CUSTOM_MACRO_CNTL+2, card->custom_macro_cntl>>16, par);
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aty_st_8(CUSTOM_MACRO_CNTL+1,
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(card->custom_macro_cntl>>8) & 0xff, par);
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aty_st_le32(MEM_ADDR_CONFIG, card->mem_addr_config, par);
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aty_st_le32(MEM_CNTL, card->mem_cntl, par);
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aty_st_le32(EXT_MEM_CNTL, card->ext_mem_cntl, par);
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aty_st_8(CONFIG_STAT0, 0xA0 | card->mem_type, par);
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aty_st_pll_ct(PLL_YCLK_CNTL, 0x01, par);
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mdelay(15);
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aty_st_pll_ct(PLL_YCLK_CNTL, card->pll_yclk_cntl, par);
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mdelay(1);
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reset_clocks(par, &pll.ct, 0);
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mdelay(50);
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reset_clocks(par, &pll.ct, 0);
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mdelay(50);
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// enable extended register block
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aty_st_8(BUS_CNTL+3, 0x7B, par);
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mdelay(1);
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// disable extended register block
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aty_st_8(BUS_CNTL+3, 0x73, par);
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aty_st_8(CONFIG_STAT0, 0x80 | card->mem_type, par);
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// disable display requests, disable CRTC
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aty_st_8(CRTC_GEN_CNTL+3, 0x04, par);
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// disable mapping registers in VGA aperture
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aty_st_8(CONFIG_CNTL, aty_ld_8(CONFIG_CNTL, par) & ~0x04, par);
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mdelay(50);
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// enable display requests, enable CRTC
|
||
|
|
aty_st_8(CRTC_GEN_CNTL+3, 0x02, par);
|
||
|
|
|
||
|
|
// make GPIO's 14,15,16 all inputs
|
||
|
|
aty_st_8(LCD_INDEX, 0x07, par);
|
||
|
|
aty_st_8(LCD_DATA+3, 0x00, par);
|
||
|
|
|
||
|
|
// enable the display
|
||
|
|
aty_st_8(CRTC_GEN_CNTL, 0x00, par);
|
||
|
|
mdelay(17);
|
||
|
|
// reset the memory controller
|
||
|
|
aty_st_8(GEN_TEST_CNTL+1, 0x02, par);
|
||
|
|
mdelay(15);
|
||
|
|
aty_st_8(GEN_TEST_CNTL+1, 0x00, par);
|
||
|
|
mdelay(30);
|
||
|
|
|
||
|
|
// enable extended register block
|
||
|
|
aty_st_8(BUS_CNTL+3,
|
||
|
|
(u8)(aty_ld_8(BUS_CNTL+3, par) | 0x08),
|
||
|
|
par);
|
||
|
|
// set FIFO size to 512 (PIO)
|
||
|
|
aty_st_le32(GUI_CNTL,
|
||
|
|
aty_ld_le32(GUI_CNTL, par) & ~0x3,
|
||
|
|
par);
|
||
|
|
|
||
|
|
// enable CRT and disable lcd
|
||
|
|
aty_st_8(LCD_INDEX, 0x01, par);
|
||
|
|
temp = aty_ld_le32(LCD_DATA, par);
|
||
|
|
temp = (temp | 0x01) & ~0x02;
|
||
|
|
aty_st_le32(LCD_DATA, temp, par);
|
||
|
|
return 0;
|
||
|
|
}
|
||
|
|
|