2006-06-26 01:25:12 -06:00
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#include <linux/clocksource.h>
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2007-02-16 02:28:04 -07:00
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#include <linux/clockchips.h>
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2006-06-26 01:25:12 -06:00
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#include <linux/errno.h>
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#include <linux/hpet.h>
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#include <linux/init.h>
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2007-03-29 07:46:48 -06:00
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#include <linux/sysdev.h>
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#include <linux/pm.h>
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2006-06-26 01:25:12 -06:00
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#include <asm/hpet.h>
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#include <asm/io.h>
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2007-02-16 02:28:04 -07:00
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extern struct clock_event_device *global_clock_event;
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2006-06-26 01:25:15 -06:00
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#define HPET_MASK CLOCKSOURCE_MASK(32)
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2006-06-26 01:25:12 -06:00
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#define HPET_SHIFT 22
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/* FSEC = 10^-15 NSEC = 10^-9 */
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#define FSEC_PER_NSEC 1000000
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2007-02-16 02:28:04 -07:00
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/*
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* HPET address is set in acpi/boot.c, when an ACPI entry exists
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*/
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unsigned long hpet_address;
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static void __iomem * hpet_virt_address;
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static inline unsigned long hpet_readl(unsigned long a)
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{
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return readl(hpet_virt_address + a);
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}
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static inline void hpet_writel(unsigned long d, unsigned long a)
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{
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writel(d, hpet_virt_address + a);
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}
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/*
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* HPET command line enable / disable
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*/
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static int boot_hpet_disable;
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static int __init hpet_setup(char* str)
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{
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if (str) {
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if (!strncmp("disable", str, 7))
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boot_hpet_disable = 1;
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}
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return 1;
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}
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__setup("hpet=", hpet_setup);
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static inline int is_hpet_capable(void)
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{
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return (!boot_hpet_disable && hpet_address);
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}
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/*
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* HPET timer interrupt enable / disable
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*/
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static int hpet_legacy_int_enabled;
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/**
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* is_hpet_enabled - check whether the hpet timer interrupt is enabled
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*/
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int is_hpet_enabled(void)
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{
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return is_hpet_capable() && hpet_legacy_int_enabled;
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}
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/*
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* When the hpet driver (/dev/hpet) is enabled, we need to reserve
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* timer 0 and timer 1 in case of RTC emulation.
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*/
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#ifdef CONFIG_HPET
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static void hpet_reserve_platform_timers(unsigned long id)
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{
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struct hpet __iomem *hpet = hpet_virt_address;
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struct hpet_timer __iomem *timer = &hpet->hpet_timers[2];
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unsigned int nrtimers, i;
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struct hpet_data hd;
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nrtimers = ((id & HPET_ID_NUMBER) >> HPET_ID_NUMBER_SHIFT) + 1;
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memset(&hd, 0, sizeof (hd));
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hd.hd_phys_address = hpet_address;
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hd.hd_address = hpet_virt_address;
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hd.hd_nirqs = nrtimers;
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hd.hd_flags = HPET_DATA_PLATFORM;
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hpet_reserve_timer(&hd, 0);
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#ifdef CONFIG_HPET_EMULATE_RTC
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hpet_reserve_timer(&hd, 1);
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#endif
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hd.hd_irq[0] = HPET_LEGACY_8254;
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hd.hd_irq[1] = HPET_LEGACY_RTC;
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for (i = 2; i < nrtimers; timer++, i++)
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hd.hd_irq[i] = (timer->hpet_config & Tn_INT_ROUTE_CNF_MASK) >>
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Tn_INT_ROUTE_CNF_SHIFT;
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hpet_alloc(&hd);
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}
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#else
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static void hpet_reserve_platform_timers(unsigned long id) { }
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#endif
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/*
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* Common hpet info
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*/
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static unsigned long hpet_period;
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static void hpet_set_mode(enum clock_event_mode mode,
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struct clock_event_device *evt);
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static int hpet_next_event(unsigned long delta,
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struct clock_event_device *evt);
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/*
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* The hpet clock event device
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*/
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static struct clock_event_device hpet_clockevent = {
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.name = "hpet",
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.features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
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.set_mode = hpet_set_mode,
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.set_next_event = hpet_next_event,
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.shift = 32,
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.irq = 0,
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};
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static void hpet_start_counter(void)
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{
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unsigned long cfg = hpet_readl(HPET_CFG);
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cfg &= ~HPET_CFG_ENABLE;
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hpet_writel(cfg, HPET_CFG);
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hpet_writel(0, HPET_COUNTER);
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hpet_writel(0, HPET_COUNTER + 4);
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cfg |= HPET_CFG_ENABLE;
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hpet_writel(cfg, HPET_CFG);
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}
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static void hpet_enable_int(void)
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{
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unsigned long cfg = hpet_readl(HPET_CFG);
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cfg |= HPET_CFG_LEGACY;
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hpet_writel(cfg, HPET_CFG);
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hpet_legacy_int_enabled = 1;
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}
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static void hpet_set_mode(enum clock_event_mode mode,
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struct clock_event_device *evt)
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{
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unsigned long cfg, cmp, now;
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uint64_t delta;
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switch(mode) {
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case CLOCK_EVT_MODE_PERIODIC:
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delta = ((uint64_t)(NSEC_PER_SEC/HZ)) * hpet_clockevent.mult;
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delta >>= hpet_clockevent.shift;
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now = hpet_readl(HPET_COUNTER);
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cmp = now + (unsigned long) delta;
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cfg = hpet_readl(HPET_T0_CFG);
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cfg |= HPET_TN_ENABLE | HPET_TN_PERIODIC |
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HPET_TN_SETVAL | HPET_TN_32BIT;
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hpet_writel(cfg, HPET_T0_CFG);
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/*
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* The first write after writing TN_SETVAL to the
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* config register sets the counter value, the second
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* write sets the period.
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*/
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hpet_writel(cmp, HPET_T0_CMP);
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udelay(1);
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hpet_writel((unsigned long) delta, HPET_T0_CMP);
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break;
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case CLOCK_EVT_MODE_ONESHOT:
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cfg = hpet_readl(HPET_T0_CFG);
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cfg &= ~HPET_TN_PERIODIC;
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cfg |= HPET_TN_ENABLE | HPET_TN_32BIT;
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hpet_writel(cfg, HPET_T0_CFG);
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break;
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case CLOCK_EVT_MODE_UNUSED:
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case CLOCK_EVT_MODE_SHUTDOWN:
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cfg = hpet_readl(HPET_T0_CFG);
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cfg &= ~HPET_TN_ENABLE;
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hpet_writel(cfg, HPET_T0_CFG);
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break;
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}
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}
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static int hpet_next_event(unsigned long delta,
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struct clock_event_device *evt)
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{
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unsigned long cnt;
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cnt = hpet_readl(HPET_COUNTER);
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cnt += delta;
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hpet_writel(cnt, HPET_T0_CMP);
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2007-03-27 01:08:26 -06:00
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return ((long)(hpet_readl(HPET_COUNTER) - cnt ) > 0) ? -ETIME : 0;
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2007-02-16 02:28:04 -07:00
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}
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2007-03-05 01:30:50 -07:00
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/*
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* Clock source related code
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*/
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static cycle_t read_hpet(void)
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{
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return (cycle_t)hpet_readl(HPET_COUNTER);
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}
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static struct clocksource clocksource_hpet = {
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.name = "hpet",
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.rating = 250,
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.read = read_hpet,
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.mask = HPET_MASK,
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.shift = HPET_SHIFT,
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.flags = CLOCK_SOURCE_IS_CONTINUOUS,
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};
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2007-02-16 02:28:04 -07:00
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/*
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* Try to setup the HPET timer
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*/
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int __init hpet_enable(void)
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{
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unsigned long id;
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uint64_t hpet_freq;
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2007-03-05 01:30:50 -07:00
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u64 tmp;
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2007-02-16 02:28:04 -07:00
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if (!is_hpet_capable())
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return 0;
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hpet_virt_address = ioremap_nocache(hpet_address, HPET_MMAP_SIZE);
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/*
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* Read the period and check for a sane value:
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*/
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hpet_period = hpet_readl(HPET_PERIOD);
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if (hpet_period < HPET_MIN_PERIOD || hpet_period > HPET_MAX_PERIOD)
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goto out_nohpet;
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/*
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* The period is a femto seconds value. We need to calculate the
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* scaled math multiplication factor for nanosecond to hpet tick
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* conversion.
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*/
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hpet_freq = 1000000000000000ULL;
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do_div(hpet_freq, hpet_period);
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hpet_clockevent.mult = div_sc((unsigned long) hpet_freq,
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NSEC_PER_SEC, 32);
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/* Calculate the min / max delta */
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hpet_clockevent.max_delta_ns = clockevent_delta2ns(0x7FFFFFFF,
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&hpet_clockevent);
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hpet_clockevent.min_delta_ns = clockevent_delta2ns(0x30,
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&hpet_clockevent);
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/*
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* Read the HPET ID register to retrieve the IRQ routing
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* information and the number of channels
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*/
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id = hpet_readl(HPET_ID);
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#ifdef CONFIG_HPET_EMULATE_RTC
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/*
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* The legacy routing mode needs at least two channels, tick timer
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* and the rtc emulation channel.
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*/
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if (!(id & HPET_ID_NUMBER))
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goto out_nohpet;
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#endif
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/* Start the counter */
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hpet_start_counter();
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2007-03-05 01:30:50 -07:00
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/* Initialize and register HPET clocksource
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*
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* hpet period is in femto seconds per cycle
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* so we need to convert this to ns/cyc units
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* aproximated by mult/2^shift
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*
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* fsec/cyc * 1nsec/1000000fsec = nsec/cyc = mult/2^shift
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* fsec/cyc * 1ns/1000000fsec * 2^shift = mult
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* fsec/cyc * 2^shift * 1nsec/1000000fsec = mult
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* (fsec/cyc << shift)/1000000 = mult
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* (hpet_period << shift)/FSEC_PER_NSEC = mult
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*/
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tmp = (u64)hpet_period << HPET_SHIFT;
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do_div(tmp, FSEC_PER_NSEC);
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clocksource_hpet.mult = (u32)tmp;
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clocksource_register(&clocksource_hpet);
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2007-02-16 02:28:04 -07:00
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if (id & HPET_ID_LEGSUP) {
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hpet_enable_int();
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hpet_reserve_platform_timers(id);
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/*
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* Start hpet with the boot cpu mask and make it
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* global after the IO_APIC has been initialized.
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*/
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hpet_clockevent.cpumask =cpumask_of_cpu(0);
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clockevents_register_device(&hpet_clockevent);
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global_clock_event = &hpet_clockevent;
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return 1;
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}
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return 0;
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2006-06-26 01:25:12 -06:00
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2007-02-16 02:28:04 -07:00
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out_nohpet:
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iounmap(hpet_virt_address);
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hpet_virt_address = NULL;
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2007-03-29 07:46:48 -06:00
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boot_hpet_disable = 1;
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2007-02-16 02:28:04 -07:00
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return 0;
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}
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#ifdef CONFIG_HPET_EMULATE_RTC
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/* HPET in LegacyReplacement Mode eats up RTC interrupt line. When, HPET
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* is enabled, we support RTC interrupt functionality in software.
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* RTC has 3 kinds of interrupts:
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* 1) Update Interrupt - generate an interrupt, every sec, when RTC clock
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* is updated
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* 2) Alarm Interrupt - generate an interrupt at a specific time of day
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* 3) Periodic Interrupt - generate periodic interrupt, with frequencies
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* 2Hz-8192Hz (2Hz-64Hz for non-root user) (all freqs in powers of 2)
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* (1) and (2) above are implemented using polling at a frequency of
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* 64 Hz. The exact frequency is a tradeoff between accuracy and interrupt
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* overhead. (DEFAULT_RTC_INT_FREQ)
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* For (3), we use interrupts at 64Hz or user specified periodic
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* frequency, whichever is higher.
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*/
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#include <linux/mc146818rtc.h>
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#include <linux/rtc.h>
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#define DEFAULT_RTC_INT_FREQ 64
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#define DEFAULT_RTC_SHIFT 6
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#define RTC_NUM_INTS 1
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static unsigned long hpet_rtc_flags;
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static unsigned long hpet_prev_update_sec;
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static struct rtc_time hpet_alarm_time;
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static unsigned long hpet_pie_count;
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static unsigned long hpet_t1_cmp;
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static unsigned long hpet_default_delta;
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static unsigned long hpet_pie_delta;
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static unsigned long hpet_pie_limit;
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/*
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* Timer 1 for RTC emulation. We use one shot mode, as periodic mode
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* is not supported by all HPET implementations for timer 1.
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*
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* hpet_rtc_timer_init() is called when the rtc is initialized.
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*/
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int hpet_rtc_timer_init(void)
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{
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unsigned long cfg, cnt, delta, flags;
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|
|
if (!is_hpet_enabled())
|
|
|
|
return 0;
|
|
|
|
|
|
|
|
if (!hpet_default_delta) {
|
|
|
|
uint64_t clc;
|
|
|
|
|
|
|
|
clc = (uint64_t) hpet_clockevent.mult * NSEC_PER_SEC;
|
|
|
|
clc >>= hpet_clockevent.shift + DEFAULT_RTC_SHIFT;
|
|
|
|
hpet_default_delta = (unsigned long) clc;
|
|
|
|
}
|
|
|
|
|
|
|
|
if (!(hpet_rtc_flags & RTC_PIE) || hpet_pie_limit)
|
|
|
|
delta = hpet_default_delta;
|
|
|
|
else
|
|
|
|
delta = hpet_pie_delta;
|
|
|
|
|
|
|
|
local_irq_save(flags);
|
|
|
|
|
|
|
|
cnt = delta + hpet_readl(HPET_COUNTER);
|
|
|
|
hpet_writel(cnt, HPET_T1_CMP);
|
|
|
|
hpet_t1_cmp = cnt;
|
|
|
|
|
|
|
|
cfg = hpet_readl(HPET_T1_CFG);
|
|
|
|
cfg &= ~HPET_TN_PERIODIC;
|
|
|
|
cfg |= HPET_TN_ENABLE | HPET_TN_32BIT;
|
|
|
|
hpet_writel(cfg, HPET_T1_CFG);
|
|
|
|
|
|
|
|
local_irq_restore(flags);
|
|
|
|
|
|
|
|
return 1;
|
|
|
|
}
|
|
|
|
|
|
|
|
/*
|
|
|
|
* The functions below are called from rtc driver.
|
|
|
|
* Return 0 if HPET is not being used.
|
|
|
|
* Otherwise do the necessary changes and return 1.
|
|
|
|
*/
|
|
|
|
int hpet_mask_rtc_irq_bit(unsigned long bit_mask)
|
|
|
|
{
|
|
|
|
if (!is_hpet_enabled())
|
|
|
|
return 0;
|
|
|
|
|
|
|
|
hpet_rtc_flags &= ~bit_mask;
|
|
|
|
return 1;
|
|
|
|
}
|
|
|
|
|
|
|
|
int hpet_set_rtc_irq_bit(unsigned long bit_mask)
|
|
|
|
{
|
|
|
|
unsigned long oldbits = hpet_rtc_flags;
|
|
|
|
|
|
|
|
if (!is_hpet_enabled())
|
|
|
|
return 0;
|
|
|
|
|
|
|
|
hpet_rtc_flags |= bit_mask;
|
|
|
|
|
|
|
|
if (!oldbits)
|
|
|
|
hpet_rtc_timer_init();
|
|
|
|
|
|
|
|
return 1;
|
|
|
|
}
|
|
|
|
|
|
|
|
int hpet_set_alarm_time(unsigned char hrs, unsigned char min,
|
|
|
|
unsigned char sec)
|
|
|
|
{
|
|
|
|
if (!is_hpet_enabled())
|
|
|
|
return 0;
|
|
|
|
|
|
|
|
hpet_alarm_time.tm_hour = hrs;
|
|
|
|
hpet_alarm_time.tm_min = min;
|
|
|
|
hpet_alarm_time.tm_sec = sec;
|
|
|
|
|
|
|
|
return 1;
|
|
|
|
}
|
|
|
|
|
|
|
|
int hpet_set_periodic_freq(unsigned long freq)
|
|
|
|
{
|
|
|
|
uint64_t clc;
|
|
|
|
|
|
|
|
if (!is_hpet_enabled())
|
|
|
|
return 0;
|
|
|
|
|
|
|
|
if (freq <= DEFAULT_RTC_INT_FREQ)
|
|
|
|
hpet_pie_limit = DEFAULT_RTC_INT_FREQ / freq;
|
|
|
|
else {
|
|
|
|
clc = (uint64_t) hpet_clockevent.mult * NSEC_PER_SEC;
|
|
|
|
do_div(clc, freq);
|
|
|
|
clc >>= hpet_clockevent.shift;
|
|
|
|
hpet_pie_delta = (unsigned long) clc;
|
|
|
|
}
|
|
|
|
return 1;
|
|
|
|
}
|
|
|
|
|
|
|
|
int hpet_rtc_dropped_irq(void)
|
|
|
|
{
|
|
|
|
return is_hpet_enabled();
|
|
|
|
}
|
|
|
|
|
|
|
|
static void hpet_rtc_timer_reinit(void)
|
|
|
|
{
|
|
|
|
unsigned long cfg, delta;
|
|
|
|
int lost_ints = -1;
|
|
|
|
|
|
|
|
if (unlikely(!hpet_rtc_flags)) {
|
|
|
|
cfg = hpet_readl(HPET_T1_CFG);
|
|
|
|
cfg &= ~HPET_TN_ENABLE;
|
|
|
|
hpet_writel(cfg, HPET_T1_CFG);
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
|
|
|
|
if (!(hpet_rtc_flags & RTC_PIE) || hpet_pie_limit)
|
|
|
|
delta = hpet_default_delta;
|
|
|
|
else
|
|
|
|
delta = hpet_pie_delta;
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Increment the comparator value until we are ahead of the
|
|
|
|
* current count.
|
|
|
|
*/
|
|
|
|
do {
|
|
|
|
hpet_t1_cmp += delta;
|
|
|
|
hpet_writel(hpet_t1_cmp, HPET_T1_CMP);
|
|
|
|
lost_ints++;
|
|
|
|
} while ((long)(hpet_readl(HPET_COUNTER) - hpet_t1_cmp) > 0);
|
|
|
|
|
|
|
|
if (lost_ints) {
|
|
|
|
if (hpet_rtc_flags & RTC_PIE)
|
|
|
|
hpet_pie_count += lost_ints;
|
|
|
|
if (printk_ratelimit())
|
|
|
|
printk(KERN_WARNING "rtc: lost %d interrupts\n",
|
|
|
|
lost_ints);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
irqreturn_t hpet_rtc_interrupt(int irq, void *dev_id)
|
|
|
|
{
|
|
|
|
struct rtc_time curr_time;
|
|
|
|
unsigned long rtc_int_flag = 0;
|
|
|
|
|
|
|
|
hpet_rtc_timer_reinit();
|
|
|
|
|
|
|
|
if (hpet_rtc_flags & (RTC_UIE | RTC_AIE))
|
|
|
|
rtc_get_rtc_time(&curr_time);
|
|
|
|
|
|
|
|
if (hpet_rtc_flags & RTC_UIE &&
|
|
|
|
curr_time.tm_sec != hpet_prev_update_sec) {
|
|
|
|
rtc_int_flag = RTC_UF;
|
|
|
|
hpet_prev_update_sec = curr_time.tm_sec;
|
|
|
|
}
|
|
|
|
|
|
|
|
if (hpet_rtc_flags & RTC_PIE &&
|
|
|
|
++hpet_pie_count >= hpet_pie_limit) {
|
|
|
|
rtc_int_flag |= RTC_PF;
|
|
|
|
hpet_pie_count = 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
if (hpet_rtc_flags & RTC_PIE &&
|
|
|
|
(curr_time.tm_sec == hpet_alarm_time.tm_sec) &&
|
|
|
|
(curr_time.tm_min == hpet_alarm_time.tm_min) &&
|
|
|
|
(curr_time.tm_hour == hpet_alarm_time.tm_hour))
|
|
|
|
rtc_int_flag |= RTC_AF;
|
|
|
|
|
|
|
|
if (rtc_int_flag) {
|
|
|
|
rtc_int_flag |= (RTC_IRQF | (RTC_NUM_INTS << 8));
|
|
|
|
rtc_interrupt(rtc_int_flag, dev_id);
|
|
|
|
}
|
|
|
|
return IRQ_HANDLED;
|
|
|
|
}
|
|
|
|
#endif
|
2007-03-29 07:46:48 -06:00
|
|
|
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Suspend/resume part
|
|
|
|
*/
|
|
|
|
|
|
|
|
#ifdef CONFIG_PM
|
|
|
|
|
|
|
|
static int hpet_suspend(struct sys_device *sys_device, pm_message_t state)
|
|
|
|
{
|
|
|
|
unsigned long cfg = hpet_readl(HPET_CFG);
|
|
|
|
|
|
|
|
cfg &= ~(HPET_CFG_ENABLE|HPET_CFG_LEGACY);
|
|
|
|
hpet_writel(cfg, HPET_CFG);
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int hpet_resume(struct sys_device *sys_device)
|
|
|
|
{
|
|
|
|
unsigned int id;
|
|
|
|
|
|
|
|
hpet_start_counter();
|
|
|
|
|
|
|
|
id = hpet_readl(HPET_ID);
|
|
|
|
|
|
|
|
if (id & HPET_ID_LEGSUP)
|
|
|
|
hpet_enable_int();
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static struct sysdev_class hpet_class = {
|
|
|
|
set_kset_name("hpet"),
|
|
|
|
.suspend = hpet_suspend,
|
|
|
|
.resume = hpet_resume,
|
|
|
|
};
|
|
|
|
|
|
|
|
static struct sys_device hpet_device = {
|
|
|
|
.id = 0,
|
|
|
|
.cls = &hpet_class,
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
|
|
static __init int hpet_register_sysfs(void)
|
|
|
|
{
|
|
|
|
int err;
|
|
|
|
|
|
|
|
if (!is_hpet_capable())
|
|
|
|
return 0;
|
|
|
|
|
|
|
|
err = sysdev_class_register(&hpet_class);
|
|
|
|
|
|
|
|
if (!err) {
|
|
|
|
err = sysdev_register(&hpet_device);
|
|
|
|
if (err)
|
|
|
|
sysdev_class_unregister(&hpet_class);
|
|
|
|
}
|
|
|
|
|
|
|
|
return err;
|
|
|
|
}
|
|
|
|
|
|
|
|
device_initcall(hpet_register_sysfs);
|
|
|
|
|
|
|
|
#endif
|