2009-09-02 08:37:17 -06:00
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/*
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* apb_timer.c: Driver for Langwell APB timers
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*
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* (C) Copyright 2009 Intel Corporation
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* Author: Jacob Pan (jacob.jun.pan@intel.com)
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; version 2
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* of the License.
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*
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* Note:
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* Langwell is the south complex of Intel Moorestown MID platform. There are
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* eight external timers in total that can be used by the operating system.
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* The timer information, such as frequency and addresses, is provided to the
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* OS via SFI tables.
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* Timer interrupts are routed via FW/HW emulated IOAPIC independently via
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* individual redirection table entries (RTE).
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* Unlike HPET, there is no master counter, therefore one of the timers are
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* used as clocksource. The overall allocation looks like:
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* - timer 0 - NR_CPUs for per cpu timer
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* - one timer for clocksource
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* - one timer for watchdog driver.
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* It is also worth notice that APB timer does not support true one-shot mode,
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* free-running mode will be used here to emulate one-shot mode.
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* APB timer can also be used as broadcast timer along with per cpu local APIC
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* timer, but by default APB timer has higher rating than local APIC timers.
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*/
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#include <linux/clocksource.h>
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#include <linux/clockchips.h>
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#include <linux/delay.h>
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#include <linux/errno.h>
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#include <linux/init.h>
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#include <linux/sysdev.h>
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include cleanup: Update gfp.h and slab.h includes to prepare for breaking implicit slab.h inclusion from percpu.h
percpu.h is included by sched.h and module.h and thus ends up being
included when building most .c files. percpu.h includes slab.h which
in turn includes gfp.h making everything defined by the two files
universally available and complicating inclusion dependencies.
percpu.h -> slab.h dependency is about to be removed. Prepare for
this change by updating users of gfp and slab facilities include those
headers directly instead of assuming availability. As this conversion
needs to touch large number of source files, the following script is
used as the basis of conversion.
http://userweb.kernel.org/~tj/misc/slabh-sweep.py
The script does the followings.
* Scan files for gfp and slab usages and update includes such that
only the necessary includes are there. ie. if only gfp is used,
gfp.h, if slab is used, slab.h.
* When the script inserts a new include, it looks at the include
blocks and try to put the new include such that its order conforms
to its surrounding. It's put in the include block which contains
core kernel includes, in the same order that the rest are ordered -
alphabetical, Christmas tree, rev-Xmas-tree or at the end if there
doesn't seem to be any matching order.
* If the script can't find a place to put a new include (mostly
because the file doesn't have fitting include block), it prints out
an error message indicating which .h file needs to be added to the
file.
The conversion was done in the following steps.
1. The initial automatic conversion of all .c files updated slightly
over 4000 files, deleting around 700 includes and adding ~480 gfp.h
and ~3000 slab.h inclusions. The script emitted errors for ~400
files.
2. Each error was manually checked. Some didn't need the inclusion,
some needed manual addition while adding it to implementation .h or
embedding .c file was more appropriate for others. This step added
inclusions to around 150 files.
3. The script was run again and the output was compared to the edits
from #2 to make sure no file was left behind.
4. Several build tests were done and a couple of problems were fixed.
e.g. lib/decompress_*.c used malloc/free() wrappers around slab
APIs requiring slab.h to be added manually.
5. The script was run on all .h files but without automatically
editing them as sprinkling gfp.h and slab.h inclusions around .h
files could easily lead to inclusion dependency hell. Most gfp.h
inclusion directives were ignored as stuff from gfp.h was usually
wildly available and often used in preprocessor macros. Each
slab.h inclusion directive was examined and added manually as
necessary.
6. percpu.h was updated not to include slab.h.
7. Build test were done on the following configurations and failures
were fixed. CONFIG_GCOV_KERNEL was turned off for all tests (as my
distributed build env didn't work with gcov compiles) and a few
more options had to be turned off depending on archs to make things
build (like ipr on powerpc/64 which failed due to missing writeq).
* x86 and x86_64 UP and SMP allmodconfig and a custom test config.
* powerpc and powerpc64 SMP allmodconfig
* sparc and sparc64 SMP allmodconfig
* ia64 SMP allmodconfig
* s390 SMP allmodconfig
* alpha SMP allmodconfig
* um on x86_64 SMP allmodconfig
8. percpu.h modifications were reverted so that it could be applied as
a separate patch and serve as bisection point.
Given the fact that I had only a couple of failures from tests on step
6, I'm fairly confident about the coverage of this conversion patch.
If there is a breakage, it's likely to be something in one of the arch
headers which should be easily discoverable easily on most builds of
the specific arch.
Signed-off-by: Tejun Heo <tj@kernel.org>
Guess-its-ok-by: Christoph Lameter <cl@linux-foundation.org>
Cc: Ingo Molnar <mingo@redhat.com>
Cc: Lee Schermerhorn <Lee.Schermerhorn@hp.com>
2010-03-24 02:04:11 -06:00
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#include <linux/slab.h>
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2009-09-02 08:37:17 -06:00
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#include <linux/pm.h>
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#include <linux/pci.h>
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#include <linux/sfi.h>
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#include <linux/interrupt.h>
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#include <linux/cpu.h>
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#include <linux/irq.h>
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#include <asm/fixmap.h>
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#include <asm/apb_timer.h>
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2010-03-03 14:38:48 -07:00
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#define APBT_MASK CLOCKSOURCE_MASK(32)
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#define APBT_SHIFT 22
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#define APBT_CLOCKEVENT_RATING 150
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#define APBT_CLOCKSOURCE_RATING 250
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#define APBT_MIN_DELTA_USEC 200
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2009-09-02 08:37:17 -06:00
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#define EVT_TO_APBT_DEV(evt) container_of(evt, struct apbt_dev, evt)
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#define APBT_CLOCKEVENT0_NUM (0)
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#define APBT_CLOCKEVENT1_NUM (1)
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#define APBT_CLOCKSOURCE_NUM (2)
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static unsigned long apbt_address;
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static int apb_timer_block_enabled;
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static void __iomem *apbt_virt_address;
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static int phy_cs_timer_id;
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/*
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* Common DW APB timer info
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*/
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static uint64_t apbt_freq;
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static void apbt_set_mode(enum clock_event_mode mode,
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2010-03-03 14:38:48 -07:00
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struct clock_event_device *evt);
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2009-09-02 08:37:17 -06:00
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static int apbt_next_event(unsigned long delta,
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2010-03-03 14:38:48 -07:00
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struct clock_event_device *evt);
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2009-09-02 08:37:17 -06:00
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static cycle_t apbt_read_clocksource(struct clocksource *cs);
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Merge branch 'x86-mrst-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/linux-2.6-tip
* 'x86-mrst-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/linux-2.6-tip: (30 commits)
x86, mrst: Fix whitespace breakage in apb_timer.c
x86, mrst: Fix APB timer per cpu clockevent
x86, mrst: Remove X86_MRST dependency on PCI_IOAPIC
x86, olpc: Use pci subarch init for OLPC
x86, pci: Add arch_init to x86_init abstraction
x86, mrst: Add Kconfig dependencies for Moorestown
x86, pci: Exclude Moorestown PCI code if CONFIG_X86_MRST=n
x86, numaq: Make CONFIG_X86_NUMAQ depend on CONFIG_PCI
x86, pci: Add sanity check for PCI fixed bar probing
x86, legacy_irq: Remove duplicate vector assigment
x86, legacy_irq: Remove left over nr_legacy_irqs
x86, mrst: Platform clock setup code
x86, apbt: Moorestown APB system timer driver
x86, mrst: Add vrtc platform data setup code
x86, mrst: Add platform timer info parsing code
x86, mrst: Fill in PCI functions in x86_init layer
x86, mrst: Add dummy legacy pic to platform setup
x86/PCI: Moorestown PCI support
x86, ioapic: Add dummy ioapic functions
x86, ioapic: Early enable ioapic for timer irq
...
Fixed up semantic conflict of new clocksources due to commit
17622339af25 ("clocksource: add argument to resume callback").
2010-03-07 16:59:39 -07:00
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static void apbt_restart_clocksource(struct clocksource *cs);
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2009-09-02 08:37:17 -06:00
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struct apbt_dev {
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2010-03-03 14:38:48 -07:00
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struct clock_event_device evt;
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unsigned int num;
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int cpu;
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unsigned int irq;
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unsigned int tick;
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unsigned int count;
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unsigned int flags;
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char name[10];
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2009-09-02 08:37:17 -06:00
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};
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int disable_apbt_percpu __cpuinitdata;
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2010-03-02 22:01:34 -07:00
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static DEFINE_PER_CPU(struct apbt_dev, cpu_apbt_dev);
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2009-09-02 08:37:17 -06:00
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#ifdef CONFIG_SMP
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static unsigned int apbt_num_timers_used;
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static struct apbt_dev *apbt_devs;
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#endif
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2010-03-03 14:38:48 -07:00
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static inline unsigned long apbt_readl_reg(unsigned long a)
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2009-09-02 08:37:17 -06:00
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{
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2010-03-03 14:38:48 -07:00
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return readl(apbt_virt_address + a);
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2009-09-02 08:37:17 -06:00
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}
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static inline void apbt_writel_reg(unsigned long d, unsigned long a)
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{
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2010-03-03 14:38:48 -07:00
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writel(d, apbt_virt_address + a);
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2009-09-02 08:37:17 -06:00
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}
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static inline unsigned long apbt_readl(int n, unsigned long a)
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{
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2010-03-03 14:38:48 -07:00
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return readl(apbt_virt_address + a + n * APBTMRS_REG_SIZE);
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2009-09-02 08:37:17 -06:00
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}
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static inline void apbt_writel(int n, unsigned long d, unsigned long a)
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{
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2010-03-03 14:38:48 -07:00
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writel(d, apbt_virt_address + a + n * APBTMRS_REG_SIZE);
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2009-09-02 08:37:17 -06:00
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}
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static inline void apbt_set_mapping(void)
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{
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2010-03-03 14:38:48 -07:00
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struct sfi_timer_table_entry *mtmr;
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if (apbt_virt_address) {
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pr_debug("APBT base already mapped\n");
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return;
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}
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mtmr = sfi_get_mtmr(APBT_CLOCKEVENT0_NUM);
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if (mtmr == NULL) {
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printk(KERN_ERR "Failed to get MTMR %d from SFI\n",
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APBT_CLOCKEVENT0_NUM);
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return;
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}
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apbt_address = (unsigned long)mtmr->phys_addr;
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if (!apbt_address) {
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printk(KERN_WARNING "No timer base from SFI, use default\n");
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apbt_address = APBT_DEFAULT_BASE;
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}
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apbt_virt_address = ioremap_nocache(apbt_address, APBT_MMAP_SIZE);
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if (apbt_virt_address) {
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pr_debug("Mapped APBT physical addr %p at virtual addr %p\n",\
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(void *)apbt_address, (void *)apbt_virt_address);
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} else {
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pr_debug("Failed mapping APBT phy address at %p\n",\
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(void *)apbt_address);
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goto panic_noapbt;
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}
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apbt_freq = mtmr->freq_hz / USEC_PER_SEC;
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sfi_free_mtmr(mtmr);
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/* Now figure out the physical timer id for clocksource device */
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mtmr = sfi_get_mtmr(APBT_CLOCKSOURCE_NUM);
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if (mtmr == NULL)
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goto panic_noapbt;
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/* Now figure out the physical timer id */
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phy_cs_timer_id = (unsigned int)(mtmr->phys_addr & 0xff)
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/ APBTMRS_REG_SIZE;
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pr_debug("Use timer %d for clocksource\n", phy_cs_timer_id);
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return;
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2009-09-02 08:37:17 -06:00
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panic_noapbt:
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2010-03-03 14:38:48 -07:00
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panic("Failed to setup APB system timer\n");
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2009-09-02 08:37:17 -06:00
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}
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static inline void apbt_clear_mapping(void)
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{
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2010-03-03 14:38:48 -07:00
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iounmap(apbt_virt_address);
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apbt_virt_address = NULL;
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2009-09-02 08:37:17 -06:00
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}
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/*
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* APBT timer interrupt enable / disable
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*/
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static inline int is_apbt_capable(void)
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{
|
2010-03-03 14:38:48 -07:00
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return apbt_virt_address ? 1 : 0;
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2009-09-02 08:37:17 -06:00
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}
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static struct clocksource clocksource_apbt = {
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2010-03-03 14:38:48 -07:00
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.name = "apbt",
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.rating = APBT_CLOCKSOURCE_RATING,
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.read = apbt_read_clocksource,
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.mask = APBT_MASK,
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.shift = APBT_SHIFT,
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.flags = CLOCK_SOURCE_IS_CONTINUOUS,
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.resume = apbt_restart_clocksource,
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2009-09-02 08:37:17 -06:00
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};
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/* boot APB clock event device */
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static struct clock_event_device apbt_clockevent = {
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2010-03-03 14:38:48 -07:00
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.name = "apbt0",
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.features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
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.set_mode = apbt_set_mode,
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.set_next_event = apbt_next_event,
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.shift = APBT_SHIFT,
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.irq = 0,
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.rating = APBT_CLOCKEVENT_RATING,
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2009-09-02 08:37:17 -06:00
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};
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/*
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* if user does not want to use per CPU apb timer, just give it a lower rating
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* than local apic timer and skip the late per cpu timer init.
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*/
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static inline int __init setup_x86_mrst_timer(char *arg)
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{
|
2010-03-03 14:38:48 -07:00
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if (!arg)
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return -EINVAL;
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if (strcmp("apbt_only", arg) == 0)
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disable_apbt_percpu = 0;
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else if (strcmp("lapic_and_apbt", arg) == 0)
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disable_apbt_percpu = 1;
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else {
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pr_warning("X86 MRST timer option %s not recognised"
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" use x86_mrst_timer=apbt_only or lapic_and_apbt\n",
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arg);
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return -EINVAL;
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}
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return 0;
|
2009-09-02 08:37:17 -06:00
|
|
|
}
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|
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__setup("x86_mrst_timer=", setup_x86_mrst_timer);
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|
|
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|
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/*
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|
|
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* start count down from 0xffff_ffff. this is done by toggling the enable bit
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* then load initial load count to ~0.
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|
*/
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|
|
static void apbt_start_counter(int n)
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|
|
{
|
2010-03-03 14:38:48 -07:00
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unsigned long ctrl = apbt_readl(n, APBTMR_N_CONTROL);
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ctrl &= ~APBTMR_CONTROL_ENABLE;
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apbt_writel(n, ctrl, APBTMR_N_CONTROL);
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apbt_writel(n, ~0, APBTMR_N_LOAD_COUNT);
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|
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/* enable, mask interrupt */
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ctrl &= ~APBTMR_CONTROL_MODE_PERIODIC;
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|
|
ctrl |= (APBTMR_CONTROL_ENABLE | APBTMR_CONTROL_INT);
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|
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apbt_writel(n, ctrl, APBTMR_N_CONTROL);
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|
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/* read it once to get cached counter value initialized */
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|
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apbt_read_clocksource(&clocksource_apbt);
|
2009-09-02 08:37:17 -06:00
|
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|
}
|
|
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|
|
static irqreturn_t apbt_interrupt_handler(int irq, void *data)
|
|
|
|
{
|
2010-03-03 14:38:48 -07:00
|
|
|
struct apbt_dev *dev = (struct apbt_dev *)data;
|
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|
struct clock_event_device *aevt = &dev->evt;
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|
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|
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if (!aevt->event_handler) {
|
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|
|
printk(KERN_INFO "Spurious APBT timer interrupt on %d\n",
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|
|
dev->num);
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|
|
return IRQ_NONE;
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|
|
|
}
|
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|
|
aevt->event_handler(aevt);
|
|
|
|
return IRQ_HANDLED;
|
2009-09-02 08:37:17 -06:00
|
|
|
}
|
|
|
|
|
Merge branch 'x86-mrst-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/linux-2.6-tip
* 'x86-mrst-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/linux-2.6-tip: (30 commits)
x86, mrst: Fix whitespace breakage in apb_timer.c
x86, mrst: Fix APB timer per cpu clockevent
x86, mrst: Remove X86_MRST dependency on PCI_IOAPIC
x86, olpc: Use pci subarch init for OLPC
x86, pci: Add arch_init to x86_init abstraction
x86, mrst: Add Kconfig dependencies for Moorestown
x86, pci: Exclude Moorestown PCI code if CONFIG_X86_MRST=n
x86, numaq: Make CONFIG_X86_NUMAQ depend on CONFIG_PCI
x86, pci: Add sanity check for PCI fixed bar probing
x86, legacy_irq: Remove duplicate vector assigment
x86, legacy_irq: Remove left over nr_legacy_irqs
x86, mrst: Platform clock setup code
x86, apbt: Moorestown APB system timer driver
x86, mrst: Add vrtc platform data setup code
x86, mrst: Add platform timer info parsing code
x86, mrst: Fill in PCI functions in x86_init layer
x86, mrst: Add dummy legacy pic to platform setup
x86/PCI: Moorestown PCI support
x86, ioapic: Add dummy ioapic functions
x86, ioapic: Early enable ioapic for timer irq
...
Fixed up semantic conflict of new clocksources due to commit
17622339af25 ("clocksource: add argument to resume callback").
2010-03-07 16:59:39 -07:00
|
|
|
static void apbt_restart_clocksource(struct clocksource *cs)
|
2009-09-02 08:37:17 -06:00
|
|
|
{
|
2010-03-03 14:38:48 -07:00
|
|
|
apbt_start_counter(phy_cs_timer_id);
|
2009-09-02 08:37:17 -06:00
|
|
|
}
|
|
|
|
|
|
|
|
/* Setup IRQ routing via IOAPIC */
|
|
|
|
#ifdef CONFIG_SMP
|
|
|
|
static void apbt_setup_irq(struct apbt_dev *adev)
|
|
|
|
{
|
2010-03-03 14:38:48 -07:00
|
|
|
struct irq_chip *chip;
|
|
|
|
struct irq_desc *desc;
|
|
|
|
|
|
|
|
/* timer0 irq has been setup early */
|
|
|
|
if (adev->irq == 0)
|
|
|
|
return;
|
|
|
|
desc = irq_to_desc(adev->irq);
|
|
|
|
chip = get_irq_chip(adev->irq);
|
|
|
|
disable_irq(adev->irq);
|
|
|
|
desc->status |= IRQ_MOVE_PCNTXT;
|
|
|
|
irq_set_affinity(adev->irq, cpumask_of(adev->cpu));
|
|
|
|
/* APB timer irqs are set up as mp_irqs, timer is edge triggerred */
|
|
|
|
set_irq_chip_and_handler_name(adev->irq, chip, handle_edge_irq, "edge");
|
|
|
|
enable_irq(adev->irq);
|
|
|
|
if (system_state == SYSTEM_BOOTING)
|
|
|
|
if (request_irq(adev->irq, apbt_interrupt_handler,
|
|
|
|
IRQF_TIMER | IRQF_DISABLED | IRQF_NOBALANCING,
|
|
|
|
adev->name, adev)) {
|
|
|
|
printk(KERN_ERR "Failed request IRQ for APBT%d\n",
|
|
|
|
adev->num);
|
|
|
|
}
|
2009-09-02 08:37:17 -06:00
|
|
|
}
|
|
|
|
#endif
|
|
|
|
|
|
|
|
static void apbt_enable_int(int n)
|
|
|
|
{
|
2010-03-03 14:38:48 -07:00
|
|
|
unsigned long ctrl = apbt_readl(n, APBTMR_N_CONTROL);
|
|
|
|
/* clear pending intr */
|
|
|
|
apbt_readl(n, APBTMR_N_EOI);
|
|
|
|
ctrl &= ~APBTMR_CONTROL_INT;
|
|
|
|
apbt_writel(n, ctrl, APBTMR_N_CONTROL);
|
2009-09-02 08:37:17 -06:00
|
|
|
}
|
|
|
|
|
|
|
|
static void apbt_disable_int(int n)
|
|
|
|
{
|
2010-03-03 14:38:48 -07:00
|
|
|
unsigned long ctrl = apbt_readl(n, APBTMR_N_CONTROL);
|
2009-09-02 08:37:17 -06:00
|
|
|
|
2010-03-03 14:38:48 -07:00
|
|
|
ctrl |= APBTMR_CONTROL_INT;
|
|
|
|
apbt_writel(n, ctrl, APBTMR_N_CONTROL);
|
2009-09-02 08:37:17 -06:00
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
static int __init apbt_clockevent_register(void)
|
|
|
|
{
|
2010-03-03 14:38:48 -07:00
|
|
|
struct sfi_timer_table_entry *mtmr;
|
|
|
|
struct apbt_dev *adev = &__get_cpu_var(cpu_apbt_dev);
|
|
|
|
|
|
|
|
mtmr = sfi_get_mtmr(APBT_CLOCKEVENT0_NUM);
|
|
|
|
if (mtmr == NULL) {
|
|
|
|
printk(KERN_ERR "Failed to get MTMR %d from SFI\n",
|
|
|
|
APBT_CLOCKEVENT0_NUM);
|
|
|
|
return -ENODEV;
|
|
|
|
}
|
|
|
|
|
|
|
|
/*
|
|
|
|
* We need to calculate the scaled math multiplication factor for
|
|
|
|
* nanosecond to apbt tick conversion.
|
|
|
|
* mult = (nsec/cycle)*2^APBT_SHIFT
|
|
|
|
*/
|
|
|
|
apbt_clockevent.mult = div_sc((unsigned long) mtmr->freq_hz
|
|
|
|
, NSEC_PER_SEC, APBT_SHIFT);
|
|
|
|
|
|
|
|
/* Calculate the min / max delta */
|
|
|
|
apbt_clockevent.max_delta_ns = clockevent_delta2ns(0x7FFFFFFF,
|
|
|
|
&apbt_clockevent);
|
|
|
|
apbt_clockevent.min_delta_ns = clockevent_delta2ns(
|
|
|
|
APBT_MIN_DELTA_USEC*apbt_freq,
|
|
|
|
&apbt_clockevent);
|
|
|
|
/*
|
|
|
|
* Start apbt with the boot cpu mask and make it
|
|
|
|
* global if not used for per cpu timer.
|
|
|
|
*/
|
|
|
|
apbt_clockevent.cpumask = cpumask_of(smp_processor_id());
|
|
|
|
adev->num = smp_processor_id();
|
|
|
|
memcpy(&adev->evt, &apbt_clockevent, sizeof(struct clock_event_device));
|
|
|
|
|
|
|
|
if (disable_apbt_percpu) {
|
|
|
|
apbt_clockevent.rating = APBT_CLOCKEVENT_RATING - 100;
|
2010-03-02 22:01:34 -07:00
|
|
|
global_clock_event = &adev->evt;
|
2010-03-03 14:38:48 -07:00
|
|
|
printk(KERN_DEBUG "%s clockevent registered as global\n",
|
|
|
|
global_clock_event->name);
|
|
|
|
}
|
|
|
|
|
|
|
|
if (request_irq(apbt_clockevent.irq, apbt_interrupt_handler,
|
|
|
|
IRQF_TIMER | IRQF_DISABLED | IRQF_NOBALANCING,
|
|
|
|
apbt_clockevent.name, adev)) {
|
|
|
|
printk(KERN_ERR "Failed request IRQ for APBT%d\n",
|
|
|
|
apbt_clockevent.irq);
|
|
|
|
}
|
|
|
|
|
|
|
|
clockevents_register_device(&adev->evt);
|
|
|
|
/* Start APBT 0 interrupts */
|
|
|
|
apbt_enable_int(APBT_CLOCKEVENT0_NUM);
|
|
|
|
|
|
|
|
sfi_free_mtmr(mtmr);
|
|
|
|
return 0;
|
2009-09-02 08:37:17 -06:00
|
|
|
}
|
|
|
|
|
|
|
|
#ifdef CONFIG_SMP
|
|
|
|
/* Should be called with per cpu */
|
|
|
|
void apbt_setup_secondary_clock(void)
|
|
|
|
{
|
2010-03-03 14:38:48 -07:00
|
|
|
struct apbt_dev *adev;
|
|
|
|
struct clock_event_device *aevt;
|
|
|
|
int cpu;
|
|
|
|
|
|
|
|
/* Don't register boot CPU clockevent */
|
|
|
|
cpu = smp_processor_id();
|
|
|
|
if (cpu == boot_cpu_id)
|
|
|
|
return;
|
|
|
|
/*
|
|
|
|
* We need to calculate the scaled math multiplication factor for
|
|
|
|
* nanosecond to apbt tick conversion.
|
|
|
|
* mult = (nsec/cycle)*2^APBT_SHIFT
|
|
|
|
*/
|
|
|
|
printk(KERN_INFO "Init per CPU clockevent %d\n", cpu);
|
|
|
|
adev = &per_cpu(cpu_apbt_dev, cpu);
|
|
|
|
aevt = &adev->evt;
|
|
|
|
|
|
|
|
memcpy(aevt, &apbt_clockevent, sizeof(*aevt));
|
|
|
|
aevt->cpumask = cpumask_of(cpu);
|
|
|
|
aevt->name = adev->name;
|
|
|
|
aevt->mode = CLOCK_EVT_MODE_UNUSED;
|
|
|
|
|
|
|
|
printk(KERN_INFO "Registering CPU %d clockevent device %s, mask %08x\n",
|
|
|
|
cpu, aevt->name, *(u32 *)aevt->cpumask);
|
|
|
|
|
|
|
|
apbt_setup_irq(adev);
|
|
|
|
|
|
|
|
clockevents_register_device(aevt);
|
|
|
|
|
|
|
|
apbt_enable_int(cpu);
|
|
|
|
|
|
|
|
return;
|
2009-09-02 08:37:17 -06:00
|
|
|
}
|
|
|
|
|
|
|
|
/*
|
|
|
|
* this notify handler process CPU hotplug events. in case of S0i3, nonboot
|
|
|
|
* cpus are disabled/enabled frequently, for performance reasons, we keep the
|
|
|
|
* per cpu timer irq registered so that we do need to do free_irq/request_irq.
|
|
|
|
*
|
|
|
|
* TODO: it might be more reliable to directly disable percpu clockevent device
|
|
|
|
* without the notifier chain. currently, cpu 0 may get interrupts from other
|
|
|
|
* cpu timers during the offline process due to the ordering of notification.
|
|
|
|
* the extra interrupt is harmless.
|
|
|
|
*/
|
|
|
|
static int apbt_cpuhp_notify(struct notifier_block *n,
|
2010-03-03 14:38:48 -07:00
|
|
|
unsigned long action, void *hcpu)
|
2009-09-02 08:37:17 -06:00
|
|
|
{
|
2010-03-03 14:38:48 -07:00
|
|
|
unsigned long cpu = (unsigned long)hcpu;
|
|
|
|
struct apbt_dev *adev = &per_cpu(cpu_apbt_dev, cpu);
|
|
|
|
|
|
|
|
switch (action & 0xf) {
|
|
|
|
case CPU_DEAD:
|
|
|
|
apbt_disable_int(cpu);
|
|
|
|
if (system_state == SYSTEM_RUNNING)
|
|
|
|
pr_debug("skipping APBT CPU %lu offline\n", cpu);
|
|
|
|
else if (adev) {
|
|
|
|
pr_debug("APBT clockevent for cpu %lu offline\n", cpu);
|
|
|
|
free_irq(adev->irq, adev);
|
|
|
|
}
|
|
|
|
break;
|
|
|
|
default:
|
|
|
|
pr_debug(KERN_INFO "APBT notified %lu, no action\n", action);
|
|
|
|
}
|
|
|
|
return NOTIFY_OK;
|
2009-09-02 08:37:17 -06:00
|
|
|
}
|
|
|
|
|
|
|
|
static __init int apbt_late_init(void)
|
|
|
|
{
|
2010-04-19 12:23:43 -06:00
|
|
|
if (disable_apbt_percpu || !apb_timer_block_enabled)
|
2010-03-03 14:38:48 -07:00
|
|
|
return 0;
|
|
|
|
/* This notifier should be called after workqueue is ready */
|
|
|
|
hotcpu_notifier(apbt_cpuhp_notify, -20);
|
|
|
|
return 0;
|
2009-09-02 08:37:17 -06:00
|
|
|
}
|
|
|
|
fs_initcall(apbt_late_init);
|
|
|
|
#else
|
|
|
|
|
|
|
|
void apbt_setup_secondary_clock(void) {}
|
|
|
|
|
|
|
|
#endif /* CONFIG_SMP */
|
|
|
|
|
|
|
|
static void apbt_set_mode(enum clock_event_mode mode,
|
2010-03-03 14:38:48 -07:00
|
|
|
struct clock_event_device *evt)
|
2009-09-02 08:37:17 -06:00
|
|
|
{
|
2010-03-03 14:38:48 -07:00
|
|
|
unsigned long ctrl;
|
|
|
|
uint64_t delta;
|
|
|
|
int timer_num;
|
|
|
|
struct apbt_dev *adev = EVT_TO_APBT_DEV(evt);
|
|
|
|
|
|
|
|
timer_num = adev->num;
|
|
|
|
pr_debug("%s CPU %d timer %d mode=%d\n",
|
|
|
|
__func__, first_cpu(*evt->cpumask), timer_num, mode);
|
|
|
|
|
|
|
|
switch (mode) {
|
|
|
|
case CLOCK_EVT_MODE_PERIODIC:
|
|
|
|
delta = ((uint64_t)(NSEC_PER_SEC/HZ)) * apbt_clockevent.mult;
|
|
|
|
delta >>= apbt_clockevent.shift;
|
|
|
|
ctrl = apbt_readl(timer_num, APBTMR_N_CONTROL);
|
|
|
|
ctrl |= APBTMR_CONTROL_MODE_PERIODIC;
|
|
|
|
apbt_writel(timer_num, ctrl, APBTMR_N_CONTROL);
|
|
|
|
/*
|
|
|
|
* DW APB p. 46, have to disable timer before load counter,
|
|
|
|
* may cause sync problem.
|
|
|
|
*/
|
|
|
|
ctrl &= ~APBTMR_CONTROL_ENABLE;
|
|
|
|
apbt_writel(timer_num, ctrl, APBTMR_N_CONTROL);
|
|
|
|
udelay(1);
|
|
|
|
pr_debug("Setting clock period %d for HZ %d\n", (int)delta, HZ);
|
|
|
|
apbt_writel(timer_num, delta, APBTMR_N_LOAD_COUNT);
|
|
|
|
ctrl |= APBTMR_CONTROL_ENABLE;
|
|
|
|
apbt_writel(timer_num, ctrl, APBTMR_N_CONTROL);
|
|
|
|
break;
|
|
|
|
/* APB timer does not have one-shot mode, use free running mode */
|
|
|
|
case CLOCK_EVT_MODE_ONESHOT:
|
|
|
|
ctrl = apbt_readl(timer_num, APBTMR_N_CONTROL);
|
|
|
|
/*
|
|
|
|
* set free running mode, this mode will let timer reload max
|
|
|
|
* timeout which will give time (3min on 25MHz clock) to rearm
|
|
|
|
* the next event, therefore emulate the one-shot mode.
|
|
|
|
*/
|
|
|
|
ctrl &= ~APBTMR_CONTROL_ENABLE;
|
|
|
|
ctrl &= ~APBTMR_CONTROL_MODE_PERIODIC;
|
|
|
|
|
|
|
|
apbt_writel(timer_num, ctrl, APBTMR_N_CONTROL);
|
|
|
|
/* write again to set free running mode */
|
|
|
|
apbt_writel(timer_num, ctrl, APBTMR_N_CONTROL);
|
|
|
|
|
|
|
|
/*
|
|
|
|
* DW APB p. 46, load counter with all 1s before starting free
|
|
|
|
* running mode.
|
|
|
|
*/
|
|
|
|
apbt_writel(timer_num, ~0, APBTMR_N_LOAD_COUNT);
|
|
|
|
ctrl &= ~APBTMR_CONTROL_INT;
|
|
|
|
ctrl |= APBTMR_CONTROL_ENABLE;
|
|
|
|
apbt_writel(timer_num, ctrl, APBTMR_N_CONTROL);
|
|
|
|
break;
|
|
|
|
|
|
|
|
case CLOCK_EVT_MODE_UNUSED:
|
|
|
|
case CLOCK_EVT_MODE_SHUTDOWN:
|
|
|
|
apbt_disable_int(timer_num);
|
|
|
|
ctrl = apbt_readl(timer_num, APBTMR_N_CONTROL);
|
|
|
|
ctrl &= ~APBTMR_CONTROL_ENABLE;
|
|
|
|
apbt_writel(timer_num, ctrl, APBTMR_N_CONTROL);
|
|
|
|
break;
|
|
|
|
|
|
|
|
case CLOCK_EVT_MODE_RESUME:
|
|
|
|
apbt_enable_int(timer_num);
|
|
|
|
break;
|
|
|
|
}
|
2009-09-02 08:37:17 -06:00
|
|
|
}
|
|
|
|
|
|
|
|
static int apbt_next_event(unsigned long delta,
|
2010-03-03 14:38:48 -07:00
|
|
|
struct clock_event_device *evt)
|
2009-09-02 08:37:17 -06:00
|
|
|
{
|
2010-03-03 14:38:48 -07:00
|
|
|
unsigned long ctrl;
|
|
|
|
int timer_num;
|
|
|
|
|
|
|
|
struct apbt_dev *adev = EVT_TO_APBT_DEV(evt);
|
|
|
|
|
|
|
|
timer_num = adev->num;
|
|
|
|
/* Disable timer */
|
|
|
|
ctrl = apbt_readl(timer_num, APBTMR_N_CONTROL);
|
|
|
|
ctrl &= ~APBTMR_CONTROL_ENABLE;
|
|
|
|
apbt_writel(timer_num, ctrl, APBTMR_N_CONTROL);
|
|
|
|
/* write new count */
|
|
|
|
apbt_writel(timer_num, delta, APBTMR_N_LOAD_COUNT);
|
|
|
|
ctrl |= APBTMR_CONTROL_ENABLE;
|
|
|
|
apbt_writel(timer_num, ctrl, APBTMR_N_CONTROL);
|
|
|
|
return 0;
|
2009-09-02 08:37:17 -06:00
|
|
|
}
|
|
|
|
|
|
|
|
/*
|
|
|
|
* APB timer clock is not in sync with pclk on Langwell, which translates to
|
|
|
|
* unreliable read value caused by sampling error. the error does not add up
|
|
|
|
* overtime and only happens when sampling a 0 as a 1 by mistake. so the time
|
|
|
|
* would go backwards. the following code is trying to prevent time traveling
|
|
|
|
* backwards. little bit paranoid.
|
|
|
|
*/
|
|
|
|
static cycle_t apbt_read_clocksource(struct clocksource *cs)
|
|
|
|
{
|
2010-03-03 14:38:48 -07:00
|
|
|
unsigned long t0, t1, t2;
|
|
|
|
static unsigned long last_read;
|
2009-09-02 08:37:17 -06:00
|
|
|
|
|
|
|
bad_count:
|
2010-03-03 14:38:48 -07:00
|
|
|
t1 = apbt_readl(phy_cs_timer_id,
|
|
|
|
APBTMR_N_CURRENT_VALUE);
|
|
|
|
t2 = apbt_readl(phy_cs_timer_id,
|
|
|
|
APBTMR_N_CURRENT_VALUE);
|
|
|
|
if (unlikely(t1 < t2)) {
|
|
|
|
pr_debug("APBT: read current count error %lx:%lx:%lx\n",
|
|
|
|
t1, t2, t2 - t1);
|
|
|
|
goto bad_count;
|
|
|
|
}
|
|
|
|
/*
|
|
|
|
* check against cached last read, makes sure time does not go back.
|
|
|
|
* it could be a normal rollover but we will do tripple check anyway
|
|
|
|
*/
|
|
|
|
if (unlikely(t2 > last_read)) {
|
|
|
|
/* check if we have a normal rollover */
|
|
|
|
unsigned long raw_intr_status =
|
|
|
|
apbt_readl_reg(APBTMRS_RAW_INT_STATUS);
|
|
|
|
/*
|
|
|
|
* cs timer interrupt is masked but raw intr bit is set if
|
|
|
|
* rollover occurs. then we read EOI reg to clear it.
|
|
|
|
*/
|
|
|
|
if (raw_intr_status & (1 << phy_cs_timer_id)) {
|
|
|
|
apbt_readl(phy_cs_timer_id, APBTMR_N_EOI);
|
|
|
|
goto out;
|
|
|
|
}
|
|
|
|
pr_debug("APB CS going back %lx:%lx:%lx ",
|
|
|
|
t2, last_read, t2 - last_read);
|
2009-09-02 08:37:17 -06:00
|
|
|
bad_count_x3:
|
2010-03-03 14:38:48 -07:00
|
|
|
pr_debug(KERN_INFO "tripple check enforced\n");
|
|
|
|
t0 = apbt_readl(phy_cs_timer_id,
|
|
|
|
APBTMR_N_CURRENT_VALUE);
|
|
|
|
udelay(1);
|
|
|
|
t1 = apbt_readl(phy_cs_timer_id,
|
|
|
|
APBTMR_N_CURRENT_VALUE);
|
|
|
|
udelay(1);
|
|
|
|
t2 = apbt_readl(phy_cs_timer_id,
|
|
|
|
APBTMR_N_CURRENT_VALUE);
|
|
|
|
if ((t2 > t1) || (t1 > t0)) {
|
|
|
|
printk(KERN_ERR "Error: APB CS tripple check failed\n");
|
|
|
|
goto bad_count_x3;
|
|
|
|
}
|
|
|
|
}
|
2009-09-02 08:37:17 -06:00
|
|
|
out:
|
2010-03-03 14:38:48 -07:00
|
|
|
last_read = t2;
|
|
|
|
return (cycle_t)~t2;
|
2009-09-02 08:37:17 -06:00
|
|
|
}
|
|
|
|
|
|
|
|
static int apbt_clocksource_register(void)
|
|
|
|
{
|
2010-03-03 14:38:48 -07:00
|
|
|
u64 start, now;
|
|
|
|
cycle_t t1;
|
|
|
|
|
|
|
|
/* Start the counter, use timer 2 as source, timer 0/1 for event */
|
|
|
|
apbt_start_counter(phy_cs_timer_id);
|
|
|
|
|
|
|
|
/* Verify whether apbt counter works */
|
|
|
|
t1 = apbt_read_clocksource(&clocksource_apbt);
|
|
|
|
rdtscll(start);
|
|
|
|
|
|
|
|
/*
|
|
|
|
* We don't know the TSC frequency yet, but waiting for
|
|
|
|
* 200000 TSC cycles is safe:
|
|
|
|
* 4 GHz == 50us
|
|
|
|
* 1 GHz == 200us
|
|
|
|
*/
|
|
|
|
do {
|
|
|
|
rep_nop();
|
|
|
|
rdtscll(now);
|
|
|
|
} while ((now - start) < 200000UL);
|
|
|
|
|
|
|
|
/* APBT is the only always on clocksource, it has to work! */
|
|
|
|
if (t1 == apbt_read_clocksource(&clocksource_apbt))
|
|
|
|
panic("APBT counter not counting. APBT disabled\n");
|
|
|
|
|
|
|
|
/*
|
|
|
|
* initialize and register APBT clocksource
|
|
|
|
* convert that to ns/clock cycle
|
|
|
|
* mult = (ns/c) * 2^APBT_SHIFT
|
|
|
|
*/
|
|
|
|
clocksource_apbt.mult = div_sc(MSEC_PER_SEC,
|
|
|
|
(unsigned long) apbt_freq, APBT_SHIFT);
|
|
|
|
clocksource_register(&clocksource_apbt);
|
|
|
|
|
|
|
|
return 0;
|
2009-09-02 08:37:17 -06:00
|
|
|
}
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Early setup the APBT timer, only use timer 0 for booting then switch to
|
|
|
|
* per CPU timer if possible.
|
|
|
|
* returns 1 if per cpu apbt is setup
|
|
|
|
* returns 0 if no per cpu apbt is chosen
|
|
|
|
* panic if set up failed, this is the only platform timer on Moorestown.
|
|
|
|
*/
|
|
|
|
void __init apbt_time_init(void)
|
|
|
|
{
|
|
|
|
#ifdef CONFIG_SMP
|
2010-03-03 14:38:48 -07:00
|
|
|
int i;
|
|
|
|
struct sfi_timer_table_entry *p_mtmr;
|
|
|
|
unsigned int percpu_timer;
|
|
|
|
struct apbt_dev *adev;
|
2009-09-02 08:37:17 -06:00
|
|
|
#endif
|
|
|
|
|
2010-03-03 14:38:48 -07:00
|
|
|
if (apb_timer_block_enabled)
|
|
|
|
return;
|
|
|
|
apbt_set_mapping();
|
|
|
|
if (apbt_virt_address) {
|
|
|
|
pr_debug("Found APBT version 0x%lx\n",\
|
|
|
|
apbt_readl_reg(APBTMRS_COMP_VERSION));
|
|
|
|
} else
|
|
|
|
goto out_noapbt;
|
|
|
|
/*
|
|
|
|
* Read the frequency and check for a sane value, for ESL model
|
|
|
|
* we extend the possible clock range to allow time scaling.
|
|
|
|
*/
|
|
|
|
|
|
|
|
if (apbt_freq < APBT_MIN_FREQ || apbt_freq > APBT_MAX_FREQ) {
|
|
|
|
pr_debug("APBT has invalid freq 0x%llx\n", apbt_freq);
|
|
|
|
goto out_noapbt;
|
|
|
|
}
|
|
|
|
if (apbt_clocksource_register()) {
|
|
|
|
pr_debug("APBT has failed to register clocksource\n");
|
|
|
|
goto out_noapbt;
|
|
|
|
}
|
|
|
|
if (!apbt_clockevent_register())
|
|
|
|
apb_timer_block_enabled = 1;
|
|
|
|
else {
|
|
|
|
pr_debug("APBT has failed to register clockevent\n");
|
|
|
|
goto out_noapbt;
|
|
|
|
}
|
2009-09-02 08:37:17 -06:00
|
|
|
#ifdef CONFIG_SMP
|
2010-03-03 14:38:48 -07:00
|
|
|
/* kernel cmdline disable apb timer, so we will use lapic timers */
|
|
|
|
if (disable_apbt_percpu) {
|
|
|
|
printk(KERN_INFO "apbt: disabled per cpu timer\n");
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
pr_debug("%s: %d CPUs online\n", __func__, num_online_cpus());
|
|
|
|
if (num_possible_cpus() <= sfi_mtimer_num) {
|
|
|
|
percpu_timer = 1;
|
|
|
|
apbt_num_timers_used = num_possible_cpus();
|
|
|
|
} else {
|
|
|
|
percpu_timer = 0;
|
|
|
|
apbt_num_timers_used = 1;
|
|
|
|
adev = &per_cpu(cpu_apbt_dev, 0);
|
|
|
|
adev->flags &= ~APBT_DEV_USED;
|
|
|
|
}
|
|
|
|
pr_debug("%s: %d APB timers used\n", __func__, apbt_num_timers_used);
|
|
|
|
|
|
|
|
/* here we set up per CPU timer data structure */
|
|
|
|
apbt_devs = kzalloc(sizeof(struct apbt_dev) * apbt_num_timers_used,
|
|
|
|
GFP_KERNEL);
|
|
|
|
if (!apbt_devs) {
|
|
|
|
printk(KERN_ERR "Failed to allocate APB timer devices\n");
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
for (i = 0; i < apbt_num_timers_used; i++) {
|
|
|
|
adev = &per_cpu(cpu_apbt_dev, i);
|
|
|
|
adev->num = i;
|
|
|
|
adev->cpu = i;
|
|
|
|
p_mtmr = sfi_get_mtmr(i);
|
|
|
|
if (p_mtmr) {
|
|
|
|
adev->tick = p_mtmr->freq_hz;
|
|
|
|
adev->irq = p_mtmr->irq;
|
|
|
|
} else
|
|
|
|
printk(KERN_ERR "Failed to get timer for cpu %d\n", i);
|
|
|
|
adev->count = 0;
|
|
|
|
sprintf(adev->name, "apbt%d", i);
|
|
|
|
}
|
2009-09-02 08:37:17 -06:00
|
|
|
#endif
|
|
|
|
|
2010-03-03 14:38:48 -07:00
|
|
|
return;
|
2009-09-02 08:37:17 -06:00
|
|
|
|
|
|
|
out_noapbt:
|
2010-03-03 14:38:48 -07:00
|
|
|
apbt_clear_mapping();
|
|
|
|
apb_timer_block_enabled = 0;
|
|
|
|
panic("failed to enable APB timer\n");
|
2009-09-02 08:37:17 -06:00
|
|
|
}
|
|
|
|
|
|
|
|
static inline void apbt_disable(int n)
|
|
|
|
{
|
2010-03-03 14:38:48 -07:00
|
|
|
if (is_apbt_capable()) {
|
|
|
|
unsigned long ctrl = apbt_readl(n, APBTMR_N_CONTROL);
|
|
|
|
ctrl &= ~APBTMR_CONTROL_ENABLE;
|
|
|
|
apbt_writel(n, ctrl, APBTMR_N_CONTROL);
|
|
|
|
}
|
2009-09-02 08:37:17 -06:00
|
|
|
}
|
|
|
|
|
|
|
|
/* called before apb_timer_enable, use early map */
|
|
|
|
unsigned long apbt_quick_calibrate()
|
|
|
|
{
|
2010-03-03 14:38:48 -07:00
|
|
|
int i, scale;
|
|
|
|
u64 old, new;
|
|
|
|
cycle_t t1, t2;
|
|
|
|
unsigned long khz = 0;
|
|
|
|
u32 loop, shift;
|
|
|
|
|
|
|
|
apbt_set_mapping();
|
|
|
|
apbt_start_counter(phy_cs_timer_id);
|
|
|
|
|
|
|
|
/* check if the timer can count down, otherwise return */
|
|
|
|
old = apbt_read_clocksource(&clocksource_apbt);
|
|
|
|
i = 10000;
|
|
|
|
while (--i) {
|
|
|
|
if (old != apbt_read_clocksource(&clocksource_apbt))
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
if (!i)
|
|
|
|
goto failed;
|
|
|
|
|
|
|
|
/* count 16 ms */
|
|
|
|
loop = (apbt_freq * 1000) << 4;
|
|
|
|
|
|
|
|
/* restart the timer to ensure it won't get to 0 in the calibration */
|
|
|
|
apbt_start_counter(phy_cs_timer_id);
|
|
|
|
|
|
|
|
old = apbt_read_clocksource(&clocksource_apbt);
|
|
|
|
old += loop;
|
|
|
|
|
|
|
|
t1 = __native_read_tsc();
|
|
|
|
|
|
|
|
do {
|
|
|
|
new = apbt_read_clocksource(&clocksource_apbt);
|
|
|
|
} while (new < old);
|
|
|
|
|
|
|
|
t2 = __native_read_tsc();
|
|
|
|
|
|
|
|
shift = 5;
|
|
|
|
if (unlikely(loop >> shift == 0)) {
|
|
|
|
printk(KERN_INFO
|
|
|
|
"APBT TSC calibration failed, not enough resolution\n");
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
scale = (int)div_u64((t2 - t1), loop >> shift);
|
|
|
|
khz = (scale * apbt_freq * 1000) >> shift;
|
|
|
|
printk(KERN_INFO "TSC freq calculated by APB timer is %lu khz\n", khz);
|
|
|
|
return khz;
|
2009-09-02 08:37:17 -06:00
|
|
|
failed:
|
2010-03-03 14:38:48 -07:00
|
|
|
return 0;
|
2009-09-02 08:37:17 -06:00
|
|
|
}
|