314 lines
9.3 KiB
C
314 lines
9.3 KiB
C
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/* myri_sbus.h: Defines for MyriCOM MyriNET SBUS card driver.
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*
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* Copyright (C) 1996 David S. Miller (davem@caip.rutgers.edu)
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*/
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#ifndef _MYRI_SBUS_H
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#define _MYRI_SBUS_H
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/* LANAI Registers */
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#define LANAI_IPF0 0x00UL /* Context zero state registers.*/
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#define LANAI_CUR0 0x04UL
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#define LANAI_PREV0 0x08UL
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#define LANAI_DATA0 0x0cUL
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#define LANAI_DPF0 0x10UL
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#define LANAI_IPF1 0x14UL /* Context one state registers. */
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#define LANAI_CUR1 0x18UL
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#define LANAI_PREV1 0x1cUL
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#define LANAI_DATA1 0x20UL
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#define LANAI_DPF1 0x24UL
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#define LANAI_ISTAT 0x28UL /* Interrupt status. */
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#define LANAI_EIMASK 0x2cUL /* External IRQ mask. */
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#define LANAI_ITIMER 0x30UL /* IRQ timer. */
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#define LANAI_RTC 0x34UL /* Real Time Clock */
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#define LANAI_CSUM 0x38UL /* Checksum. */
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#define LANAI_DMAXADDR 0x3cUL /* SBUS DMA external address. */
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#define LANAI_DMALADDR 0x40UL /* SBUS DMA local address. */
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#define LANAI_DMACTR 0x44UL /* SBUS DMA counter. */
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#define LANAI_RXDMAPTR 0x48UL /* Receive DMA pointer. */
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#define LANAI_RXDMALIM 0x4cUL /* Receive DMA limit. */
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#define LANAI_TXDMAPTR 0x50UL /* Transmit DMA pointer. */
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#define LANAI_TXDMALIM 0x54UL /* Transmit DMA limit. */
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#define LANAI_TXDMALIMT 0x58UL /* Transmit DMA limit w/tail. */
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/* 0x5cUL, reserved */
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#define LANAI_RBYTE 0x60UL /* Receive byte. */
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/* 0x64-->0x6c, reserved */
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#define LANAI_RHALF 0x70UL /* Receive half-word. */
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/* 0x72UL, reserved */
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#define LANAI_RWORD 0x74UL /* Receive word. */
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#define LANAI_SALIGN 0x78UL /* Send align. */
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#define LANAI_SBYTE 0x7cUL /* SingleSend send-byte. */
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#define LANAI_SHALF 0x80UL /* SingleSend send-halfword. */
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#define LANAI_SWORD 0x84UL /* SingleSend send-word. */
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#define LANAI_SSENDT 0x88UL /* SingleSend special. */
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#define LANAI_DMADIR 0x8cUL /* DMA direction. */
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#define LANAI_DMASTAT 0x90UL /* DMA status. */
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#define LANAI_TIMEO 0x94UL /* Timeout register. */
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#define LANAI_MYRINET 0x98UL /* XXX MAGIC myricom thing */
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#define LANAI_HWDEBUG 0x9cUL /* Hardware debugging reg. */
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#define LANAI_LEDS 0xa0UL /* LED control. */
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#define LANAI_VERS 0xa4UL /* Version register. */
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#define LANAI_LINKON 0xa8UL /* Link activation reg. */
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/* 0xac-->0x104, reserved */
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#define LANAI_CVAL 0x108UL /* Clock value register. */
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#define LANAI_REG_SIZE 0x10cUL
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/* Interrupt status bits. */
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#define ISTAT_DEBUG 0x80000000
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#define ISTAT_HOST 0x40000000
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#define ISTAT_LAN7 0x00800000
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#define ISTAT_LAN6 0x00400000
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#define ISTAT_LAN5 0x00200000
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#define ISTAT_LAN4 0x00100000
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#define ISTAT_LAN3 0x00080000
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#define ISTAT_LAN2 0x00040000
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#define ISTAT_LAN1 0x00020000
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#define ISTAT_LAN0 0x00010000
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#define ISTAT_WRDY 0x00008000
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#define ISTAT_HRDY 0x00004000
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#define ISTAT_SRDY 0x00002000
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#define ISTAT_LINK 0x00001000
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#define ISTAT_FRES 0x00000800
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#define ISTAT_NRES 0x00000800
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#define ISTAT_WAKE 0x00000400
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#define ISTAT_OB2 0x00000200
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#define ISTAT_OB1 0x00000100
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#define ISTAT_TAIL 0x00000080
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#define ISTAT_WDOG 0x00000040
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#define ISTAT_TIME 0x00000020
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#define ISTAT_DMA 0x00000010
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#define ISTAT_SEND 0x00000008
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#define ISTAT_BUF 0x00000004
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#define ISTAT_RECV 0x00000002
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#define ISTAT_BRDY 0x00000001
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/* MYRI Registers */
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#define MYRI_RESETOFF 0x00UL
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#define MYRI_RESETON 0x04UL
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#define MYRI_IRQOFF 0x08UL
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#define MYRI_IRQON 0x0cUL
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#define MYRI_WAKEUPOFF 0x10UL
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#define MYRI_WAKEUPON 0x14UL
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#define MYRI_IRQREAD 0x18UL
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/* 0x1c-->0x3ffc, reserved */
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#define MYRI_LOCALMEM 0x4000UL
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#define MYRI_REG_SIZE 0x25000UL
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/* Shared memory interrupt mask. */
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#define SHMEM_IMASK_RX 0x00000002
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#define SHMEM_IMASK_TX 0x00000001
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/* Just to make things readable. */
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#define KERNEL_CHANNEL 0
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/* The size of this must be >= 129 bytes. */
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struct myri_eeprom {
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unsigned int cval;
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unsigned short cpuvers;
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unsigned char id[6];
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unsigned int ramsz;
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unsigned char fvers[32];
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unsigned char mvers[16];
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unsigned short dlval;
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unsigned short brd_type;
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unsigned short bus_type;
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unsigned short prod_code;
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unsigned int serial_num;
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unsigned short _reserved[24];
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unsigned int _unused[2];
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};
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/* EEPROM bus types, only SBUS is valid in this driver. */
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#define BUS_TYPE_SBUS 1
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/* EEPROM CPU revisions. */
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#define CPUVERS_2_3 0x0203
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#define CPUVERS_3_0 0x0300
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#define CPUVERS_3_1 0x0301
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#define CPUVERS_3_2 0x0302
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#define CPUVERS_4_0 0x0400
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#define CPUVERS_4_1 0x0401
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#define CPUVERS_4_2 0x0402
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#define CPUVERS_5_0 0x0500
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/* MYRI Control Registers */
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#define MYRICTRL_CTRL 0x00UL
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#define MYRICTRL_IRQLVL 0x02UL
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#define MYRICTRL_REG_SIZE 0x04UL
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/* Global control register defines. */
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#define CONTROL_ROFF 0x8000 /* Reset OFF. */
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#define CONTROL_RON 0x4000 /* Reset ON. */
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#define CONTROL_EIRQ 0x2000 /* Enable IRQ's. */
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#define CONTROL_DIRQ 0x1000 /* Disable IRQ's. */
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#define CONTROL_WON 0x0800 /* Wake-up ON. */
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#define MYRI_SCATTER_ENTRIES 8
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#define MYRI_GATHER_ENTRIES 16
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struct myri_sglist {
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u32 addr;
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u32 len;
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};
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struct myri_rxd {
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struct myri_sglist myri_scatters[MYRI_SCATTER_ENTRIES]; /* DMA scatter list.*/
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u32 csum; /* HW computed checksum. */
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u32 ctx;
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u32 num_sg; /* Total scatter entries. */
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};
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struct myri_txd {
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struct myri_sglist myri_gathers[MYRI_GATHER_ENTRIES]; /* DMA scatter list. */
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u32 num_sg; /* Total scatter entries. */
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u16 addr[4]; /* XXX address */
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u32 chan;
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u32 len; /* Total length of packet. */
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u32 csum_off; /* Where data to csum is. */
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u32 csum_field; /* Where csum goes in pkt. */
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};
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#define MYRINET_MTU 8432
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#define RX_ALLOC_SIZE 8448
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#define MYRI_PAD_LEN 2
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#define RX_COPY_THRESHOLD 256
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/* These numbers are cast in stone, new firmware is needed if
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* you want to change them.
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*/
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#define TX_RING_MAXSIZE 16
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#define RX_RING_MAXSIZE 16
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#define TX_RING_SIZE 16
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#define RX_RING_SIZE 16
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/* GRRR... */
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static __inline__ int NEXT_RX(int num)
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{
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/* XXX >=??? */
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if(++num > RX_RING_SIZE)
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num = 0;
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return num;
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}
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static __inline__ int PREV_RX(int num)
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{
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if(--num < 0)
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num = RX_RING_SIZE;
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return num;
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}
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#define NEXT_TX(num) (((num) + 1) & (TX_RING_SIZE - 1))
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#define PREV_TX(num) (((num) - 1) & (TX_RING_SIZE - 1))
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#define TX_BUFFS_AVAIL(head, tail) \
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((head) <= (tail) ? \
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(head) + (TX_RING_SIZE - 1) - (tail) : \
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(head) - (tail) - 1)
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struct sendq {
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u32 tail;
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u32 head;
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u32 hdebug;
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u32 mdebug;
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struct myri_txd myri_txd[TX_RING_MAXSIZE];
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};
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struct recvq {
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u32 head;
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u32 tail;
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u32 hdebug;
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u32 mdebug;
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struct myri_rxd myri_rxd[RX_RING_MAXSIZE + 1];
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};
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#define MYRI_MLIST_SIZE 8
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struct mclist {
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u32 maxlen;
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u32 len;
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u32 cache;
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struct pair {
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u8 addr[8];
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u32 val;
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} mc_pairs[MYRI_MLIST_SIZE];
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u8 bcast_addr[8];
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};
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struct myri_channel {
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u32 state; /* State of the channel. */
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u32 busy; /* Channel is busy. */
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struct sendq sendq; /* Device tx queue. */
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struct recvq recvq; /* Device rx queue. */
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struct recvq recvqa; /* Device rx queue acked. */
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u32 rbytes; /* Receive bytes. */
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u32 sbytes; /* Send bytes. */
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u32 rmsgs; /* Receive messages. */
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u32 smsgs; /* Send messages. */
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struct mclist mclist; /* Device multicast list. */
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};
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/* Values for per-channel state. */
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#define STATE_WFH 0 /* Waiting for HOST. */
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#define STATE_WFN 1 /* Waiting for NET. */
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#define STATE_READY 2 /* Ready. */
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struct myri_shmem {
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u8 addr[8]; /* Board's address. */
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u32 nchan; /* Number of channels. */
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u32 burst; /* SBUS dma burst enable. */
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u32 shakedown; /* DarkkkkStarrr Crashesss... */
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u32 send; /* Send wanted. */
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u32 imask; /* Interrupt enable mask. */
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u32 mlevel; /* Map level. */
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u32 debug[4]; /* Misc. debug areas. */
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struct myri_channel channel; /* Only one channel on a host. */
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};
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struct myri_eth {
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/* These are frequently accessed, keep together
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* to obtain good cache hit rates.
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*/
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spinlock_t irq_lock;
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struct myri_shmem __iomem *shmem; /* Shared data structures. */
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void __iomem *cregs; /* Control register space. */
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struct recvq __iomem *rqack; /* Where we ack rx's. */
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struct recvq __iomem *rq; /* Where we put buffers. */
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struct sendq __iomem *sq; /* Where we stuff tx's. */
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struct net_device *dev; /* Linux/NET dev struct. */
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int tx_old; /* To speed up tx cleaning. */
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void __iomem *lregs; /* Quick ptr to LANAI regs. */
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struct sk_buff *rx_skbs[RX_RING_SIZE+1];/* RX skb's */
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struct sk_buff *tx_skbs[TX_RING_SIZE]; /* TX skb's */
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struct net_device_stats enet_stats; /* Interface stats. */
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/* These are less frequently accessed. */
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void __iomem *regs; /* MyriCOM register space. */
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void __iomem *lanai; /* View 2 of register space. */
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unsigned int myri_bursts; /* SBUS bursts. */
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struct myri_eeprom eeprom; /* Local copy of EEPROM. */
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unsigned int reg_size; /* Size of register space. */
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unsigned int shmem_base; /* Offset to shared ram. */
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struct sbus_dev *myri_sdev; /* Our SBUS device struct. */
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struct myri_eth *next_module; /* Next in adapter chain. */
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};
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/* We use this to acquire receive skb's that we can DMA directly into. */
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#define ALIGNED_RX_SKB_ADDR(addr) \
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((((unsigned long)(addr) + (64 - 1)) & ~(64 - 1)) - (unsigned long)(addr))
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static inline struct sk_buff *myri_alloc_skb(unsigned int length, int gfp_flags)
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{
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struct sk_buff *skb;
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skb = alloc_skb(length + 64, gfp_flags);
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if(skb) {
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int offset = ALIGNED_RX_SKB_ADDR(skb->data);
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if(offset)
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skb_reserve(skb, offset);
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}
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return skb;
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}
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#endif /* !(_MYRI_SBUS_H) */
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