2005-04-16 16:20:36 -06:00
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/*
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* include/asm-ppc/mpc83xx.h
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*
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* MPC83xx definitions
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*
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* Maintainer: Kumar Gala <kumar.gala@freescale.com>
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*
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* Copyright 2005 Freescale Semiconductor, Inc
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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*/
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#ifdef __KERNEL__
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#ifndef __ASM_MPC83xx_H__
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#define __ASM_MPC83xx_H__
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#include <linux/config.h>
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#include <asm/mmu.h>
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#ifdef CONFIG_83xx
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#ifdef CONFIG_MPC834x_SYS
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#include <platforms/83xx/mpc834x_sys.h>
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#endif
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#define _IO_BASE isa_io_base
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#define _ISA_MEM_BASE isa_mem_base
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#ifdef CONFIG_PCI
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#define PCI_DRAM_OFFSET pci_dram_offset
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#else
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#define PCI_DRAM_OFFSET 0
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#endif
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/*
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* The "residual" board information structure the boot loader passes
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* into the kernel.
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*/
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extern unsigned char __res[];
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/* Internal IRQs on MPC83xx OpenPIC */
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/* Not all of these exist on all MPC83xx implementations */
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#ifndef MPC83xx_IPIC_IRQ_OFFSET
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#define MPC83xx_IPIC_IRQ_OFFSET 0
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#endif
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#define NR_IPIC_INTS 128
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#define MPC83xx_IRQ_UART1 ( 9 + MPC83xx_IPIC_IRQ_OFFSET)
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#define MPC83xx_IRQ_UART2 (10 + MPC83xx_IPIC_IRQ_OFFSET)
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#define MPC83xx_IRQ_SEC2 (11 + MPC83xx_IPIC_IRQ_OFFSET)
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#define MPC83xx_IRQ_IIC1 (14 + MPC83xx_IPIC_IRQ_OFFSET)
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#define MPC83xx_IRQ_IIC2 (15 + MPC83xx_IPIC_IRQ_OFFSET)
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#define MPC83xx_IRQ_SPI (16 + MPC83xx_IPIC_IRQ_OFFSET)
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#define MPC83xx_IRQ_EXT1 (17 + MPC83xx_IPIC_IRQ_OFFSET)
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#define MPC83xx_IRQ_EXT2 (18 + MPC83xx_IPIC_IRQ_OFFSET)
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#define MPC83xx_IRQ_EXT3 (19 + MPC83xx_IPIC_IRQ_OFFSET)
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#define MPC83xx_IRQ_EXT4 (20 + MPC83xx_IPIC_IRQ_OFFSET)
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#define MPC83xx_IRQ_EXT5 (21 + MPC83xx_IPIC_IRQ_OFFSET)
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#define MPC83xx_IRQ_EXT6 (22 + MPC83xx_IPIC_IRQ_OFFSET)
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#define MPC83xx_IRQ_EXT7 (23 + MPC83xx_IPIC_IRQ_OFFSET)
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#define MPC83xx_IRQ_TSEC1_TX (32 + MPC83xx_IPIC_IRQ_OFFSET)
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#define MPC83xx_IRQ_TSEC1_RX (33 + MPC83xx_IPIC_IRQ_OFFSET)
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#define MPC83xx_IRQ_TSEC1_ERROR (34 + MPC83xx_IPIC_IRQ_OFFSET)
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#define MPC83xx_IRQ_TSEC2_TX (35 + MPC83xx_IPIC_IRQ_OFFSET)
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#define MPC83xx_IRQ_TSEC2_RX (36 + MPC83xx_IPIC_IRQ_OFFSET)
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#define MPC83xx_IRQ_TSEC2_ERROR (37 + MPC83xx_IPIC_IRQ_OFFSET)
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#define MPC83xx_IRQ_USB2_DR (38 + MPC83xx_IPIC_IRQ_OFFSET)
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#define MPC83xx_IRQ_USB2_MPH (39 + MPC83xx_IPIC_IRQ_OFFSET)
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#define MPC83xx_IRQ_EXT0 (48 + MPC83xx_IPIC_IRQ_OFFSET)
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#define MPC83xx_IRQ_RTC_SEC (64 + MPC83xx_IPIC_IRQ_OFFSET)
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#define MPC83xx_IRQ_PIT (65 + MPC83xx_IPIC_IRQ_OFFSET)
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#define MPC83xx_IRQ_PCI1 (66 + MPC83xx_IPIC_IRQ_OFFSET)
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#define MPC83xx_IRQ_PCI2 (67 + MPC83xx_IPIC_IRQ_OFFSET)
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#define MPC83xx_IRQ_RTC_ALR (68 + MPC83xx_IPIC_IRQ_OFFSET)
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#define MPC83xx_IRQ_MU (69 + MPC83xx_IPIC_IRQ_OFFSET)
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#define MPC83xx_IRQ_SBA (70 + MPC83xx_IPIC_IRQ_OFFSET)
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#define MPC83xx_IRQ_DMA (71 + MPC83xx_IPIC_IRQ_OFFSET)
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#define MPC83xx_IRQ_GTM4 (72 + MPC83xx_IPIC_IRQ_OFFSET)
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#define MPC83xx_IRQ_GTM8 (73 + MPC83xx_IPIC_IRQ_OFFSET)
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#define MPC83xx_IRQ_GPIO1 (74 + MPC83xx_IPIC_IRQ_OFFSET)
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#define MPC83xx_IRQ_GPIO2 (75 + MPC83xx_IPIC_IRQ_OFFSET)
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#define MPC83xx_IRQ_DDR (76 + MPC83xx_IPIC_IRQ_OFFSET)
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#define MPC83xx_IRQ_LBC (77 + MPC83xx_IPIC_IRQ_OFFSET)
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#define MPC83xx_IRQ_GTM2 (78 + MPC83xx_IPIC_IRQ_OFFSET)
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#define MPC83xx_IRQ_GTM6 (79 + MPC83xx_IPIC_IRQ_OFFSET)
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#define MPC83xx_IRQ_PMC (80 + MPC83xx_IPIC_IRQ_OFFSET)
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#define MPC83xx_IRQ_GTM3 (84 + MPC83xx_IPIC_IRQ_OFFSET)
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#define MPC83xx_IRQ_GTM7 (85 + MPC83xx_IPIC_IRQ_OFFSET)
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#define MPC83xx_IRQ_GTM1 (90 + MPC83xx_IPIC_IRQ_OFFSET)
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#define MPC83xx_IRQ_GTM5 (91 + MPC83xx_IPIC_IRQ_OFFSET)
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#define MPC83xx_CCSRBAR_SIZE (1024*1024)
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/* Let modules/drivers get at immrbar (physical) */
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extern phys_addr_t immrbar;
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enum ppc_sys_devices {
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MPC83xx_TSEC1,
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MPC83xx_TSEC2,
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MPC83xx_IIC1,
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MPC83xx_IIC2,
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MPC83xx_DUART,
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MPC83xx_SEC2,
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MPC83xx_USB2_DR,
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MPC83xx_USB2_MPH,
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2005-11-08 22:34:37 -07:00
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MPC83xx_MDIO,
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2005-04-16 16:20:36 -06:00
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};
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#endif /* CONFIG_83xx */
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#endif /* __ASM_MPC83xx_H__ */
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#endif /* __KERNEL__ */
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