2008-08-05 09:14:15 -06:00
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/* arch/arm/mach-s3c2410/include/mach/irqs.h
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2005-04-16 16:20:36 -06:00
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*
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* Copyright (c) 2003-2005 Simtec Electronics
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* Ben Dooks <ben@simtec.co.uk>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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2006-09-09 12:44:52 -06:00
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*/
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2005-04-16 16:20:36 -06:00
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#ifndef __ASM_ARCH_IRQS_H
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#define __ASM_ARCH_IRQS_H __FILE__
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/* we keep the first set of CPU IRQs out of the range of
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* the ISA space, so that the PC104 has them to itself
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* and we don't end up having to do horrible things to the
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* standard ISA drivers....
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*/
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#define S3C2410_CPUIRQ_OFFSET (16)
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#define S3C2410_IRQ(x) ((x) + S3C2410_CPUIRQ_OFFSET)
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/* main cpu interrupts */
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#define IRQ_EINT0 S3C2410_IRQ(0) /* 16 */
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#define IRQ_EINT1 S3C2410_IRQ(1)
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#define IRQ_EINT2 S3C2410_IRQ(2)
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#define IRQ_EINT3 S3C2410_IRQ(3)
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#define IRQ_EINT4t7 S3C2410_IRQ(4) /* 20 */
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#define IRQ_EINT8t23 S3C2410_IRQ(5)
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#define IRQ_RESERVED6 S3C2410_IRQ(6) /* for s3c2410 */
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2007-02-15 08:35:51 -07:00
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#define IRQ_CAM S3C2410_IRQ(6) /* for s3c2440,s3c2443 */
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#define IRQ_BATT_FLT S3C2410_IRQ(7)
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#define IRQ_TICK S3C2410_IRQ(8) /* 24 */
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#define IRQ_WDT S3C2410_IRQ(9) /* WDT/AC97 for s3c2443 */
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#define IRQ_TIMER0 S3C2410_IRQ(10)
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#define IRQ_TIMER1 S3C2410_IRQ(11)
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#define IRQ_TIMER2 S3C2410_IRQ(12)
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#define IRQ_TIMER3 S3C2410_IRQ(13)
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#define IRQ_TIMER4 S3C2410_IRQ(14)
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#define IRQ_UART2 S3C2410_IRQ(15)
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#define IRQ_LCD S3C2410_IRQ(16) /* 32 */
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#define IRQ_DMA0 S3C2410_IRQ(17) /* IRQ_DMA for s3c2443 */
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#define IRQ_DMA1 S3C2410_IRQ(18)
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#define IRQ_DMA2 S3C2410_IRQ(19)
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#define IRQ_DMA3 S3C2410_IRQ(20)
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#define IRQ_SDI S3C2410_IRQ(21)
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#define IRQ_SPI0 S3C2410_IRQ(22)
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#define IRQ_UART1 S3C2410_IRQ(23)
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#define IRQ_RESERVED24 S3C2410_IRQ(24) /* 40 */
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#define IRQ_NFCON S3C2410_IRQ(24) /* for s3c2440 */
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#define IRQ_USBD S3C2410_IRQ(25)
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#define IRQ_USBH S3C2410_IRQ(26)
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#define IRQ_IIC S3C2410_IRQ(27)
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#define IRQ_UART0 S3C2410_IRQ(28) /* 44 */
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#define IRQ_SPI1 S3C2410_IRQ(29)
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#define IRQ_RTC S3C2410_IRQ(30)
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#define IRQ_ADCPARENT S3C2410_IRQ(31)
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/* interrupts generated from the external interrupts sources */
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#define IRQ_EINT4 S3C2410_IRQ(32) /* 48 */
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#define IRQ_EINT5 S3C2410_IRQ(33)
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#define IRQ_EINT6 S3C2410_IRQ(34)
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#define IRQ_EINT7 S3C2410_IRQ(35)
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#define IRQ_EINT8 S3C2410_IRQ(36)
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#define IRQ_EINT9 S3C2410_IRQ(37)
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#define IRQ_EINT10 S3C2410_IRQ(38)
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#define IRQ_EINT11 S3C2410_IRQ(39)
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#define IRQ_EINT12 S3C2410_IRQ(40)
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#define IRQ_EINT13 S3C2410_IRQ(41)
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#define IRQ_EINT14 S3C2410_IRQ(42)
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#define IRQ_EINT15 S3C2410_IRQ(43)
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#define IRQ_EINT16 S3C2410_IRQ(44)
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#define IRQ_EINT17 S3C2410_IRQ(45)
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#define IRQ_EINT18 S3C2410_IRQ(46)
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#define IRQ_EINT19 S3C2410_IRQ(47)
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#define IRQ_EINT20 S3C2410_IRQ(48) /* 64 */
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#define IRQ_EINT21 S3C2410_IRQ(49)
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#define IRQ_EINT22 S3C2410_IRQ(50)
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#define IRQ_EINT23 S3C2410_IRQ(51)
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2008-12-11 17:24:13 -07:00
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#define IRQ_EINT_BIT(x) ((x) - IRQ_EINT4 + 4)
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#define IRQ_EINT(x) (((x) >= 4) ? (IRQ_EINT4 + (x) - 4) : (IRQ_EINT0 + (x)))
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#define IRQ_LCD_FIFO S3C2410_IRQ(52)
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#define IRQ_LCD_FRAME S3C2410_IRQ(53)
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/* IRQs for the interal UARTs, and ADC
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* these need to be ordered in number of appearance in the
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* SUBSRC mask register
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*/
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2007-02-15 08:28:11 -07:00
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#define S3C2410_IRQSUB(x) S3C2410_IRQ((x)+54)
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2007-02-15 08:28:11 -07:00
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#define IRQ_S3CUART_RX0 S3C2410_IRQSUB(0) /* 70 */
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#define IRQ_S3CUART_TX0 S3C2410_IRQSUB(1)
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#define IRQ_S3CUART_ERR0 S3C2410_IRQSUB(2)
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2007-02-15 08:28:11 -07:00
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#define IRQ_S3CUART_RX1 S3C2410_IRQSUB(3) /* 73 */
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#define IRQ_S3CUART_TX1 S3C2410_IRQSUB(4)
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#define IRQ_S3CUART_ERR1 S3C2410_IRQSUB(5)
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#define IRQ_S3CUART_RX2 S3C2410_IRQSUB(6) /* 76 */
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#define IRQ_S3CUART_TX2 S3C2410_IRQSUB(7)
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#define IRQ_S3CUART_ERR2 S3C2410_IRQSUB(8)
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#define IRQ_TC S3C2410_IRQSUB(9)
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#define IRQ_ADC S3C2410_IRQSUB(10)
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2007-10-04 14:41:20 -06:00
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/* extra irqs for s3c2412 */
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#define IRQ_S3C2412_CFSDI S3C2410_IRQ(21)
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#define IRQ_S3C2412_SDI S3C2410_IRQSUB(13)
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#define IRQ_S3C2412_CF S3C2410_IRQSUB(14)
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2009-08-19 07:31:03 -06:00
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#define IRQ_S3C2416_EINT8t15 S3C2410_IRQ(5)
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#define IRQ_S3C2416_DMA S3C2410_IRQ(17)
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#define IRQ_S3C2416_UART3 S3C2410_IRQ(18)
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#define IRQ_S3C2416_SDI1 S3C2410_IRQ(20)
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#define IRQ_S3C2416_SDI0 S3C2410_IRQ(21)
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#define IRQ_S3C2416_LCD2 S3C2410_IRQSUB(15)
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#define IRQ_S3C2416_LCD3 S3C2410_IRQSUB(16)
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#define IRQ_S3C2416_LCD4 S3C2410_IRQSUB(17)
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#define IRQ_S3C2416_DMA0 S3C2410_IRQSUB(18)
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#define IRQ_S3C2416_DMA1 S3C2410_IRQSUB(19)
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#define IRQ_S3C2416_DMA2 S3C2410_IRQSUB(20)
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#define IRQ_S3C2416_DMA3 S3C2410_IRQSUB(21)
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#define IRQ_S3C2416_DMA4 S3C2410_IRQSUB(22)
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#define IRQ_S3C2416_DMA5 S3C2410_IRQSUB(23)
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#define IRQ_S32416_WDT S3C2410_IRQSUB(27)
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#define IRQ_S32416_AC97 S3C2410_IRQSUB(28)
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2012-05-19 10:01:35 -06:00
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/* second interrupt-register of s3c2416/s3c2450 */
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#define S3C2416_IRQ(x) S3C2410_IRQ((x) + 54 + 29)
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#define IRQ_S3C2416_2D S3C2416_IRQ(0)
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#define IRQ_S3C2416_IIC1 S3C2416_IRQ(1)
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#define IRQ_S3C2416_RESERVED2 S3C2416_IRQ(2)
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#define IRQ_S3C2416_RESERVED3 S3C2416_IRQ(3)
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#define IRQ_S3C2416_PCM0 S3C2416_IRQ(4)
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#define IRQ_S3C2416_PCM1 S3C2416_IRQ(5)
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#define IRQ_S3C2416_I2S0 S3C2416_IRQ(6)
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#define IRQ_S3C2416_I2S1 S3C2416_IRQ(7)
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2009-08-19 07:31:03 -06:00
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2005-04-16 16:20:36 -06:00
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/* extra irqs for s3c2440 */
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2007-02-15 08:35:51 -07:00
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#define IRQ_S3C2440_CAM_C S3C2410_IRQSUB(11) /* S3C2443 too */
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#define IRQ_S3C2440_CAM_P S3C2410_IRQSUB(12) /* S3C2443 too */
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#define IRQ_S3C2440_WDT S3C2410_IRQSUB(13)
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#define IRQ_S3C2440_AC97 S3C2410_IRQSUB(14)
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2007-02-15 08:35:51 -07:00
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/* irqs for s3c2443 */
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#define IRQ_S3C2443_DMA S3C2410_IRQ(17) /* IRQ_DMA1 */
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#define IRQ_S3C2443_UART3 S3C2410_IRQ(18) /* IRQ_DMA2 */
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#define IRQ_S3C2443_CFCON S3C2410_IRQ(19) /* IRQ_DMA3 */
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2007-05-20 10:32:39 -06:00
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#define IRQ_S3C2443_HSMMC S3C2410_IRQ(20) /* IRQ_SDI */
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2007-02-15 08:35:51 -07:00
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#define IRQ_S3C2443_NAND S3C2410_IRQ(24) /* reserved */
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2010-04-29 03:59:43 -06:00
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#define IRQ_S3C2416_HSMMC0 S3C2410_IRQ(21) /* S3C2416/S3C2450 */
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2011-01-05 21:04:33 -07:00
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#define IRQ_HSMMC0 IRQ_S3C2416_HSMMC0
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#define IRQ_HSMMC1 IRQ_S3C2443_HSMMC
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2008-10-31 10:14:28 -06:00
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2007-02-15 08:35:51 -07:00
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#define IRQ_S3C2443_LCD1 S3C2410_IRQSUB(14)
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#define IRQ_S3C2443_LCD2 S3C2410_IRQSUB(15)
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#define IRQ_S3C2443_LCD3 S3C2410_IRQSUB(16)
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#define IRQ_S3C2443_LCD4 S3C2410_IRQSUB(17)
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#define IRQ_S3C2443_DMA0 S3C2410_IRQSUB(18)
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#define IRQ_S3C2443_DMA1 S3C2410_IRQSUB(19)
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#define IRQ_S3C2443_DMA2 S3C2410_IRQSUB(20)
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#define IRQ_S3C2443_DMA3 S3C2410_IRQSUB(21)
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#define IRQ_S3C2443_DMA4 S3C2410_IRQSUB(22)
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#define IRQ_S3C2443_DMA5 S3C2410_IRQSUB(23)
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/* UART3 */
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#define IRQ_S3C2443_RX3 S3C2410_IRQSUB(24)
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#define IRQ_S3C2443_TX3 S3C2410_IRQSUB(25)
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#define IRQ_S3C2443_ERR3 S3C2410_IRQSUB(26)
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#define IRQ_S3C2443_WDT S3C2410_IRQSUB(27)
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#define IRQ_S3C2443_AC97 S3C2410_IRQSUB(28)
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2012-05-19 10:01:35 -06:00
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#if defined(CONFIG_CPU_S3C2416)
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#define NR_IRQS (IRQ_S3C2416_I2S1 + 1)
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#elif defined(CONFIG_CPU_S3C2443)
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2007-02-15 08:35:51 -07:00
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#define NR_IRQS (IRQ_S3C2443_AC97+1)
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#else
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2005-04-16 16:20:36 -06:00
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#define NR_IRQS (IRQ_S3C2440_AC97+1)
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2007-02-15 08:35:51 -07:00
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#endif
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2005-04-16 16:20:36 -06:00
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2008-11-04 08:29:09 -07:00
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/* compatibility define. */
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#define IRQ_UART3 IRQ_S3C2443_UART3
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#define IRQ_S3CUART_RX3 IRQ_S3C2443_RX3
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#define IRQ_S3CUART_TX3 IRQ_S3C2443_TX3
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#define IRQ_S3CUART_ERR3 IRQ_S3C2443_ERR3
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2010-04-30 04:08:38 -06:00
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#define IRQ_LCD_VSYNC IRQ_S3C2443_LCD3
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#define IRQ_LCD_SYSTEM IRQ_S3C2443_LCD2
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2009-08-05 11:29:57 -06:00
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#ifdef CONFIG_CPU_S3C2440
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2011-10-02 20:34:26 -06:00
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#define IRQ_S3C244X_AC97 IRQ_S3C2440_AC97
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2009-08-05 11:29:57 -06:00
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#else
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2011-10-02 20:34:26 -06:00
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#define IRQ_S3C244X_AC97 IRQ_S3C2443_AC97
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2009-08-05 11:29:57 -06:00
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#endif
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2008-01-28 05:01:22 -07:00
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/* Our FIQs are routable from IRQ_EINT0 to IRQ_ADCPARENT */
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#define FIQ_START IRQ_EINT0
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2005-04-16 16:20:36 -06:00
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#endif /* __ASM_ARCH_IRQ_H */
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