48 lines
1.3 KiB
C
48 lines
1.3 KiB
C
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#ifndef _SERIAL_MFD_H_
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#define _SERIAL_MFD_H_
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/* HW register offset definition */
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#define UART_FOR 0x08
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#define UART_PS 0x0C
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#define UART_MUL 0x0D
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#define UART_DIV 0x0E
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#define HSU_GBL_IEN 0x0
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#define HSU_GBL_IST 0x4
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#define HSU_GBL_INT_BIT_PORT0 0x0
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#define HSU_GBL_INT_BIT_PORT1 0x1
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#define HSU_GBL_INT_BIT_PORT2 0x2
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#define HSU_GBL_INT_BIT_IRI 0x3
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#define HSU_GBL_INT_BIT_HDLC 0x4
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#define HSU_GBL_INT_BIT_DMA 0x5
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#define HSU_GBL_ISR 0x8
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#define HSU_GBL_DMASR 0x400
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#define HSU_GBL_DMAISR 0x404
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#define HSU_PORT_REG_OFFSET 0x80
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#define HSU_PORT0_REG_OFFSET 0x80
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#define HSU_PORT1_REG_OFFSET 0x100
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#define HSU_PORT2_REG_OFFSET 0x180
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#define HSU_PORT_REG_LENGTH 0x80
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#define HSU_DMA_CHANS_REG_OFFSET 0x500
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#define HSU_DMA_CHANS_REG_LENGTH 0x40
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#define HSU_CH_SR 0x0 /* channel status reg */
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#define HSU_CH_CR 0x4 /* control reg */
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#define HSU_CH_DCR 0x8 /* descriptor control reg */
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#define HSU_CH_BSR 0x10 /* max fifo buffer size reg */
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#define HSU_CH_MOTSR 0x14 /* minimum ocp transfer size */
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#define HSU_CH_D0SAR 0x20 /* desc 0 start addr */
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#define HSU_CH_D0TSR 0x24 /* desc 0 transfer size */
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#define HSU_CH_D1SAR 0x28
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#define HSU_CH_D1TSR 0x2C
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#define HSU_CH_D2SAR 0x30
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#define HSU_CH_D2TSR 0x34
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#define HSU_CH_D3SAR 0x38
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#define HSU_CH_D3TSR 0x3C
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#endif
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