2005-04-16 16:20:36 -06:00
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/*
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* Copyright (C) 2004 Matthew Wilcox <matthew@wil.cx>
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* Copyright (C) 2004 Intel Corp.
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*
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* This code is released under the GNU General Public License version 2.
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*/
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/*
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* mmconfig.c - Low-level direct PCI config space access via MMCONFIG
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*/
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#include <linux/pci.h>
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#include <linux/init.h>
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2005-06-23 18:35:56 -06:00
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#include <linux/acpi.h>
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2006-04-07 11:49:30 -06:00
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#include <asm/e820.h>
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2005-04-16 16:20:36 -06:00
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#include "pci.h"
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2006-04-07 11:49:30 -06:00
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#define MMCONFIG_APER_SIZE (256*1024*1024)
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2006-04-07 11:50:12 -06:00
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/* Assume systems with more busses have correct MCFG */
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#define MAX_CHECK_BUS 16
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2005-04-16 16:20:36 -06:00
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#define mmcfg_virt_addr ((void __iomem *) fix_to_virt(FIX_PCIE_MCFG))
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/* The base address of the last MMCONFIG device accessed */
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static u32 mmcfg_last_accessed_device;
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2006-04-07 11:50:12 -06:00
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static DECLARE_BITMAP(fallback_slots, MAX_CHECK_BUS*32);
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2005-12-12 23:17:11 -07:00
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2005-04-16 16:20:36 -06:00
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/*
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* Functions for accessing PCI configuration space with MMCONFIG accesses
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*/
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2005-12-12 23:17:11 -07:00
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static u32 get_base_addr(unsigned int seg, int bus, unsigned devfn)
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2005-06-23 18:35:56 -06:00
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{
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int cfg_num = -1;
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struct acpi_table_mcfg_config *cfg;
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2006-04-07 11:50:12 -06:00
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if (seg == 0 && bus < MAX_CHECK_BUS &&
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test_bit(PCI_SLOT(devfn) + 32*bus, fallback_slots))
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2005-12-12 23:17:11 -07:00
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return 0;
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2005-06-23 18:35:56 -06:00
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while (1) {
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++cfg_num;
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if (cfg_num >= pci_mmcfg_config_num) {
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2006-01-26 18:03:50 -07:00
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break;
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2005-06-23 18:35:56 -06:00
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}
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cfg = &pci_mmcfg_config[cfg_num];
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if (cfg->pci_segment_group_number != seg)
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continue;
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if ((cfg->start_bus_number <= bus) &&
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(cfg->end_bus_number >= bus))
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return cfg->base_address;
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}
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2006-01-26 18:03:50 -07:00
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/* Handle more broken MCFG tables on Asus etc.
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They only contain a single entry for bus 0-0. Assume
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this applies to all busses. */
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cfg = &pci_mmcfg_config[0];
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if (pci_mmcfg_config_num == 1 &&
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cfg->pci_segment_group_number == 0 &&
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(cfg->start_bus_number | cfg->end_bus_number) == 0)
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return cfg->base_address;
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/* Fall back to type 0 */
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return 0;
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2005-06-23 18:35:56 -06:00
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}
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2005-04-16 16:20:36 -06:00
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2005-12-12 23:17:10 -07:00
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static inline void pci_exp_set_dev_base(unsigned int base, int bus, int devfn)
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2005-04-16 16:20:36 -06:00
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{
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2005-12-12 23:17:10 -07:00
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u32 dev_base = base | (bus << 20) | (devfn << 12);
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2005-04-16 16:20:36 -06:00
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if (dev_base != mmcfg_last_accessed_device) {
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mmcfg_last_accessed_device = dev_base;
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set_fixmap_nocache(FIX_PCIE_MCFG, dev_base);
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}
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}
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static int pci_mmcfg_read(unsigned int seg, unsigned int bus,
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unsigned int devfn, int reg, int len, u32 *value)
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{
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unsigned long flags;
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2005-12-12 23:17:10 -07:00
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u32 base;
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2005-04-16 16:20:36 -06:00
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2006-04-11 04:54:48 -06:00
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if ((bus > 255) || (devfn > 255) || (reg > 4095)) {
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2006-04-07 11:50:15 -06:00
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*value = -1;
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2005-04-16 16:20:36 -06:00
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return -EINVAL;
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2006-04-07 11:50:15 -06:00
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}
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2005-04-16 16:20:36 -06:00
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2005-12-12 23:17:11 -07:00
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base = get_base_addr(seg, bus, devfn);
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2005-12-12 23:17:10 -07:00
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if (!base)
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return pci_conf1_read(seg,bus,devfn,reg,len,value);
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2005-04-16 16:20:36 -06:00
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spin_lock_irqsave(&pci_config_lock, flags);
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2005-12-12 23:17:10 -07:00
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pci_exp_set_dev_base(base, bus, devfn);
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2005-04-16 16:20:36 -06:00
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switch (len) {
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case 1:
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*value = readb(mmcfg_virt_addr + reg);
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break;
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case 2:
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*value = readw(mmcfg_virt_addr + reg);
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break;
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case 4:
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*value = readl(mmcfg_virt_addr + reg);
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break;
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}
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spin_unlock_irqrestore(&pci_config_lock, flags);
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return 0;
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}
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static int pci_mmcfg_write(unsigned int seg, unsigned int bus,
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unsigned int devfn, int reg, int len, u32 value)
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{
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unsigned long flags;
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2005-12-12 23:17:10 -07:00
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u32 base;
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2005-04-16 16:20:36 -06:00
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if ((bus > 255) || (devfn > 255) || (reg > 4095))
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return -EINVAL;
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2005-12-12 23:17:11 -07:00
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base = get_base_addr(seg, bus, devfn);
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2005-12-12 23:17:10 -07:00
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if (!base)
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return pci_conf1_write(seg,bus,devfn,reg,len,value);
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2005-04-16 16:20:36 -06:00
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spin_lock_irqsave(&pci_config_lock, flags);
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2005-12-12 23:17:10 -07:00
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pci_exp_set_dev_base(base, bus, devfn);
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2005-04-16 16:20:36 -06:00
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switch (len) {
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case 1:
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writeb(value, mmcfg_virt_addr + reg);
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break;
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case 2:
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writew(value, mmcfg_virt_addr + reg);
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break;
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case 4:
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writel(value, mmcfg_virt_addr + reg);
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break;
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}
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spin_unlock_irqrestore(&pci_config_lock, flags);
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return 0;
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}
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static struct pci_raw_ops pci_mmcfg = {
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.read = pci_mmcfg_read,
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.write = pci_mmcfg_write,
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};
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2005-12-12 23:17:11 -07:00
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/* K8 systems have some devices (typically in the builtin northbridge)
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that are only accessible using type1
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Normally this can be expressed in the MCFG by not listing them
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and assigning suitable _SEGs, but this isn't implemented in some BIOS.
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Instead try to discover all devices on bus 0 that are unreachable using MM
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2006-04-07 11:50:12 -06:00
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and fallback for them. */
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2005-12-12 23:17:11 -07:00
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static __init void unreachable_devices(void)
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{
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2006-04-07 11:50:12 -06:00
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int i, k;
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2005-12-12 23:17:11 -07:00
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unsigned long flags;
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2006-04-07 11:50:12 -06:00
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for (k = 0; k < MAX_CHECK_BUS; k++) {
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for (i = 0; i < 32; i++) {
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u32 val1;
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u32 addr;
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pci_conf1_read(0, k, PCI_DEVFN(i, 0), 0, 4, &val1);
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if (val1 == 0xffffffff)
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continue;
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/* Locking probably not needed, but safer */
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spin_lock_irqsave(&pci_config_lock, flags);
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addr = get_base_addr(0, k, PCI_DEVFN(i, 0));
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if (addr != 0)
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pci_exp_set_dev_base(addr, k, PCI_DEVFN(i, 0));
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if (addr == 0 ||
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readl((u32 __iomem *)mmcfg_virt_addr) != val1) {
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set_bit(i, fallback_slots);
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printk(KERN_NOTICE
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"PCI: No mmconfig possible on %x:%x\n", k, i);
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}
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spin_unlock_irqrestore(&pci_config_lock, flags);
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}
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2005-12-12 23:17:11 -07:00
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}
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}
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2006-03-23 15:35:12 -07:00
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void __init pci_mmcfg_init(void)
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2005-04-16 16:20:36 -06:00
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{
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if ((pci_probe & PCI_PROBE_MMCONF) == 0)
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2006-03-23 15:35:12 -07:00
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return;
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2005-06-23 18:35:56 -06:00
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acpi_table_parse(ACPI_MCFG, acpi_parse_mcfg);
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if ((pci_mmcfg_config_num == 0) ||
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(pci_mmcfg_config == NULL) ||
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(pci_mmcfg_config[0].base_address == 0))
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2006-03-23 15:35:12 -07:00
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return;
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2005-04-16 16:20:36 -06:00
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2006-04-07 11:49:30 -06:00
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if (!e820_all_mapped(pci_mmcfg_config[0].base_address,
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pci_mmcfg_config[0].base_address + MMCONFIG_APER_SIZE,
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E820_RESERVED)) {
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printk(KERN_ERR "PCI: BIOS Bug: MCFG area is not E820-reserved\n");
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printk(KERN_ERR "PCI: Not using MMCONFIG.\n");
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return;
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}
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2005-04-16 16:20:36 -06:00
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printk(KERN_INFO "PCI: Using MMCONFIG\n");
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raw_pci_ops = &pci_mmcfg;
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pci_probe = (pci_probe & ~PCI_PROBE_MASK) | PCI_PROBE_MMCONF;
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2005-12-12 23:17:11 -07:00
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unreachable_devices();
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2005-04-16 16:20:36 -06:00
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}
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