431 lines
14 KiB
C
431 lines
14 KiB
C
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/*
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* NCR 5380 defines
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*
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* Copyright 1993, Drew Eckhardt
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* Visionary Computing
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* (Unix consulting and custom programming)
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* drew@colorado.edu
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* +1 (303) 666-5836
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*
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* DISTRIBUTION RELEASE 7
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*
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* For more information, please consult
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*
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* NCR 5380 Family
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* SCSI Protocol Controller
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* Databook
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* NCR Microelectronics
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* 1635 Aeroplaza Drive
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* Colorado Springs, CO 80916
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* 1+ (719) 578-3400
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* 1+ (800) 334-5454
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*/
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/*
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* $Log: NCR5380.h,v $
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*/
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#ifndef NCR5380_H
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#define NCR5380_H
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#include <linux/interrupt.h>
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#define NCR5380_PUBLIC_RELEASE 7
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#define NCR53C400_PUBLIC_RELEASE 2
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#define NDEBUG_ARBITRATION 0x1
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#define NDEBUG_AUTOSENSE 0x2
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#define NDEBUG_DMA 0x4
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#define NDEBUG_HANDSHAKE 0x8
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#define NDEBUG_INFORMATION 0x10
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#define NDEBUG_INIT 0x20
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#define NDEBUG_INTR 0x40
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#define NDEBUG_LINKED 0x80
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#define NDEBUG_MAIN 0x100
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#define NDEBUG_NO_DATAOUT 0x200
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#define NDEBUG_NO_WRITE 0x400
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#define NDEBUG_PIO 0x800
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#define NDEBUG_PSEUDO_DMA 0x1000
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#define NDEBUG_QUEUES 0x2000
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#define NDEBUG_RESELECTION 0x4000
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#define NDEBUG_SELECTION 0x8000
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#define NDEBUG_USLEEP 0x10000
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#define NDEBUG_LAST_BYTE_SENT 0x20000
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#define NDEBUG_RESTART_SELECT 0x40000
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#define NDEBUG_EXTENDED 0x80000
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#define NDEBUG_C400_PREAD 0x100000
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#define NDEBUG_C400_PWRITE 0x200000
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#define NDEBUG_LISTS 0x400000
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#define NDEBUG_ANY 0xFFFFFFFFUL
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/*
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* The contents of the OUTPUT DATA register are asserted on the bus when
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* either arbitration is occurring or the phase-indicating signals (
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* IO, CD, MSG) in the TARGET COMMAND register and the ASSERT DATA
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* bit in the INITIATOR COMMAND register is set.
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*/
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#define OUTPUT_DATA_REG 0 /* wo DATA lines on SCSI bus */
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#define CURRENT_SCSI_DATA_REG 0 /* ro same */
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#define INITIATOR_COMMAND_REG 1 /* rw */
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#define ICR_ASSERT_RST 0x80 /* rw Set to assert RST */
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#define ICR_ARBITRATION_PROGRESS 0x40 /* ro Indicates arbitration complete */
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#define ICR_TRI_STATE 0x40 /* wo Set to tri-state drivers */
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#define ICR_ARBITRATION_LOST 0x20 /* ro Indicates arbitration lost */
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#define ICR_DIFF_ENABLE 0x20 /* wo Set to enable diff. drivers */
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#define ICR_ASSERT_ACK 0x10 /* rw ini Set to assert ACK */
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#define ICR_ASSERT_BSY 0x08 /* rw Set to assert BSY */
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#define ICR_ASSERT_SEL 0x04 /* rw Set to assert SEL */
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#define ICR_ASSERT_ATN 0x02 /* rw Set to assert ATN */
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#define ICR_ASSERT_DATA 0x01 /* rw SCSI_DATA_REG is asserted */
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#ifdef DIFFERENTIAL
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#define ICR_BASE ICR_DIFF_ENABLE
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#else
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#define ICR_BASE 0
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#endif
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#define MODE_REG 2
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/*
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* Note : BLOCK_DMA code will keep DRQ asserted for the duration of the
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* transfer, causing the chip to hog the bus. You probably don't want
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* this.
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*/
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#define MR_BLOCK_DMA_MODE 0x80 /* rw block mode DMA */
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#define MR_TARGET 0x40 /* rw target mode */
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#define MR_ENABLE_PAR_CHECK 0x20 /* rw enable parity checking */
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#define MR_ENABLE_PAR_INTR 0x10 /* rw enable bad parity interrupt */
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#define MR_ENABLE_EOP_INTR 0x08 /* rw enable eop interrupt */
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#define MR_MONITOR_BSY 0x04 /* rw enable int on unexpected bsy fail */
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#define MR_DMA_MODE 0x02 /* rw DMA / pseudo DMA mode */
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#define MR_ARBITRATE 0x01 /* rw start arbitration */
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#ifdef PARITY
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#define MR_BASE MR_ENABLE_PAR_CHECK
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#else
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#define MR_BASE 0
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#endif
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#define TARGET_COMMAND_REG 3
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#define TCR_LAST_BYTE_SENT 0x80 /* ro DMA done */
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#define TCR_ASSERT_REQ 0x08 /* tgt rw assert REQ */
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#define TCR_ASSERT_MSG 0x04 /* tgt rw assert MSG */
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#define TCR_ASSERT_CD 0x02 /* tgt rw assert CD */
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#define TCR_ASSERT_IO 0x01 /* tgt rw assert IO */
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#define STATUS_REG 4 /* ro */
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/*
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* Note : a set bit indicates an active signal, driven by us or another
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* device.
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*/
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#define SR_RST 0x80
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#define SR_BSY 0x40
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#define SR_REQ 0x20
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#define SR_MSG 0x10
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#define SR_CD 0x08
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#define SR_IO 0x04
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#define SR_SEL 0x02
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#define SR_DBP 0x01
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/*
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* Setting a bit in this register will cause an interrupt to be generated when
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* BSY is false and SEL true and this bit is asserted on the bus.
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*/
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#define SELECT_ENABLE_REG 4 /* wo */
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#define BUS_AND_STATUS_REG 5 /* ro */
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#define BASR_END_DMA_TRANSFER 0x80 /* ro set on end of transfer */
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#define BASR_DRQ 0x40 /* ro mirror of DRQ pin */
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#define BASR_PARITY_ERROR 0x20 /* ro parity error detected */
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#define BASR_IRQ 0x10 /* ro mirror of IRQ pin */
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#define BASR_PHASE_MATCH 0x08 /* ro Set when MSG CD IO match TCR */
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#define BASR_BUSY_ERROR 0x04 /* ro Unexpected change to inactive state */
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#define BASR_ATN 0x02 /* ro BUS status */
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#define BASR_ACK 0x01 /* ro BUS status */
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/* Write any value to this register to start a DMA send */
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#define START_DMA_SEND_REG 5 /* wo */
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/*
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* Used in DMA transfer mode, data is latched from the SCSI bus on
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* the falling edge of REQ (ini) or ACK (tgt)
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*/
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#define INPUT_DATA_REG 6 /* ro */
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/* Write any value to this register to start a DMA receive */
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#define START_DMA_TARGET_RECEIVE_REG 6 /* wo */
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/* Read this register to clear interrupt conditions */
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#define RESET_PARITY_INTERRUPT_REG 7 /* ro */
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/* Write any value to this register to start an ini mode DMA receive */
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#define START_DMA_INITIATOR_RECEIVE_REG 7 /* wo */
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#define C400_CONTROL_STATUS_REG NCR53C400_register_offset-8 /* rw */
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#define CSR_RESET 0x80 /* wo Resets 53c400 */
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#define CSR_53C80_REG 0x80 /* ro 5380 registers busy */
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#define CSR_TRANS_DIR 0x40 /* rw Data transfer direction */
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#define CSR_SCSI_BUFF_INTR 0x20 /* rw Enable int on transfer ready */
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#define CSR_53C80_INTR 0x10 /* rw Enable 53c80 interrupts */
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#define CSR_SHARED_INTR 0x08 /* rw Interrupt sharing */
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#define CSR_HOST_BUF_NOT_RDY 0x04 /* ro Is Host buffer ready */
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#define CSR_SCSI_BUF_RDY 0x02 /* ro SCSI buffer read */
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#define CSR_GATED_53C80_IRQ 0x01 /* ro Last block xferred */
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#if 0
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#define CSR_BASE CSR_SCSI_BUFF_INTR | CSR_53C80_INTR
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#else
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#define CSR_BASE CSR_53C80_INTR
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#endif
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/* Number of 128-byte blocks to be transferred */
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#define C400_BLOCK_COUNTER_REG NCR53C400_register_offset-7 /* rw */
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/* Resume transfer after disconnect */
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#define C400_RESUME_TRANSFER_REG NCR53C400_register_offset-6 /* wo */
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/* Access to host buffer stack */
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#define C400_HOST_BUFFER NCR53C400_register_offset-4 /* rw */
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/* Note : PHASE_* macros are based on the values of the STATUS register */
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#define PHASE_MASK (SR_MSG | SR_CD | SR_IO)
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#define PHASE_DATAOUT 0
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#define PHASE_DATAIN SR_IO
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#define PHASE_CMDOUT SR_CD
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#define PHASE_STATIN (SR_CD | SR_IO)
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#define PHASE_MSGOUT (SR_MSG | SR_CD)
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#define PHASE_MSGIN (SR_MSG | SR_CD | SR_IO)
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#define PHASE_UNKNOWN 0xff
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/*
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* Convert status register phase to something we can use to set phase in
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* the target register so we can get phase mismatch interrupts on DMA
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* transfers.
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*/
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#define PHASE_SR_TO_TCR(phase) ((phase) >> 2)
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/*
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* The internal should_disconnect() function returns these based on the
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* expected length of a disconnect if a device supports disconnect/
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* reconnect.
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*/
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#define DISCONNECT_NONE 0
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#define DISCONNECT_TIME_TO_DATA 1
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#define DISCONNECT_LONG 2
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/*
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* These are "special" values for the tag parameter passed to NCR5380_select.
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*/
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#define TAG_NEXT -1 /* Use next free tag */
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#define TAG_NONE -2 /*
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* Establish I_T_L nexus instead of I_T_L_Q
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* even on SCSI-II devices.
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*/
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/*
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* These are "special" values for the irq and dma_channel fields of the
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* Scsi_Host structure
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*/
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#define SCSI_IRQ_NONE 255
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#define DMA_NONE 255
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#define IRQ_AUTO 254
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#define DMA_AUTO 254
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#define PORT_AUTO 0xffff /* autoprobe io port for 53c400a */
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#define FLAG_HAS_LAST_BYTE_SENT 1 /* NCR53c81 or better */
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#define FLAG_CHECK_LAST_BYTE_SENT 2 /* Only test once */
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#define FLAG_NCR53C400 4 /* NCR53c400 */
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#define FLAG_NO_PSEUDO_DMA 8 /* Inhibit DMA */
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#define FLAG_DTC3181E 16 /* DTC3181E */
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#ifndef ASM
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struct NCR5380_hostdata {
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NCR5380_implementation_fields; /* implementation specific */
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struct Scsi_Host *host; /* Host backpointer */
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unsigned char id_mask, id_higher_mask; /* 1 << id, all bits greater */
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unsigned char targets_present; /* targets we have connected
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to, so we can call a select
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failure a retryable condition */
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volatile unsigned char busy[8]; /* index = target, bit = lun */
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#if defined(REAL_DMA) || defined(REAL_DMA_POLL)
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volatile int dma_len; /* requested length of DMA */
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#endif
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volatile unsigned char last_message; /* last message OUT */
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volatile Scsi_Cmnd *connected; /* currently connected command */
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volatile Scsi_Cmnd *issue_queue; /* waiting to be issued */
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volatile Scsi_Cmnd *disconnected_queue; /* waiting for reconnect */
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volatile int restart_select; /* we have disconnected,
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used to restart
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NCR5380_select() */
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volatile unsigned aborted:1; /* flag, says aborted */
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int flags;
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unsigned long time_expires; /* in jiffies, set prior to sleeping */
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int select_time; /* timer in select for target response */
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volatile Scsi_Cmnd *selecting;
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struct work_struct coroutine; /* our co-routine */
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#ifdef NCR5380_STATS
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unsigned timebase; /* Base for time calcs */
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long time_read[8]; /* time to do reads */
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long time_write[8]; /* time to do writes */
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unsigned long bytes_read[8]; /* bytes read */
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unsigned long bytes_write[8]; /* bytes written */
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unsigned pendingr;
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unsigned pendingw;
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#endif
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};
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#ifdef __KERNEL__
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#define dprintk(a,b) do {} while(0)
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#define NCR5380_dprint(a,b) do {} while(0)
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#define NCR5380_dprint_phase(a,b) do {} while(0)
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#if defined(AUTOPROBE_IRQ)
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static int NCR5380_probe_irq(struct Scsi_Host *instance, int possible);
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#endif
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static int NCR5380_init(struct Scsi_Host *instance, int flags);
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static void NCR5380_exit(struct Scsi_Host *instance);
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static void NCR5380_information_transfer(struct Scsi_Host *instance);
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#ifndef DONT_USE_INTR
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static irqreturn_t NCR5380_intr(int irq, void *dev_id, struct pt_regs *regs);
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#endif
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static void NCR5380_main(void *ptr);
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static void NCR5380_print_options(struct Scsi_Host *instance);
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#ifdef NDEBUG
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static void NCR5380_print_phase(struct Scsi_Host *instance);
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static void NCR5380_print(struct Scsi_Host *instance);
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#endif
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static int NCR5380_abort(Scsi_Cmnd * cmd);
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static int NCR5380_bus_reset(Scsi_Cmnd * cmd);
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static int NCR5380_queue_command(Scsi_Cmnd * cmd, void (*done) (Scsi_Cmnd *));
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static int NCR5380_proc_info(struct Scsi_Host *instance, char *buffer, char **start,
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off_t offset, int length, int inout);
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static void NCR5380_reselect(struct Scsi_Host *instance);
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static int NCR5380_select(struct Scsi_Host *instance, Scsi_Cmnd * cmd, int tag);
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#if defined(PSEUDO_DMA) || defined(REAL_DMA) || defined(REAL_DMA_POLL)
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static int NCR5380_transfer_dma(struct Scsi_Host *instance, unsigned char *phase, int *count, unsigned char **data);
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#endif
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static int NCR5380_transfer_pio(struct Scsi_Host *instance, unsigned char *phase, int *count, unsigned char **data);
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#if (defined(REAL_DMA) || defined(REAL_DMA_POLL))
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#if defined(i386) || defined(__alpha__)
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/**
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* NCR5380_pc_dma_setup - setup ISA DMA
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* @instance: adapter to set up
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* @ptr: block to transfer (virtual address)
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* @count: number of bytes to transfer
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* @mode: DMA controller mode to use
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*
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* Program the DMA controller ready to perform an ISA DMA transfer
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* on this chip.
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*
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* Locks: takes and releases the ISA DMA lock.
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*/
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static __inline__ int NCR5380_pc_dma_setup(struct Scsi_Host *instance, unsigned char *ptr, unsigned int count, unsigned char mode)
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{
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unsigned limit;
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unsigned long bus_addr = virt_to_bus(ptr);
|
||
|
|
unsigned long flags;
|
||
|
|
|
||
|
|
if (instance->dma_channel <= 3) {
|
||
|
|
if (count > 65536)
|
||
|
|
count = 65536;
|
||
|
|
limit = 65536 - (bus_addr & 0xFFFF);
|
||
|
|
} else {
|
||
|
|
if (count > 65536 * 2)
|
||
|
|
count = 65536 * 2;
|
||
|
|
limit = 65536 * 2 - (bus_addr & 0x1FFFF);
|
||
|
|
}
|
||
|
|
|
||
|
|
if (count > limit)
|
||
|
|
count = limit;
|
||
|
|
|
||
|
|
if ((count & 1) || (bus_addr & 1))
|
||
|
|
panic("scsi%d : attempted unaligned DMA transfer\n", instance->host_no);
|
||
|
|
|
||
|
|
flags=claim_dma_lock();
|
||
|
|
disable_dma(instance->dma_channel);
|
||
|
|
clear_dma_ff(instance->dma_channel);
|
||
|
|
set_dma_addr(instance->dma_channel, bus_addr);
|
||
|
|
set_dma_count(instance->dma_channel, count);
|
||
|
|
set_dma_mode(instance->dma_channel, mode);
|
||
|
|
enable_dma(instance->dma_channel);
|
||
|
|
release_dma_lock(flags);
|
||
|
|
|
||
|
|
return count;
|
||
|
|
}
|
||
|
|
|
||
|
|
/**
|
||
|
|
* NCR5380_pc_dma_write_setup - setup ISA DMA write
|
||
|
|
* @instance: adapter to set up
|
||
|
|
* @ptr: block to transfer (virtual address)
|
||
|
|
* @count: number of bytes to transfer
|
||
|
|
*
|
||
|
|
* Program the DMA controller ready to perform an ISA DMA write to the
|
||
|
|
* SCSI controller.
|
||
|
|
*
|
||
|
|
* Locks: called routines take and release the ISA DMA lock.
|
||
|
|
*/
|
||
|
|
|
||
|
|
static __inline__ int NCR5380_pc_dma_write_setup(struct Scsi_Host *instance, unsigned char *src, unsigned int count)
|
||
|
|
{
|
||
|
|
return NCR5380_pc_dma_setup(instance, src, count, DMA_MODE_WRITE);
|
||
|
|
}
|
||
|
|
|
||
|
|
/**
|
||
|
|
* NCR5380_pc_dma_read_setup - setup ISA DMA read
|
||
|
|
* @instance: adapter to set up
|
||
|
|
* @ptr: block to transfer (virtual address)
|
||
|
|
* @count: number of bytes to transfer
|
||
|
|
*
|
||
|
|
* Program the DMA controller ready to perform an ISA DMA read from the
|
||
|
|
* SCSI controller.
|
||
|
|
*
|
||
|
|
* Locks: called routines take and release the ISA DMA lock.
|
||
|
|
*/
|
||
|
|
|
||
|
|
static __inline__ int NCR5380_pc_dma_read_setup(struct Scsi_Host *instance, unsigned char *src, unsigned int count)
|
||
|
|
{
|
||
|
|
return NCR5380_pc_dma_setup(instance, src, count, DMA_MODE_READ);
|
||
|
|
}
|
||
|
|
|
||
|
|
/**
|
||
|
|
* NCR5380_pc_dma_residual - return bytes left
|
||
|
|
* @instance: adapter
|
||
|
|
*
|
||
|
|
* Reports the number of bytes left over after the DMA was terminated.
|
||
|
|
*
|
||
|
|
* Locks: takes and releases the ISA DMA lock.
|
||
|
|
*/
|
||
|
|
|
||
|
|
static __inline__ int NCR5380_pc_dma_residual(struct Scsi_Host *instance)
|
||
|
|
{
|
||
|
|
unsigned long flags;
|
||
|
|
int tmp;
|
||
|
|
|
||
|
|
flags = claim_dma_lock();
|
||
|
|
clear_dma_ff(instance->dma_channel);
|
||
|
|
tmp = get_dma_residue(instance->dma_channel);
|
||
|
|
release_dma_lock(flags);
|
||
|
|
|
||
|
|
return tmp;
|
||
|
|
}
|
||
|
|
#endif /* defined(i386) || defined(__alpha__) */
|
||
|
|
#endif /* defined(REAL_DMA) */
|
||
|
|
#endif /* __KERNEL__ */
|
||
|
|
#endif /* ndef ASM */
|
||
|
|
#endif /* NCR5380_H */
|