2016-11-22 06:44:09 -07:00
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/*
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* Shared descriptors for aead, ablkcipher algorithms
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*
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* Copyright 2016 NXP
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*/
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#ifndef _CAAMALG_DESC_H_
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#define _CAAMALG_DESC_H_
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/* length of descriptors text */
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#define DESC_AEAD_BASE (4 * CAAM_CMD_SZ)
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#define DESC_AEAD_ENC_LEN (DESC_AEAD_BASE + 11 * CAAM_CMD_SZ)
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#define DESC_AEAD_DEC_LEN (DESC_AEAD_BASE + 15 * CAAM_CMD_SZ)
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#define DESC_AEAD_GIVENC_LEN (DESC_AEAD_ENC_LEN + 7 * CAAM_CMD_SZ)
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crypto: caam/qi - add ablkcipher and authenc algorithms
Add support to submit ablkcipher and authenc algorithms
via the QI backend:
-ablkcipher:
cbc({aes,des,des3_ede})
ctr(aes), rfc3686(ctr(aes))
xts(aes)
-authenc:
authenc(hmac(md5),cbc({aes,des,des3_ede}))
authenc(hmac(sha*),cbc({aes,des,des3_ede}))
caam/qi being a new driver, let's wait some time to settle down without
interfering with existing caam/jr driver.
Accordingly, for now all caam/qi algorithms (caamalg_qi module) are
marked to be of lower priority than caam/jr ones (caamalg module).
Signed-off-by: Vakul Garg <vakul.garg@nxp.com>
Signed-off-by: Alex Porosanu <alexandru.porosanu@nxp.com>
Signed-off-by: Horia Geantă <horia.geanta@nxp.com>
Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2017-03-17 04:06:02 -06:00
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#define DESC_QI_AEAD_ENC_LEN (DESC_AEAD_ENC_LEN + 3 * CAAM_CMD_SZ)
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#define DESC_QI_AEAD_DEC_LEN (DESC_AEAD_DEC_LEN + 3 * CAAM_CMD_SZ)
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#define DESC_QI_AEAD_GIVENC_LEN (DESC_AEAD_GIVENC_LEN + 3 * CAAM_CMD_SZ)
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2016-11-22 06:44:09 -07:00
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/* Note: Nonce is counted in cdata.keylen */
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#define DESC_AEAD_CTR_RFC3686_LEN (4 * CAAM_CMD_SZ)
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#define DESC_AEAD_NULL_BASE (3 * CAAM_CMD_SZ)
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#define DESC_AEAD_NULL_ENC_LEN (DESC_AEAD_NULL_BASE + 11 * CAAM_CMD_SZ)
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#define DESC_AEAD_NULL_DEC_LEN (DESC_AEAD_NULL_BASE + 13 * CAAM_CMD_SZ)
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#define DESC_GCM_BASE (3 * CAAM_CMD_SZ)
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#define DESC_GCM_ENC_LEN (DESC_GCM_BASE + 16 * CAAM_CMD_SZ)
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#define DESC_GCM_DEC_LEN (DESC_GCM_BASE + 12 * CAAM_CMD_SZ)
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#define DESC_RFC4106_BASE (3 * CAAM_CMD_SZ)
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#define DESC_RFC4106_ENC_LEN (DESC_RFC4106_BASE + 13 * CAAM_CMD_SZ)
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#define DESC_RFC4106_DEC_LEN (DESC_RFC4106_BASE + 13 * CAAM_CMD_SZ)
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#define DESC_RFC4543_BASE (3 * CAAM_CMD_SZ)
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#define DESC_RFC4543_ENC_LEN (DESC_RFC4543_BASE + 11 * CAAM_CMD_SZ)
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#define DESC_RFC4543_DEC_LEN (DESC_RFC4543_BASE + 12 * CAAM_CMD_SZ)
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#define DESC_ABLKCIPHER_BASE (3 * CAAM_CMD_SZ)
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#define DESC_ABLKCIPHER_ENC_LEN (DESC_ABLKCIPHER_BASE + \
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20 * CAAM_CMD_SZ)
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#define DESC_ABLKCIPHER_DEC_LEN (DESC_ABLKCIPHER_BASE + \
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15 * CAAM_CMD_SZ)
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void cnstr_shdsc_aead_null_encap(u32 * const desc, struct alginfo *adata,
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unsigned int icvsize);
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void cnstr_shdsc_aead_null_decap(u32 * const desc, struct alginfo *adata,
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unsigned int icvsize);
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void cnstr_shdsc_aead_encap(u32 * const desc, struct alginfo *cdata,
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crypto: caam/qi - add ablkcipher and authenc algorithms
Add support to submit ablkcipher and authenc algorithms
via the QI backend:
-ablkcipher:
cbc({aes,des,des3_ede})
ctr(aes), rfc3686(ctr(aes))
xts(aes)
-authenc:
authenc(hmac(md5),cbc({aes,des,des3_ede}))
authenc(hmac(sha*),cbc({aes,des,des3_ede}))
caam/qi being a new driver, let's wait some time to settle down without
interfering with existing caam/jr driver.
Accordingly, for now all caam/qi algorithms (caamalg_qi module) are
marked to be of lower priority than caam/jr ones (caamalg module).
Signed-off-by: Vakul Garg <vakul.garg@nxp.com>
Signed-off-by: Alex Porosanu <alexandru.porosanu@nxp.com>
Signed-off-by: Horia Geantă <horia.geanta@nxp.com>
Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2017-03-17 04:06:02 -06:00
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struct alginfo *adata, unsigned int ivsize,
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unsigned int icvsize, const bool is_rfc3686,
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u32 *nonce, const u32 ctx1_iv_off,
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const bool is_qi);
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2016-11-22 06:44:09 -07:00
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void cnstr_shdsc_aead_decap(u32 * const desc, struct alginfo *cdata,
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struct alginfo *adata, unsigned int ivsize,
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unsigned int icvsize, const bool geniv,
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const bool is_rfc3686, u32 *nonce,
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crypto: caam/qi - add ablkcipher and authenc algorithms
Add support to submit ablkcipher and authenc algorithms
via the QI backend:
-ablkcipher:
cbc({aes,des,des3_ede})
ctr(aes), rfc3686(ctr(aes))
xts(aes)
-authenc:
authenc(hmac(md5),cbc({aes,des,des3_ede}))
authenc(hmac(sha*),cbc({aes,des,des3_ede}))
caam/qi being a new driver, let's wait some time to settle down without
interfering with existing caam/jr driver.
Accordingly, for now all caam/qi algorithms (caamalg_qi module) are
marked to be of lower priority than caam/jr ones (caamalg module).
Signed-off-by: Vakul Garg <vakul.garg@nxp.com>
Signed-off-by: Alex Porosanu <alexandru.porosanu@nxp.com>
Signed-off-by: Horia Geantă <horia.geanta@nxp.com>
Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2017-03-17 04:06:02 -06:00
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const u32 ctx1_iv_off, const bool is_qi);
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2016-11-22 06:44:09 -07:00
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void cnstr_shdsc_aead_givencap(u32 * const desc, struct alginfo *cdata,
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struct alginfo *adata, unsigned int ivsize,
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unsigned int icvsize, const bool is_rfc3686,
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crypto: caam/qi - add ablkcipher and authenc algorithms
Add support to submit ablkcipher and authenc algorithms
via the QI backend:
-ablkcipher:
cbc({aes,des,des3_ede})
ctr(aes), rfc3686(ctr(aes))
xts(aes)
-authenc:
authenc(hmac(md5),cbc({aes,des,des3_ede}))
authenc(hmac(sha*),cbc({aes,des,des3_ede}))
caam/qi being a new driver, let's wait some time to settle down without
interfering with existing caam/jr driver.
Accordingly, for now all caam/qi algorithms (caamalg_qi module) are
marked to be of lower priority than caam/jr ones (caamalg module).
Signed-off-by: Vakul Garg <vakul.garg@nxp.com>
Signed-off-by: Alex Porosanu <alexandru.porosanu@nxp.com>
Signed-off-by: Horia Geantă <horia.geanta@nxp.com>
Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2017-03-17 04:06:02 -06:00
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u32 *nonce, const u32 ctx1_iv_off,
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const bool is_qi);
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2016-11-22 06:44:09 -07:00
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void cnstr_shdsc_gcm_encap(u32 * const desc, struct alginfo *cdata,
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unsigned int icvsize);
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void cnstr_shdsc_gcm_decap(u32 * const desc, struct alginfo *cdata,
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unsigned int icvsize);
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void cnstr_shdsc_rfc4106_encap(u32 * const desc, struct alginfo *cdata,
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unsigned int icvsize);
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void cnstr_shdsc_rfc4106_decap(u32 * const desc, struct alginfo *cdata,
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unsigned int icvsize);
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void cnstr_shdsc_rfc4543_encap(u32 * const desc, struct alginfo *cdata,
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unsigned int icvsize);
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void cnstr_shdsc_rfc4543_decap(u32 * const desc, struct alginfo *cdata,
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unsigned int icvsize);
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void cnstr_shdsc_ablkcipher_encap(u32 * const desc, struct alginfo *cdata,
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unsigned int ivsize, const bool is_rfc3686,
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const u32 ctx1_iv_off);
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void cnstr_shdsc_ablkcipher_decap(u32 * const desc, struct alginfo *cdata,
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unsigned int ivsize, const bool is_rfc3686,
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const u32 ctx1_iv_off);
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void cnstr_shdsc_ablkcipher_givencap(u32 * const desc, struct alginfo *cdata,
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unsigned int ivsize, const bool is_rfc3686,
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const u32 ctx1_iv_off);
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void cnstr_shdsc_xts_ablkcipher_encap(u32 * const desc, struct alginfo *cdata);
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void cnstr_shdsc_xts_ablkcipher_decap(u32 * const desc, struct alginfo *cdata);
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#endif /* _CAAMALG_DESC_H_ */
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