2009-01-19 23:15:18 -07:00
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/*
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* linux/arch/arm/mach-mmp/time.c
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*
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* Support for clocksource and clockevents
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*
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* Copyright (C) 2008 Marvell International Ltd.
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* All rights reserved.
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*
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* 2008-04-11: Jason Chagas <Jason.chagas@marvell.com>
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* 2008-10-08: Bin Yang <bin.yang@marvell.com>
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*
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2011-03-30 19:57:33 -06:00
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* The timers module actually includes three timers, each timer with up to
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2009-01-19 23:15:18 -07:00
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* three match comparators. Timer #0 is used here in free-running mode as
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* the clock source, and match comparator #1 used as clock event device.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include <linux/init.h>
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#include <linux/kernel.h>
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#include <linux/interrupt.h>
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#include <linux/clockchips.h>
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#include <linux/io.h>
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#include <linux/irq.h>
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#include <linux/sched.h>
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2010-12-15 14:46:48 -07:00
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#include <asm/sched_clock.h>
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2009-01-19 23:15:18 -07:00
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#include <mach/addr-map.h>
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#include <mach/regs-timers.h>
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2009-12-04 07:41:28 -07:00
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#include <mach/regs-apbc.h>
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2009-01-19 23:15:18 -07:00
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#include <mach/irqs.h>
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2009-12-04 07:41:28 -07:00
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#include <mach/cputype.h>
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#include <asm/mach/time.h>
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2009-01-19 23:15:18 -07:00
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#include "clock.h"
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#define TIMERS_VIRT_BASE TIMERS1_VIRT_BASE
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#define MAX_DELTA (0xfffffffe)
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#define MIN_DELTA (16)
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2010-12-15 14:46:48 -07:00
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static DEFINE_CLOCK_DATA(cd);
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2009-01-19 23:15:18 -07:00
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/*
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* FIXME: the timer needs some delay to stablize the counter capture
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*/
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static inline uint32_t timer_read(void)
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{
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int delay = 100;
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2011-08-09 12:37:34 -06:00
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__raw_writel(1, TIMERS_VIRT_BASE + TMR_CVWR(1));
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2009-01-19 23:15:18 -07:00
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while (delay--)
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cpu_relax();
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2011-08-09 12:37:34 -06:00
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return __raw_readl(TIMERS_VIRT_BASE + TMR_CVWR(1));
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2009-01-19 23:15:18 -07:00
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}
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2010-12-15 12:19:25 -07:00
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unsigned long long notrace sched_clock(void)
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2009-01-19 23:15:18 -07:00
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{
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2010-12-15 14:46:48 -07:00
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u32 cyc = timer_read();
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return cyc_to_sched_clock(&cd, cyc, (u32)~0);
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}
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static void notrace mmp_update_sched_clock(void)
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{
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u32 cyc = timer_read();
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update_sched_clock(&cd, cyc, (u32)~0);
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2009-01-19 23:15:18 -07:00
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}
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static irqreturn_t timer_interrupt(int irq, void *dev_id)
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{
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struct clock_event_device *c = dev_id;
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2011-08-09 12:37:55 -06:00
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/*
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* Clear pending interrupt status.
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*/
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__raw_writel(0x01, TIMERS_VIRT_BASE + TMR_ICR(0));
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/*
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* Disable timer 0.
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*/
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__raw_writel(0x02, TIMERS_VIRT_BASE + TMR_CER);
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2009-01-19 23:15:18 -07:00
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c->event_handler(c);
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2011-08-09 12:37:55 -06:00
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2009-01-19 23:15:18 -07:00
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return IRQ_HANDLED;
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}
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static int timer_set_next_event(unsigned long delta,
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struct clock_event_device *dev)
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{
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2011-08-09 12:37:55 -06:00
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unsigned long flags;
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2009-01-19 23:15:18 -07:00
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local_irq_save(flags);
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2011-08-09 12:37:55 -06:00
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/*
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* Disable timer 0.
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*/
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__raw_writel(0x02, TIMERS_VIRT_BASE + TMR_CER);
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/*
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* Clear and enable timer match 0 interrupt.
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*/
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2009-01-19 23:15:18 -07:00
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__raw_writel(0x01, TIMERS_VIRT_BASE + TMR_ICR(0));
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__raw_writel(0x01, TIMERS_VIRT_BASE + TMR_IER(0));
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2011-08-09 12:37:55 -06:00
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/*
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* Setup new clockevent timer value.
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*/
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__raw_writel(delta - 1, TIMERS_VIRT_BASE + TMR_TN_MM(0, 0));
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/*
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* Enable timer 0.
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*/
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__raw_writel(0x03, TIMERS_VIRT_BASE + TMR_CER);
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2009-01-19 23:15:18 -07:00
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local_irq_restore(flags);
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2011-08-09 12:37:55 -06:00
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2009-01-19 23:15:18 -07:00
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return 0;
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}
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static void timer_set_mode(enum clock_event_mode mode,
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struct clock_event_device *dev)
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{
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unsigned long flags;
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local_irq_save(flags);
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switch (mode) {
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case CLOCK_EVT_MODE_ONESHOT:
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case CLOCK_EVT_MODE_UNUSED:
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case CLOCK_EVT_MODE_SHUTDOWN:
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/* disable the matching interrupt */
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__raw_writel(0x00, TIMERS_VIRT_BASE + TMR_IER(0));
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break;
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case CLOCK_EVT_MODE_RESUME:
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case CLOCK_EVT_MODE_PERIODIC:
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break;
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}
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local_irq_restore(flags);
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}
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static struct clock_event_device ckevt = {
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.name = "clockevent",
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.features = CLOCK_EVT_FEAT_ONESHOT,
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.shift = 32,
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.rating = 200,
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.set_next_event = timer_set_next_event,
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.set_mode = timer_set_mode,
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};
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2009-04-22 13:04:45 -06:00
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static cycle_t clksrc_read(struct clocksource *cs)
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2009-01-19 23:15:18 -07:00
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{
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return timer_read();
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}
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static struct clocksource cksrc = {
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.name = "clocksource",
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.rating = 200,
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.read = clksrc_read,
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.mask = CLOCKSOURCE_MASK(32),
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.flags = CLOCK_SOURCE_IS_CONTINUOUS,
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};
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static void __init timer_config(void)
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{
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uint32_t ccr = __raw_readl(TIMERS_VIRT_BASE + TMR_CCR);
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2011-08-09 12:36:59 -06:00
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__raw_writel(0x0, TIMERS_VIRT_BASE + TMR_CER); /* disable */
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2009-01-19 23:15:18 -07:00
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2011-08-09 12:36:59 -06:00
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ccr &= (cpu_is_mmp2()) ? (TMR_CCR_CS_0(0) | TMR_CCR_CS_1(0)) :
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(TMR_CCR_CS_0(3) | TMR_CCR_CS_1(3));
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2009-01-19 23:15:18 -07:00
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__raw_writel(ccr, TIMERS_VIRT_BASE + TMR_CCR);
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2011-08-09 12:37:55 -06:00
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/* set timer 0 to periodic mode, and timer 1 to free-running mode */
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__raw_writel(0x2, TIMERS_VIRT_BASE + TMR_CMR);
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2009-01-19 23:15:18 -07:00
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2011-08-09 12:37:55 -06:00
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__raw_writel(0x1, TIMERS_VIRT_BASE + TMR_PLCR(0)); /* periodic */
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2009-01-19 23:15:18 -07:00
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__raw_writel(0x7, TIMERS_VIRT_BASE + TMR_ICR(0)); /* clear status */
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__raw_writel(0x0, TIMERS_VIRT_BASE + TMR_IER(0));
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2011-08-09 12:36:59 -06:00
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__raw_writel(0x0, TIMERS_VIRT_BASE + TMR_PLCR(1)); /* free-running */
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__raw_writel(0x7, TIMERS_VIRT_BASE + TMR_ICR(1)); /* clear status */
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__raw_writel(0x0, TIMERS_VIRT_BASE + TMR_IER(1));
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2011-08-09 12:37:55 -06:00
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/* enable timer 1 counter */
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__raw_writel(0x2, TIMERS_VIRT_BASE + TMR_CER);
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2009-01-19 23:15:18 -07:00
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}
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static struct irqaction timer_irq = {
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.name = "timer",
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.flags = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL,
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.handler = timer_interrupt,
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.dev_id = &ckevt,
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};
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void __init timer_init(int irq)
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{
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timer_config();
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2010-12-15 14:46:48 -07:00
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init_sched_clock(&cd, mmp_update_sched_clock, 32, CLOCK_TICK_RATE);
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2009-01-19 23:15:18 -07:00
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ckevt.mult = div_sc(CLOCK_TICK_RATE, NSEC_PER_SEC, ckevt.shift);
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ckevt.max_delta_ns = clockevent_delta2ns(MAX_DELTA, &ckevt);
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ckevt.min_delta_ns = clockevent_delta2ns(MIN_DELTA, &ckevt);
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ckevt.cpumask = cpumask_of(0);
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setup_irq(irq, &timer_irq);
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2010-12-13 06:18:04 -07:00
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clocksource_register_hz(&cksrc, CLOCK_TICK_RATE);
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2009-01-19 23:15:18 -07:00
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clockevents_register_device(&ckevt);
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}
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