2008-09-12 01:19:21 -06:00
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#ifndef _SPARC64_MM_INIT_H
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#define _SPARC64_MM_INIT_H
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2013-09-18 16:39:06 -06:00
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#include <asm/page.h>
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2008-09-12 01:19:21 -06:00
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/* Most of the symbols in this file are defined in init.c and
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* marked non-static so that assembler code can get at them.
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*/
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2013-09-18 16:39:06 -06:00
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#define MAX_PHYS_ADDRESS (1UL << MAX_PHYS_ADDRESS_BITS)
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sparc64: Validate linear D-TLB misses.
When page alloc debugging is not enabled, we essentially accept any
virtual address for linear kernel TLB misses. But with kgdb, kernel
address probing, and other facilities we can try to access arbitrary
crap.
So, make sure the address we miss on will translate to physical memory
that actually exists.
In order to make this work we have to embed the valid address bitmap
into the kernel image. And in order to make that less expensive we
make an adjustment, in that the max physical memory address is
decreased to "1 << 41", even on the chips that support a 42-bit
physical address space. We can do this because bit 41 indicates
"I/O space" and thus covers non-memory ranges.
The result of this is that:
1) kpte_linear_bitmap shrinks from 2K to 1K in size
2) we need 64K more for the valid address bitmap
We can't let the valid address bitmap be dynamically allocated
once we start using it to validate TLB misses, otherwise we have
crazy issues to deal with wrt. recursive TLB misses and such.
If we're in a TLB miss it could be the deepest trap level that's legal
inside of the cpu. So if we TLB miss referencing the bitmap, the cpu
will be out of trap levels and enter RED state.
To guard against out-of-range accesses to the bitmap, we have to check
to make sure no bits in the physical address above bit 40 are set. We
could export and use last_valid_pfn for this check, but that's just an
unnecessary extra memory reference.
On the plus side of all this, since we load all of these translations
into the special 4MB mapping TSB, and we check the TSB first for TLB
misses, there should be absolutely no real cost for these new checks
in the TLB miss path.
Reported-by: heyongli@gmail.com
Signed-off-by: David S. Miller <davem@davemloft.net>
2009-08-25 17:47:46 -06:00
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#define KPTE_BITMAP_CHUNK_SZ (256UL * 1024UL * 1024UL)
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2008-09-12 01:19:21 -06:00
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#define KPTE_BITMAP_BYTES \
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2012-09-06 19:13:58 -06:00
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((MAX_PHYS_ADDRESS / KPTE_BITMAP_CHUNK_SZ) / 4)
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sparc64: Validate linear D-TLB misses.
When page alloc debugging is not enabled, we essentially accept any
virtual address for linear kernel TLB misses. But with kgdb, kernel
address probing, and other facilities we can try to access arbitrary
crap.
So, make sure the address we miss on will translate to physical memory
that actually exists.
In order to make this work we have to embed the valid address bitmap
into the kernel image. And in order to make that less expensive we
make an adjustment, in that the max physical memory address is
decreased to "1 << 41", even on the chips that support a 42-bit
physical address space. We can do this because bit 41 indicates
"I/O space" and thus covers non-memory ranges.
The result of this is that:
1) kpte_linear_bitmap shrinks from 2K to 1K in size
2) we need 64K more for the valid address bitmap
We can't let the valid address bitmap be dynamically allocated
once we start using it to validate TLB misses, otherwise we have
crazy issues to deal with wrt. recursive TLB misses and such.
If we're in a TLB miss it could be the deepest trap level that's legal
inside of the cpu. So if we TLB miss referencing the bitmap, the cpu
will be out of trap levels and enter RED state.
To guard against out-of-range accesses to the bitmap, we have to check
to make sure no bits in the physical address above bit 40 are set. We
could export and use last_valid_pfn for this check, but that's just an
unnecessary extra memory reference.
On the plus side of all this, since we load all of these translations
into the special 4MB mapping TSB, and we check the TSB first for TLB
misses, there should be absolutely no real cost for these new checks
in the TLB miss path.
Reported-by: heyongli@gmail.com
Signed-off-by: David S. Miller <davem@davemloft.net>
2009-08-25 17:47:46 -06:00
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#define VALID_ADDR_BITMAP_CHUNK_SZ (4UL * 1024UL * 1024UL)
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#define VALID_ADDR_BITMAP_BYTES \
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((MAX_PHYS_ADDRESS / VALID_ADDR_BITMAP_CHUNK_SZ) / 8)
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2008-09-12 01:19:21 -06:00
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2012-09-06 19:13:58 -06:00
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extern unsigned long kern_linear_pte_xor[4];
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2008-09-12 01:19:21 -06:00
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extern unsigned long kpte_linear_bitmap[KPTE_BITMAP_BYTES / sizeof(unsigned long)];
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extern unsigned int sparc64_highest_unlocked_tlb_ent;
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extern unsigned long sparc64_kern_pri_context;
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extern unsigned long sparc64_kern_pri_nuc_bits;
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extern unsigned long sparc64_kern_sec_context;
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extern void mmu_info(struct seq_file *m);
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struct linux_prom_translation {
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unsigned long virt;
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unsigned long size;
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unsigned long data;
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};
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/* Exported for kernel TLB miss handling in ktlb.S */
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extern struct linux_prom_translation prom_trans[512];
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extern unsigned int prom_trans_ents;
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/* Exported for SMP bootup purposes. */
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extern unsigned long kern_locked_tte_data;
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extern void prom_world(int enter);
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#ifdef CONFIG_SPARSEMEM_VMEMMAP
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#define VMEMMAP_CHUNK_SHIFT 22
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#define VMEMMAP_CHUNK (1UL << VMEMMAP_CHUNK_SHIFT)
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#define VMEMMAP_CHUNK_MASK ~(VMEMMAP_CHUNK - 1UL)
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#define VMEMMAP_ALIGN(x) (((x)+VMEMMAP_CHUNK-1UL)&VMEMMAP_CHUNK_MASK)
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#define VMEMMAP_SIZE ((((1UL << MAX_PHYSADDR_BITS) >> PAGE_SHIFT) * \
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2009-11-23 17:38:56 -07:00
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sizeof(struct page)) >> VMEMMAP_CHUNK_SHIFT)
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2008-09-12 01:19:21 -06:00
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extern unsigned long vmemmap_table[VMEMMAP_SIZE];
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#endif
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#endif /* _SPARC64_MM_INIT_H */
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