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kernel-fxtec-pro1x/drivers/crypto/Makefile

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[CRYPTO] padlock: Get rid of padlock-generic.c Merge padlock-generic.c into padlock-aes.c and compile AES as a standalone module. We won't make a monolithic padlock.ko with all supported algorithms, instead we'll compile each driver into its own module. Signed-off-by: Michal Ludvig <michal@logix.cz> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2006-08-06 06:46:20 -06:00
obj-$(CONFIG_CRYPTO_DEV_PADLOCK_AES) += padlock-aes.o
[CRYPTO] padlock: Driver for SHA1 / SHA256 algorithms Support for SHA1 / SHA256 algorithms in VIA C7 processors. Signed-off-by: Michal Ludvig <michal@logix.cz> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2006-07-11 20:29:38 -06:00
obj-$(CONFIG_CRYPTO_DEV_PADLOCK_SHA) += padlock-sha.o
[PATCH] crypto: Add support for the Geode LX AES hardware Add a driver to support the AES hardware on the Geode LX processor. Signed-off-by: Jordan Crouse <jordan.crouse@amd.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2006-10-04 02:48:57 -06:00
obj-$(CONFIG_CRYPTO_DEV_GEODE) += geode-aes.o
crypto: n2 - Add Niagara2 crypto driver Current deficiencies: 1) No HMAC hash support yet. 2) Although the algs are registered as ASYNC they always run synchronously. Signed-off-by: David S. Miller <davem@davemloft.net> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2010-05-18 22:14:04 -06:00
obj-$(CONFIG_CRYPTO_DEV_NIAGARA2) += n2_crypto.o
crypto: Makefile - replace the use of <module>-objs with <module>-y Changed <module>-objs to <module>-y in Makefile. Signed-off-by: Tracey Dent <tdent48227@gmail.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2010-10-19 06:52:26 -06:00
n2_crypto-y := n2_core.o n2_asm.o
[CRYPTO] hifn_795x: HIFN 795x driver This is a driver for HIFN 795x crypto accelerator chips. It passed all tests for AES, DES and DES3_EDE except weak test for DES, since hardware can not determine weak keys. Signed-off-by: Evgeniy Polyakov <johnpol@2ka.mipt.ru> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2007-10-26 07:31:14 -06:00
obj-$(CONFIG_CRYPTO_DEV_HIFN_795X) += hifn_795x.o
crypto: mv_cesa - Add support for Orion5X crypto engine This adds support for Marvell's Cryptographic Engines and Security Accelerator (CESA) which can be found on a few SoC. Tested with dm-crypt. Acked-by: Nicolas Pitre <nico@marvell.com> Signed-off-by: Sebastian Andrzej Siewior <sebastian@breakpoint.cc> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2009-08-09 20:50:03 -06:00
obj-$(CONFIG_CRYPTO_DEV_MV_CESA) += mv_cesa.o
crypto: talitos - Freescale integrated security engine (SEC) driver Add support for the SEC available on a wide range of PowerQUICC devices, e.g. MPC8349E, MPC8548E. This initial version supports authenc(hmac(sha1),cbc(aes)) for use with IPsec. Signed-off-by: Kim Phillips <kim.phillips@freescale.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2008-06-23 05:50:15 -06:00
obj-$(CONFIG_CRYPTO_DEV_TALITOS) += talitos.o
crypto: caam - Add support for the Freescale SEC4/CAAM The SEC4 supercedes the SEC2.x/3.x as Freescale's Integrated Security Engine. Its programming model is incompatible with all prior versions of the SEC (talitos). The SEC4 is also known as the Cryptographic Accelerator and Assurance Module (CAAM); this driver is named caam. This initial submission does not include support for Data Path mode operation - AEAD descriptors are submitted via the job ring interface, while the Queue Interface (QI) is enabled for use by others. Only AEAD algorithms are implemented at this time, for use with IPsec. Many thanks to the Freescale STC team for their contributions to this driver. Signed-off-by: Steve Cornelius <sec@pobox.com> Signed-off-by: Kim Phillips <kim.phillips@freescale.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2011-03-13 01:54:26 -07:00
obj-$(CONFIG_CRYPTO_DEV_FSL_CAAM) += caam/
crypto: ixp4xx - Hardware crypto support for IXP4xx CPUs Add support for the hardware crypto engine provided by the NPE C of the Intel IXP4xx networking processor series. Supported ciphers: des, des3, aes and a combination of them with md5 and sha1 hmac Signed-off-by: Christian Hohnstaedt <chohnstaedt@innominate.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2008-06-25 00:38:47 -06:00
obj-$(CONFIG_CRYPTO_DEV_IXP4XX) += ixp4xx_crypto.o
crypto: amcc - Add crypt4xx driver This patch adds support for AMCC ppc4xx security device driver. This is the initial release that includes the driver framework with AES and SHA1 algorithms support. The remaining algorithms will be released in the near future. Signed-off-by: James Hsiao <jhsiao@amcc.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2009-02-04 22:18:13 -07:00
obj-$(CONFIG_CRYPTO_DEV_PPC4XX) += amcc/
crypto: omap - sha1 & md5 driver Earlier kernel contained omap sha1 and md5 driver, which was not maintained, was not ported to new crypto APIs and removed from the source tree. - implements async crypto API using dma and cpu. - supports multiple sham instances if available - hmac - concurrent requests Signed-off-by: Dmitry Kasatkin <dmitry.kasatkin@nokia.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2010-05-02 21:10:59 -06:00
obj-$(CONFIG_CRYPTO_DEV_OMAP_SHAM) += omap-sham.o
crypto: omap-aes - OMAP2/3 AES hw accelerator driver Signed-off-by: Dmitry Kasatkin <dmitry.kasatkin@nokia.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2010-09-03 05:16:02 -06:00
obj-$(CONFIG_CRYPTO_DEV_OMAP_AES) += omap-aes.o
crypto: picoxcell - add support for the picoxcell crypto engines Picochip picoXcell devices have two crypto engines, one targeted at IPSEC offload and the other at WCDMA layer 2 ciphering. Signed-off-by: Jamie Iles <jamie@jamieiles.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2011-02-20 22:43:21 -07:00
obj-$(CONFIG_CRYPTO_DEV_PICOXCELL) += picoxcell_crypto.o
crypto: sahara - Add driver for SAHARA2 accelerator. SAHARA2 HW module is included in the i.MX27 SoC from Freescale. It is capable of performing cipher algorithms such as AES, 3DES..., hashing and RNG too. This driver provides support for AES-CBC and AES-ECB by now. Reviewed-by: Arnd Bergmann <arnd@arndb.de> Signed-off-by: Javier Martin <javier.martin@vista-silicon.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2013-03-01 04:37:53 -07:00
obj-$(CONFIG_CRYPTO_DEV_SAHARA) += sahara.o
crypto: dcp - Added support for Freescale's DCP co-processor This patch enables the DCP crypto functionality on imx28. Currently, only aes-128-cbc is supported. Moreover, the dcpboot misc-device, which is used by Freescale's SDK tools and uses a non-software-readable OTP-key, is added. Changes of v2: - ring buffer for hardware-descriptors - use of ablkcipher walk - OTP key encryption/decryption via misc-device (compatible to Freescale-SDK) - overall cleanup The DCP is also capable of sha1/sha256 but I won't be able to add that anytime soon. Tested with built-in runtime-self-test, tcrypt and openssl via cryptodev 1.6 on imx28-evk and a custom built imx28-board. Signed-off-by: Tobias Rauter <tobias.rauter@gmail.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2013-05-19 13:59:38 -06:00
obj-$(CONFIG_CRYPTO_DEV_DCP) += dcp.o
crypto: s5p-sss - add S5PV210 advanced crypto engine support This change adds support for AES encrypting and decrypting using advanced crypto engine found on Samsung S5PV210 and S5PC110 SoCs. Signed-off-by: Vladimir Zapolskiy <vzapolskiy@gmail.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2011-04-08 06:40:51 -06:00
obj-$(CONFIG_CRYPTO_DEV_S5P) += s5p-sss.o
crypto: driver for Tegra AES hardware driver supports ecb/cbc/ofb/ansi_x9.31rng modes, 128, 192 and 256-bit key sizes Signed-off-by: Varun Wadekar <vwadekar@nvidia.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2012-01-12 22:38:37 -07:00
obj-$(CONFIG_CRYPTO_DEV_TEGRA_AES) += tegra-aes.o
crypto: bfin_crc - CRC hardware driver for BF60x family processors. The CRC peripheral is a hardware block used to compute the CRC of the block of data. This is based on a CRC32 engine which computes the CRC value of 32b data words presented to it. For data words of < 32b in size, this driver pack 0 automatically into 32b data units. This driver implements the async hash crypto framework API. Signed-off-by: Sonic Zhang <sonic.zhang@analog.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2012-06-03 22:24:47 -06:00
obj-$(CONFIG_CRYPTO_DEV_UX500) += ux500/
obj-$(CONFIG_CRYPTO_DEV_BFIN_CRC) += bfin_crc.o
crypto: nx - move nx build to driver/crypto Makefile When the nx driver was pulled, the Makefile that actually builds it is arch/powerpc/Makefile. This is unnatural. This patch moves the line that builds the nx driver from arch/powerpc/Makefile to drivers/crypto/Makefile where it belongs. Signed-off-by: Seth Jennings <sjenning@linux.vnet.ibm.com> Acked-by: Kent Yoder <key@linux.vnet.ibm.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2012-06-13 12:22:42 -06:00
obj-$(CONFIG_CRYPTO_DEV_NX) += nx/
crypto: atmel - add Atmel AES driver Signed-off-by: Nicolas Royer <nicolas@eukrea.com> Acked-by: Nicolas Ferre <nicolas.ferre@atmel.com> Acked-by: Eric Bénard <eric@eukrea.com> Tested-by: Eric Bénard <eric@eukrea.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2012-07-01 11:19:44 -06:00
obj-$(CONFIG_CRYPTO_DEV_ATMEL_AES) += atmel-aes.o
crypto: atmel - add Atmel DES/TDES driver Signed-off-by: Nicolas Royer <nicolas@eukrea.com> Acked-by: Nicolas Ferre <nicolas.ferre@atmel.com> Acked-by: Eric Bénard <eric@eukrea.com> Tested-by: Eric Bénard <eric@eukrea.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2012-07-01 11:19:45 -06:00
obj-$(CONFIG_CRYPTO_DEV_ATMEL_TDES) += atmel-tdes.o
crypto: atmel - add Atmel SHA1/SHA256 driver Signed-off-by: Nicolas Royer <nicolas@eukrea.com> Acked-by: Nicolas Ferre <nicolas.ferre@atmel.com> Acked-by: Eric Bénard <eric@eukrea.com> Tested-by: Eric Bénard <eric@eukrea.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
2012-07-01 11:19:46 -06:00
obj-$(CONFIG_CRYPTO_DEV_ATMEL_SHA) += atmel-sha.o
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