2005-04-16 16:20:36 -06:00
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/*
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* arch/ppc64/kernel/cputable.c
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*
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* Copyright (C) 2001 Ben. Herrenschmidt (benh@kernel.crashing.org)
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*
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* Modifications for ppc64:
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* Copyright (C) 2003 Dave Engebretsen <engebret@us.ibm.com>
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2005-08-02 22:40:16 -06:00
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*
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2005-04-16 16:20:36 -06:00
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version
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* 2 of the License, or (at your option) any later version.
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*/
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#include <linux/config.h>
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#include <linux/string.h>
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#include <linux/sched.h>
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#include <linux/threads.h>
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#include <linux/init.h>
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#include <linux/module.h>
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#include <asm/cputable.h>
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struct cpu_spec* cur_cpu_spec = NULL;
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EXPORT_SYMBOL(cur_cpu_spec);
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/* NOTE:
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* Unlike ppc32, ppc64 will only call this once for the boot CPU, it's
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* the responsibility of the appropriate CPU save/restore functions to
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* eventually copy these settings over. Those save/restore aren't yet
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* part of the cputable though. That has to be fixed for both ppc32
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* and ppc64
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*/
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extern void __setup_cpu_power3(unsigned long offset, struct cpu_spec* spec);
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extern void __setup_cpu_power4(unsigned long offset, struct cpu_spec* spec);
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extern void __setup_cpu_ppc970(unsigned long offset, struct cpu_spec* spec);
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2005-06-22 17:43:37 -06:00
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extern void __setup_cpu_be(unsigned long offset, struct cpu_spec* spec);
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2005-04-16 16:20:36 -06:00
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/* We only set the altivec features if the kernel was compiled with altivec
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* support
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*/
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#ifdef CONFIG_ALTIVEC
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#define CPU_FTR_ALTIVEC_COMP CPU_FTR_ALTIVEC
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#define PPC_FEATURE_HAS_ALTIVEC_COMP PPC_FEATURE_HAS_ALTIVEC
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#else
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#define CPU_FTR_ALTIVEC_COMP 0
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#define PPC_FEATURE_HAS_ALTIVEC_COMP 0
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#endif
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struct cpu_spec cpu_specs[] = {
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2005-07-07 18:56:11 -06:00
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{ /* Power3 */
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.pvr_mask = 0xffff0000,
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.pvr_value = 0x00400000,
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.cpu_name = "POWER3 (630)",
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.cpu_features = CPU_FTR_SPLIT_ID_CACHE |
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2005-09-05 22:50:48 -06:00
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CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE | CPU_FTR_IABR,
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2005-07-07 18:56:11 -06:00
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.cpu_user_features = COMMON_USER_PPC64,
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.icache_bsize = 128,
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.dcache_bsize = 128,
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2005-09-05 22:47:49 -06:00
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.num_pmcs = 8,
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2005-07-07 18:56:11 -06:00
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.cpu_setup = __setup_cpu_power3,
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},
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{ /* Power3+ */
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.pvr_mask = 0xffff0000,
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.pvr_value = 0x00410000,
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.cpu_name = "POWER3 (630+)",
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.cpu_features = CPU_FTR_SPLIT_ID_CACHE |
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2005-09-05 22:50:48 -06:00
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CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE | CPU_FTR_IABR,
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2005-07-07 18:56:11 -06:00
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.cpu_user_features = COMMON_USER_PPC64,
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.icache_bsize = 128,
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.dcache_bsize = 128,
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2005-09-05 22:47:49 -06:00
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.num_pmcs = 8,
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2005-07-07 18:56:11 -06:00
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.cpu_setup = __setup_cpu_power3,
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},
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{ /* Northstar */
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.pvr_mask = 0xffff0000,
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.pvr_value = 0x00330000,
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.cpu_name = "RS64-II (northstar)",
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.cpu_features = CPU_FTR_SPLIT_ID_CACHE |
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CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE | CPU_FTR_IABR |
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2005-09-05 22:50:48 -06:00
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CPU_FTR_MMCRA | CPU_FTR_CTRL,
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2005-07-07 18:56:11 -06:00
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.cpu_user_features = COMMON_USER_PPC64,
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.icache_bsize = 128,
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.dcache_bsize = 128,
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2005-09-05 22:47:49 -06:00
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.num_pmcs = 8,
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2005-07-07 18:56:11 -06:00
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.cpu_setup = __setup_cpu_power3,
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},
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{ /* Pulsar */
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.pvr_mask = 0xffff0000,
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.pvr_value = 0x00340000,
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.cpu_name = "RS64-III (pulsar)",
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.cpu_features = CPU_FTR_SPLIT_ID_CACHE |
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CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE | CPU_FTR_IABR |
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2005-09-05 22:50:48 -06:00
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CPU_FTR_MMCRA | CPU_FTR_CTRL,
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2005-07-07 18:56:11 -06:00
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.cpu_user_features = COMMON_USER_PPC64,
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.icache_bsize = 128,
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.dcache_bsize = 128,
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2005-09-05 22:47:49 -06:00
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.num_pmcs = 8,
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2005-07-07 18:56:11 -06:00
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.cpu_setup = __setup_cpu_power3,
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},
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{ /* I-star */
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.pvr_mask = 0xffff0000,
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.pvr_value = 0x00360000,
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.cpu_name = "RS64-III (icestar)",
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.cpu_features = CPU_FTR_SPLIT_ID_CACHE |
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CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE | CPU_FTR_IABR |
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2005-09-05 22:50:48 -06:00
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CPU_FTR_MMCRA | CPU_FTR_CTRL,
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2005-07-07 18:56:11 -06:00
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.cpu_user_features = COMMON_USER_PPC64,
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.icache_bsize = 128,
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.dcache_bsize = 128,
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2005-09-05 22:47:49 -06:00
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.num_pmcs = 8,
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2005-07-07 18:56:11 -06:00
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.cpu_setup = __setup_cpu_power3,
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},
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{ /* S-star */
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.pvr_mask = 0xffff0000,
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.pvr_value = 0x00370000,
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.cpu_name = "RS64-IV (sstar)",
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.cpu_features = CPU_FTR_SPLIT_ID_CACHE |
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CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE | CPU_FTR_IABR |
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2005-09-05 22:50:48 -06:00
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CPU_FTR_MMCRA | CPU_FTR_CTRL,
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2005-07-07 18:56:11 -06:00
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.cpu_user_features = COMMON_USER_PPC64,
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.icache_bsize = 128,
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.dcache_bsize = 128,
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2005-09-05 22:47:49 -06:00
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.num_pmcs = 8,
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2005-07-07 18:56:11 -06:00
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.cpu_setup = __setup_cpu_power3,
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},
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{ /* Power4 */
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.pvr_mask = 0xffff0000,
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.pvr_value = 0x00350000,
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.cpu_name = "POWER4 (gp)",
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.cpu_features = CPU_FTR_SPLIT_ID_CACHE |
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CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE |
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2005-09-05 22:50:48 -06:00
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CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_MMCRA,
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2005-07-07 18:56:11 -06:00
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.cpu_user_features = COMMON_USER_PPC64,
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.icache_bsize = 128,
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.dcache_bsize = 128,
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2005-09-05 22:47:49 -06:00
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.num_pmcs = 8,
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2005-07-07 18:56:11 -06:00
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.cpu_setup = __setup_cpu_power4,
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},
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{ /* Power4+ */
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.pvr_mask = 0xffff0000,
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.pvr_value = 0x00380000,
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.cpu_name = "POWER4+ (gq)",
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.cpu_features = CPU_FTR_SPLIT_ID_CACHE |
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CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE |
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2005-09-05 22:50:48 -06:00
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CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_MMCRA,
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2005-07-07 18:56:11 -06:00
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.cpu_user_features = COMMON_USER_PPC64,
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.icache_bsize = 128,
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.dcache_bsize = 128,
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2005-09-05 22:47:49 -06:00
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.num_pmcs = 8,
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2005-07-07 18:56:11 -06:00
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.cpu_setup = __setup_cpu_power4,
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},
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{ /* PPC970 */
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.pvr_mask = 0xffff0000,
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.pvr_value = 0x00390000,
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.cpu_name = "PPC970",
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.cpu_features = CPU_FTR_SPLIT_ID_CACHE |
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CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE |
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CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_ALTIVEC_COMP |
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2005-09-05 22:50:48 -06:00
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CPU_FTR_CAN_NAP | CPU_FTR_MMCRA,
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2005-07-07 18:56:11 -06:00
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.cpu_user_features = COMMON_USER_PPC64 |
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PPC_FEATURE_HAS_ALTIVEC_COMP,
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.icache_bsize = 128,
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.dcache_bsize = 128,
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2005-09-05 22:47:49 -06:00
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.num_pmcs = 8,
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2005-07-07 18:56:11 -06:00
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.cpu_setup = __setup_cpu_ppc970,
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},
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{ /* PPC970FX */
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.pvr_mask = 0xffff0000,
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.pvr_value = 0x003c0000,
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.cpu_name = "PPC970FX",
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.cpu_features = CPU_FTR_SPLIT_ID_CACHE |
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CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE |
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CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_ALTIVEC_COMP |
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2005-09-05 22:50:48 -06:00
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CPU_FTR_CAN_NAP | CPU_FTR_MMCRA,
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2005-07-07 18:56:11 -06:00
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.cpu_user_features = COMMON_USER_PPC64 |
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PPC_FEATURE_HAS_ALTIVEC_COMP,
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.icache_bsize = 128,
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.dcache_bsize = 128,
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2005-09-05 22:47:49 -06:00
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.num_pmcs = 8,
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2005-07-07 18:56:11 -06:00
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.cpu_setup = __setup_cpu_ppc970,
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},
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2005-07-13 02:11:44 -06:00
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{ /* PPC970MP */
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.pvr_mask = 0xffff0000,
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.pvr_value = 0x00440000,
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.cpu_name = "PPC970MP",
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.cpu_features = CPU_FTR_SPLIT_ID_CACHE |
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CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE |
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CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_ALTIVEC_COMP |
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2005-09-05 22:50:48 -06:00
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CPU_FTR_CAN_NAP | CPU_FTR_MMCRA,
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2005-07-13 02:11:44 -06:00
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.cpu_user_features = COMMON_USER_PPC64 |
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PPC_FEATURE_HAS_ALTIVEC_COMP,
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.icache_bsize = 128,
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.dcache_bsize = 128,
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.cpu_setup = __setup_cpu_ppc970,
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},
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2005-07-07 18:56:11 -06:00
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{ /* Power5 */
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.pvr_mask = 0xffff0000,
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.pvr_value = 0x003a0000,
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.cpu_name = "POWER5 (gr)",
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.cpu_features = CPU_FTR_SPLIT_ID_CACHE |
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CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE |
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CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_MMCRA | CPU_FTR_SMT |
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CPU_FTR_COHERENT_ICACHE | CPU_FTR_LOCKLESS_TLBIE |
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CPU_FTR_MMCRA_SIHV,
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.cpu_user_features = COMMON_USER_PPC64,
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.icache_bsize = 128,
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.dcache_bsize = 128,
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2005-09-05 22:47:49 -06:00
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.num_pmcs = 6,
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2005-07-07 18:56:11 -06:00
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.cpu_setup = __setup_cpu_power4,
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},
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{ /* Power5 */
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.pvr_mask = 0xffff0000,
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.pvr_value = 0x003b0000,
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.cpu_name = "POWER5 (gs)",
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.cpu_features = CPU_FTR_SPLIT_ID_CACHE |
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CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE |
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CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_MMCRA | CPU_FTR_SMT |
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CPU_FTR_COHERENT_ICACHE | CPU_FTR_LOCKLESS_TLBIE |
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CPU_FTR_MMCRA_SIHV,
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.cpu_user_features = COMMON_USER_PPC64,
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.icache_bsize = 128,
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.dcache_bsize = 128,
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2005-09-05 22:47:49 -06:00
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.num_pmcs = 6,
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2005-07-07 18:56:11 -06:00
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.cpu_setup = __setup_cpu_power4,
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},
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{ /* BE DD1.x */
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.pvr_mask = 0xffff0000,
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.pvr_value = 0x00700000,
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.cpu_name = "Broadband Engine",
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.cpu_features = CPU_FTR_SPLIT_ID_CACHE |
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CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE |
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CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_ALTIVEC_COMP |
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CPU_FTR_SMT,
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.cpu_user_features = COMMON_USER_PPC64 |
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PPC_FEATURE_HAS_ALTIVEC_COMP,
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.icache_bsize = 128,
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.dcache_bsize = 128,
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.cpu_setup = __setup_cpu_be,
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},
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{ /* default match */
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.pvr_mask = 0x00000000,
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.pvr_value = 0x00000000,
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.cpu_name = "POWER4 (compatible)",
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.cpu_features = CPU_FTR_SPLIT_ID_CACHE |
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CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE |
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CPU_FTR_PPCAS_ARCH_V2,
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.cpu_user_features = COMMON_USER_PPC64,
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.icache_bsize = 128,
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.dcache_bsize = 128,
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2005-09-05 22:47:49 -06:00
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.num_pmcs = 6,
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2005-07-07 18:56:11 -06:00
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.cpu_setup = __setup_cpu_power4,
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}
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2005-04-16 16:20:36 -06:00
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};
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