2005-04-16 16:20:36 -06:00
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/*
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* linux/arch/alpha/kernel/pci.c
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*
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* Extruded from code written by
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* Dave Rusling (david.rusling@reo.mts.dec.com)
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* David Mosberger (davidm@cs.arizona.edu)
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*/
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/* 2.3.x PCI/resources, 1999 Andrea Arcangeli <andrea@suse.de> */
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/*
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* Nov 2000, Ivan Kokshaysky <ink@jurassic.park.msu.ru>
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* PCI-PCI bridges cleanup
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*/
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#include <linux/string.h>
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#include <linux/pci.h>
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#include <linux/init.h>
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#include <linux/ioport.h>
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#include <linux/kernel.h>
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#include <linux/bootmem.h>
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#include <linux/module.h>
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#include <linux/cache.h>
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#include <linux/slab.h>
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#include <asm/machvec.h>
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#include "proto.h"
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#include "pci_impl.h"
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/*
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* Some string constants used by the various core logics.
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*/
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const char *const pci_io_names[] = {
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"PCI IO bus 0", "PCI IO bus 1", "PCI IO bus 2", "PCI IO bus 3",
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"PCI IO bus 4", "PCI IO bus 5", "PCI IO bus 6", "PCI IO bus 7"
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};
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const char *const pci_mem_names[] = {
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"PCI mem bus 0", "PCI mem bus 1", "PCI mem bus 2", "PCI mem bus 3",
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"PCI mem bus 4", "PCI mem bus 5", "PCI mem bus 6", "PCI mem bus 7"
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};
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const char pci_hae0_name[] = "HAE0";
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/* Indicate whether we respect the PCI setup left by console. */
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/*
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* Make this long-lived so that we know when shutting down
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* whether we probed only or not.
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*/
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int pci_probe_only;
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/*
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* The PCI controller list.
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*/
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struct pci_controller *hose_head, **hose_tail = &hose_head;
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struct pci_controller *pci_isa_hose;
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/*
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* Quirks.
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*/
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static void __init
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quirk_isa_bridge(struct pci_dev *dev)
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{
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dev->class = PCI_CLASS_BRIDGE_ISA << 8;
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}
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DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82378, quirk_isa_bridge);
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static void __init
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quirk_cypress(struct pci_dev *dev)
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{
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2008-06-20 17:28:54 -06:00
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/* The Notorious Cy82C693 chip. */
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/* The generic legacy mode IDE fixup in drivers/pci/probe.c
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doesn't work correctly with the Cypress IDE controller as
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it has non-standard register layout. Fix that. */
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if (dev->class >> 8 == PCI_CLASS_STORAGE_IDE) {
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dev->resource[2].start = dev->resource[3].start = 0;
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dev->resource[2].end = dev->resource[3].end = 0;
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dev->resource[2].flags = dev->resource[3].flags = 0;
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if (PCI_FUNC(dev->devfn) == 2) {
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dev->resource[0].start = 0x170;
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dev->resource[0].end = 0x177;
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dev->resource[1].start = 0x376;
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dev->resource[1].end = 0x376;
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}
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}
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2005-04-16 16:20:36 -06:00
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/* The Cypress bridge responds on the PCI bus in the address range
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0xffff0000-0xffffffff (conventional x86 BIOS ROM). There is no
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way to turn this off. The bridge also supports several extended
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BIOS ranges (disabled after power-up), and some consoles do turn
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them on. So if we use a large direct-map window, or a large SG
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window, we must avoid the entire 0xfff00000-0xffffffff region. */
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2008-04-24 06:51:55 -06:00
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if (dev->class >> 8 == PCI_CLASS_BRIDGE_ISA) {
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2005-04-16 16:20:36 -06:00
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if (__direct_map_base + __direct_map_size >= 0xfff00000UL)
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__direct_map_size = 0xfff00000UL - __direct_map_base;
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else {
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struct pci_controller *hose = dev->sysdata;
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struct pci_iommu_arena *pci = hose->sg_pci;
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if (pci && pci->dma_base + pci->size >= 0xfff00000UL)
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pci->size = 0xfff00000UL - pci->dma_base;
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}
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}
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}
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DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_CONTAQ, PCI_DEVICE_ID_CONTAQ_82C693, quirk_cypress);
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/* Called for each device after PCI setup is done. */
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static void __init
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pcibios_fixup_final(struct pci_dev *dev)
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{
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unsigned int class = dev->class >> 8;
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if (class == PCI_CLASS_BRIDGE_ISA || class == PCI_CLASS_BRIDGE_EISA) {
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dev->dma_mask = MAX_ISA_DMA_ADDRESS - 1;
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isa_bridge = dev;
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}
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}
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DECLARE_PCI_FIXUP_FINAL(PCI_ANY_ID, PCI_ANY_ID, pcibios_fixup_final);
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/* Just declaring that the power-of-ten prefixes are actually the
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power-of-two ones doesn't make it true :) */
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#define KB 1024
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#define MB (1024*KB)
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#define GB (1024*MB)
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void
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pcibios_align_resource(void *data, struct resource *res,
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2006-06-12 18:06:02 -06:00
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resource_size_t size, resource_size_t align)
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2005-04-16 16:20:36 -06:00
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{
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struct pci_dev *dev = data;
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struct pci_controller *hose = dev->sysdata;
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unsigned long alignto;
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2006-06-12 18:06:02 -06:00
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resource_size_t start = res->start;
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2005-04-16 16:20:36 -06:00
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if (res->flags & IORESOURCE_IO) {
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/* Make sure we start at our min on all hoses */
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if (start - hose->io_space->start < PCIBIOS_MIN_IO)
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start = PCIBIOS_MIN_IO + hose->io_space->start;
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/*
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* Put everything into 0x00-0xff region modulo 0x400
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*/
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if (start & 0x300)
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start = (start + 0x3ff) & ~0x3ff;
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}
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else if (res->flags & IORESOURCE_MEM) {
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/* Make sure we start at our min on all hoses */
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if (start - hose->mem_space->start < PCIBIOS_MIN_MEM)
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start = PCIBIOS_MIN_MEM + hose->mem_space->start;
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/*
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* The following holds at least for the Low Cost
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* Alpha implementation of the PCI interface:
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*
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* In sparse memory address space, the first
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* octant (16MB) of every 128MB segment is
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* aliased to the very first 16 MB of the
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* address space (i.e., it aliases the ISA
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* memory address space). Thus, we try to
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* avoid allocating PCI devices in that range.
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* Can be allocated in 2nd-7th octant only.
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* Devices that need more than 112MB of
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* address space must be accessed through
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* dense memory space only!
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*/
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/* Align to multiple of size of minimum base. */
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alignto = max(0x1000UL, align);
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start = ALIGN(start, alignto);
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if (hose->sparse_mem_base && size <= 7 * 16*MB) {
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if (((start / (16*MB)) & 0x7) == 0) {
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start &= ~(128*MB - 1);
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start += 16*MB;
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start = ALIGN(start, alignto);
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}
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if (start/(128*MB) != (start + size - 1)/(128*MB)) {
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start &= ~(128*MB - 1);
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start += (128 + 16)*MB;
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start = ALIGN(start, alignto);
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}
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}
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}
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res->start = start;
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}
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#undef KB
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#undef MB
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#undef GB
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static int __init
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pcibios_init(void)
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{
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if (alpha_mv.init_pci)
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alpha_mv.init_pci();
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return 0;
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}
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subsys_initcall(pcibios_init);
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2007-07-26 10:34:19 -06:00
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char * __devinit
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2005-04-16 16:20:36 -06:00
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pcibios_setup(char *str)
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{
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return str;
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}
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#ifdef ALPHA_RESTORE_SRM_SETUP
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static struct pdev_srm_saved_conf *srm_saved_configs;
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2007-07-26 10:34:19 -06:00
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void __devinit
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2005-04-16 16:20:36 -06:00
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pdev_save_srm_config(struct pci_dev *dev)
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{
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struct pdev_srm_saved_conf *tmp;
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static int printed = 0;
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if (!alpha_using_srm || pci_probe_only)
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return;
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if (!printed) {
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printk(KERN_INFO "pci: enabling save/restore of SRM state\n");
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printed = 1;
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}
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tmp = kmalloc(sizeof(*tmp), GFP_KERNEL);
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if (!tmp) {
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2008-04-28 03:13:46 -06:00
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printk(KERN_ERR "%s: kmalloc() failed!\n", __func__);
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2005-04-16 16:20:36 -06:00
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return;
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}
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tmp->next = srm_saved_configs;
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tmp->dev = dev;
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pci_save_state(dev);
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srm_saved_configs = tmp;
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}
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void
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pci_restore_srm_config(void)
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{
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struct pdev_srm_saved_conf *tmp;
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/* No need to restore if probed only. */
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if (pci_probe_only)
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return;
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/* Restore SRM config. */
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for (tmp = srm_saved_configs; tmp; tmp = tmp->next) {
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pci_restore_state(tmp->dev);
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}
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}
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#endif
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2007-07-26 10:34:19 -06:00
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void __devinit
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2005-04-16 16:20:36 -06:00
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pcibios_fixup_resource(struct resource *res, struct resource *root)
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{
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res->start += root->start;
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res->end += root->start;
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}
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2007-07-26 10:34:19 -06:00
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void __devinit
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2005-04-16 16:20:36 -06:00
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pcibios_fixup_device_resources(struct pci_dev *dev, struct pci_bus *bus)
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{
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/* Update device resources. */
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struct pci_controller *hose = (struct pci_controller *)bus->sysdata;
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int i;
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for (i = 0; i < PCI_NUM_RESOURCES; i++) {
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if (!dev->resource[i].start)
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continue;
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if (dev->resource[i].flags & IORESOURCE_IO)
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pcibios_fixup_resource(&dev->resource[i],
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hose->io_space);
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else if (dev->resource[i].flags & IORESOURCE_MEM)
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pcibios_fixup_resource(&dev->resource[i],
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hose->mem_space);
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}
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}
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2007-07-26 10:34:19 -06:00
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void __devinit
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2005-04-16 16:20:36 -06:00
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pcibios_fixup_bus(struct pci_bus *bus)
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{
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/* Propagate hose info into the subordinate devices. */
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struct pci_controller *hose = bus->sysdata;
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struct pci_dev *dev = bus->self;
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if (!dev) {
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/* Root bus. */
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u32 pci_mem_end;
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u32 sg_base = hose->sg_pci ? hose->sg_pci->dma_base : ~0;
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unsigned long end;
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bus->resource[0] = hose->io_space;
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bus->resource[1] = hose->mem_space;
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/* Adjust hose mem_space limit to prevent PCI allocations
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in the iommu windows. */
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pci_mem_end = min((u32)__direct_map_base, sg_base) - 1;
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end = hose->mem_space->start + pci_mem_end;
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if (hose->mem_space->end > end)
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hose->mem_space->end = end;
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} else if (pci_probe_only &&
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(dev->class >> 8) == PCI_CLASS_BRIDGE_PCI) {
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pci_read_bridge_bases(bus);
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pcibios_fixup_device_resources(dev, bus);
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}
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list_for_each_entry(dev, &bus->devices, bus_list) {
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pdev_save_srm_config(dev);
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if ((dev->class >> 8) != PCI_CLASS_BRIDGE_PCI)
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pcibios_fixup_device_resources(dev, bus);
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}
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}
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void __init
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pcibios_update_irq(struct pci_dev *dev, int irq)
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{
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pci_write_config_byte(dev, PCI_INTERRUPT_LINE, irq);
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}
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2008-11-22 10:37:04 -07:00
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void
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2005-04-16 16:20:36 -06:00
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pcibios_resource_to_bus(struct pci_dev *dev, struct pci_bus_region *region,
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struct resource *res)
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{
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struct pci_controller *hose = (struct pci_controller *)dev->sysdata;
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unsigned long offset = 0;
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if (res->flags & IORESOURCE_IO)
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offset = hose->io_space->start;
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else if (res->flags & IORESOURCE_MEM)
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offset = hose->mem_space->start;
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region->start = res->start - offset;
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region->end = res->end - offset;
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}
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2005-08-04 19:06:21 -06:00
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void pcibios_bus_to_resource(struct pci_dev *dev, struct resource *res,
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struct pci_bus_region *region)
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{
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struct pci_controller *hose = (struct pci_controller *)dev->sysdata;
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unsigned long offset = 0;
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if (res->flags & IORESOURCE_IO)
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offset = hose->io_space->start;
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else if (res->flags & IORESOURCE_MEM)
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offset = hose->mem_space->start;
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res->start = region->start + offset;
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res->end = region->end + offset;
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}
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2005-04-16 16:20:36 -06:00
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#ifdef CONFIG_HOTPLUG
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EXPORT_SYMBOL(pcibios_resource_to_bus);
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2005-08-04 19:06:21 -06:00
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EXPORT_SYMBOL(pcibios_bus_to_resource);
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2005-04-16 16:20:36 -06:00
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#endif
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int
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pcibios_enable_device(struct pci_dev *dev, int mask)
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{
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2008-03-04 11:56:48 -07:00
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return pci_enable_resources(dev, mask);
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2005-04-16 16:20:36 -06:00
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}
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/*
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* If we set up a device for bus mastering, we need to check the latency
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* timer as certain firmware forgets to set it properly, as seen
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* on SX164 and LX164 with SRM.
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*/
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void
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pcibios_set_master(struct pci_dev *dev)
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{
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u8 lat;
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pci_read_config_byte(dev, PCI_LATENCY_TIMER, &lat);
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if (lat >= 16) return;
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printk("PCI: Setting latency timer of device %s to 64\n",
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pci_name(dev));
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pci_write_config_byte(dev, PCI_LATENCY_TIMER, 64);
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}
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2008-04-24 06:51:55 -06:00
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void __init
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2005-04-16 16:20:36 -06:00
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pcibios_claim_one_bus(struct pci_bus *b)
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{
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struct pci_dev *dev;
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struct pci_bus *child_bus;
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list_for_each_entry(dev, &b->devices, bus_list) {
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int i;
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for (i = 0; i < PCI_NUM_RESOURCES; i++) {
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struct resource *r = &dev->resource[i];
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if (r->parent || !r->start || !r->flags)
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continue;
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2008-04-24 06:51:55 -06:00
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if (pci_probe_only || (r->flags & IORESOURCE_PCI_FIXED))
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pci_claim_resource(dev, i);
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2005-04-16 16:20:36 -06:00
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}
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}
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list_for_each_entry(child_bus, &b->children, node)
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pcibios_claim_one_bus(child_bus);
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}
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static void __init
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pcibios_claim_console_setup(void)
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{
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struct pci_bus *b;
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list_for_each_entry(b, &pci_root_buses, node)
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pcibios_claim_one_bus(b);
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}
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void __init
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common_init_pci(void)
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{
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struct pci_controller *hose;
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struct pci_bus *bus;
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int next_busno;
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int need_domain_info = 0;
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/* Scan all of the recorded PCI controllers. */
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for (next_busno = 0, hose = hose_head; hose; hose = hose->next) {
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bus = pci_scan_bus(next_busno, alpha_mv.pci_ops, hose);
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hose->bus = bus;
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hose->need_domain_info = need_domain_info;
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next_busno = bus->subordinate + 1;
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/* Don't allow 8-bit bus number overflow inside the hose -
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reserve some space for bridges. */
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if (next_busno > 224) {
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next_busno = 0;
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need_domain_info = 1;
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}
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}
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2008-04-24 06:51:55 -06:00
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pcibios_claim_console_setup();
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2005-04-16 16:20:36 -06:00
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pci_assign_unassigned_resources();
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pci_fixup_irqs(alpha_mv.pci_swizzle, alpha_mv.pci_map_irq);
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}
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struct pci_controller * __init
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alloc_pci_controller(void)
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{
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struct pci_controller *hose;
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hose = alloc_bootmem(sizeof(*hose));
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*hose_tail = hose;
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hose_tail = &hose->next;
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return hose;
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}
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struct resource * __init
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alloc_resource(void)
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{
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struct resource *res;
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res = alloc_bootmem(sizeof(*res));
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return res;
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}
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/* Provide information on locations of various I/O regions in physical
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memory. Do this on a per-card basis so that we choose the right hose. */
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asmlinkage long
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sys_pciconfig_iobase(long which, unsigned long bus, unsigned long dfn)
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{
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struct pci_controller *hose;
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struct pci_dev *dev;
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/* from hose or from bus.devfn */
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if (which & IOBASE_FROM_HOSE) {
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for(hose = hose_head; hose; hose = hose->next)
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if (hose->index == bus) break;
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if (!hose) return -ENODEV;
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} else {
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/* Special hook for ISA access. */
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if (bus == 0 && dfn == 0) {
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hose = pci_isa_hose;
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} else {
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2006-12-06 21:33:59 -07:00
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dev = pci_get_bus_and_slot(bus, dfn);
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2005-04-16 16:20:36 -06:00
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if (!dev)
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return -ENODEV;
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hose = dev->sysdata;
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2006-12-06 21:33:59 -07:00
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pci_dev_put(dev);
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2005-04-16 16:20:36 -06:00
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}
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}
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switch (which & ~IOBASE_FROM_HOSE) {
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case IOBASE_HOSE:
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return hose->index;
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case IOBASE_SPARSE_MEM:
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return hose->sparse_mem_base;
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case IOBASE_DENSE_MEM:
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return hose->dense_mem_base;
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case IOBASE_SPARSE_IO:
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return hose->sparse_io_base;
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case IOBASE_DENSE_IO:
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return hose->dense_io_base;
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case IOBASE_ROOT_BUS:
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return hose->bus->number;
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}
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return -EOPNOTSUPP;
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}
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/* Create an __iomem token from a PCI BAR. Copied from lib/iomap.c with
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no changes, since we don't want the other things in that object file. */
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void __iomem *pci_iomap(struct pci_dev *dev, int bar, unsigned long maxlen)
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{
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2008-04-29 01:59:11 -06:00
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resource_size_t start = pci_resource_start(dev, bar);
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resource_size_t len = pci_resource_len(dev, bar);
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2005-04-16 16:20:36 -06:00
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unsigned long flags = pci_resource_flags(dev, bar);
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if (!len || !start)
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return NULL;
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if (maxlen && len > maxlen)
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len = maxlen;
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if (flags & IORESOURCE_IO)
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return ioport_map(start, len);
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if (flags & IORESOURCE_MEM) {
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/* Not checking IORESOURCE_CACHEABLE because alpha does
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not distinguish between ioremap and ioremap_nocache. */
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return ioremap(start, len);
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}
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return NULL;
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}
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/* Destroy that token. Not copied from lib/iomap.c. */
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void pci_iounmap(struct pci_dev *dev, void __iomem * addr)
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{
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if (__is_mmio(addr))
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iounmap(addr);
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}
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EXPORT_SYMBOL(pci_iomap);
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EXPORT_SYMBOL(pci_iounmap);
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2007-01-06 13:48:41 -07:00
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/* FIXME: Some boxes have multiple ISA bridges! */
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struct pci_dev *isa_bridge;
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EXPORT_SYMBOL(isa_bridge);
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