2009-01-21 22:30:23 -07:00
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/* pcr.c: Generic sparc64 performance counter infrastructure.
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*
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* Copyright (C) 2009 David S. Miller (davem@davemloft.net)
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*/
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/init.h>
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#include <linux/irq.h>
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2010-10-14 00:01:34 -06:00
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#include <linux/irq_work.h>
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2010-04-07 05:41:33 -06:00
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#include <linux/ftrace.h>
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2009-09-10 06:59:24 -06:00
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2009-01-21 22:30:23 -07:00
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#include <asm/pil.h>
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#include <asm/pcr.h>
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2009-01-29 22:22:47 -07:00
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#include <asm/nmi.h>
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2009-01-21 22:30:23 -07:00
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/* This code is shared between various users of the performance
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* counters. Users will be oprofile, pseudo-NMI watchdog, and the
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perf: Do the big rename: Performance Counters -> Performance Events
Bye-bye Performance Counters, welcome Performance Events!
In the past few months the perfcounters subsystem has grown out its
initial role of counting hardware events, and has become (and is
becoming) a much broader generic event enumeration, reporting, logging,
monitoring, analysis facility.
Naming its core object 'perf_counter' and naming the subsystem
'perfcounters' has become more and more of a misnomer. With pending
code like hw-breakpoints support the 'counter' name is less and
less appropriate.
All in one, we've decided to rename the subsystem to 'performance
events' and to propagate this rename through all fields, variables
and API names. (in an ABI compatible fashion)
The word 'event' is also a bit shorter than 'counter' - which makes
it slightly more convenient to write/handle as well.
Thanks goes to Stephane Eranian who first observed this misnomer and
suggested a rename.
User-space tooling and ABI compatibility is not affected - this patch
should be function-invariant. (Also, defconfigs were not touched to
keep the size down.)
This patch has been generated via the following script:
FILES=$(find * -type f | grep -vE 'oprofile|[^K]config')
sed -i \
-e 's/PERF_EVENT_/PERF_RECORD_/g' \
-e 's/PERF_COUNTER/PERF_EVENT/g' \
-e 's/perf_counter/perf_event/g' \
-e 's/nb_counters/nb_events/g' \
-e 's/swcounter/swevent/g' \
-e 's/tpcounter_event/tp_event/g' \
$FILES
for N in $(find . -name perf_counter.[ch]); do
M=$(echo $N | sed 's/perf_counter/perf_event/g')
mv $N $M
done
FILES=$(find . -name perf_event.*)
sed -i \
-e 's/COUNTER_MASK/REG_MASK/g' \
-e 's/COUNTER/EVENT/g' \
-e 's/\<event\>/event_id/g' \
-e 's/counter/event/g' \
-e 's/Counter/Event/g' \
$FILES
... to keep it as correct as possible. This script can also be
used by anyone who has pending perfcounters patches - it converts
a Linux kernel tree over to the new naming. We tried to time this
change to the point in time where the amount of pending patches
is the smallest: the end of the merge window.
Namespace clashes were fixed up in a preparatory patch - and some
stylistic fallout will be fixed up in a subsequent patch.
( NOTE: 'counters' are still the proper terminology when we deal
with hardware registers - and these sed scripts are a bit
over-eager in renaming them. I've undone some of that, but
in case there's something left where 'counter' would be
better than 'event' we can undo that on an individual basis
instead of touching an otherwise nicely automated patch. )
Suggested-by: Stephane Eranian <eranian@google.com>
Acked-by: Peter Zijlstra <a.p.zijlstra@chello.nl>
Acked-by: Paul Mackerras <paulus@samba.org>
Reviewed-by: Arjan van de Ven <arjan@linux.intel.com>
Cc: Mike Galbraith <efault@gmx.de>
Cc: Arnaldo Carvalho de Melo <acme@redhat.com>
Cc: Frederic Weisbecker <fweisbec@gmail.com>
Cc: Steven Rostedt <rostedt@goodmis.org>
Cc: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Cc: David Howells <dhowells@redhat.com>
Cc: Kyle McMartin <kyle@mcmartin.ca>
Cc: Martin Schwidefsky <schwidefsky@de.ibm.com>
Cc: "David S. Miller" <davem@davemloft.net>
Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: "H. Peter Anvin" <hpa@zytor.com>
Cc: <linux-arch@vger.kernel.org>
LKML-Reference: <new-submission>
Signed-off-by: Ingo Molnar <mingo@elte.hu>
2009-09-21 04:02:48 -06:00
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* perf_event support layer.
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2009-01-21 22:30:23 -07:00
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*/
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2009-01-29 22:22:47 -07:00
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#define PCR_SUN4U_ENABLE (PCR_PIC_PRIV | PCR_STRACE | PCR_UTRACE)
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#define PCR_N2_ENABLE (PCR_PIC_PRIV | PCR_STRACE | PCR_UTRACE | \
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PCR_N2_TOE_OV1 | \
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(2 << PCR_N2_SL1_SHIFT) | \
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(0xff << PCR_N2_MASK1_SHIFT))
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u64 pcr_enable;
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unsigned int picl_shift;
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2009-01-21 22:30:23 -07:00
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/* Performance counter interrupts run unmasked at PIL level 15.
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* Therefore we can't do things like wakeups and other work
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* that expects IRQ disabling to be adhered to in locking etc.
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*
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* Therefore in such situations we defer the work by signalling
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* a lower level cpu IRQ.
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*/
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2010-04-07 05:41:33 -06:00
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void __irq_entry deferred_pcr_work_irq(int irq, struct pt_regs *regs)
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2009-01-21 22:30:23 -07:00
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{
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2009-09-10 06:59:24 -06:00
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struct pt_regs *old_regs;
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2009-01-21 22:30:23 -07:00
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clear_softint(1 << PIL_DEFERRED_PCR_WORK);
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2009-09-10 06:59:24 -06:00
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old_regs = set_irq_regs(regs);
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irq_enter();
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2010-10-14 00:01:34 -06:00
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#ifdef CONFIG_IRQ_WORK
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irq_work_run();
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2009-09-10 06:59:24 -06:00
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#endif
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irq_exit();
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set_irq_regs(old_regs);
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2009-01-21 22:30:23 -07:00
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}
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2010-10-14 00:01:34 -06:00
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void arch_irq_work_raise(void)
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2009-01-21 22:30:23 -07:00
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{
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set_softint(1 << PIL_DEFERRED_PCR_WORK);
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}
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const struct pcr_ops *pcr_ops;
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EXPORT_SYMBOL_GPL(pcr_ops);
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static u64 direct_pcr_read(void)
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{
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u64 val;
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read_pcr(val);
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return val;
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}
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static void direct_pcr_write(u64 val)
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{
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write_pcr(val);
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}
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static const struct pcr_ops direct_pcr_ops = {
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.read = direct_pcr_read,
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.write = direct_pcr_write,
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};
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static void n2_pcr_write(u64 val)
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{
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unsigned long ret;
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2011-07-27 21:46:25 -06:00
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if (val & PCR_N2_HTRACE) {
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ret = sun4v_niagara2_setperf(HV_N2_PERF_SPARC_CTL, val);
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if (ret != HV_EOK)
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write_pcr(val);
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} else
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2009-01-21 22:30:23 -07:00
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write_pcr(val);
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}
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static const struct pcr_ops n2_pcr_ops = {
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.read = direct_pcr_read,
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.write = n2_pcr_write,
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};
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static unsigned long perf_hsvc_group;
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static unsigned long perf_hsvc_major;
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static unsigned long perf_hsvc_minor;
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static int __init register_perf_hsvc(void)
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{
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if (tlb_type == hypervisor) {
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switch (sun4v_chip_type) {
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case SUN4V_CHIP_NIAGARA1:
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perf_hsvc_group = HV_GRP_NIAG_PERF;
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break;
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case SUN4V_CHIP_NIAGARA2:
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perf_hsvc_group = HV_GRP_N2_CPU;
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break;
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sparc: Detect and handle UltraSPARC-T3 cpu types.
The cpu compatible string we look for is "SPARC-T3".
As far as memset/memcpy optimizations go, we treat this chip the same
as Niagara-T2/T2+. Use cache initializing stores for memset, and use
perfetch, FPU block loads, cache initializing stores, and block stores
for copies.
We use the Niagara-T2 perf support, since T3 is a close relative in
this regard. Later we'll add support for the new events T3 can
report, plus enable T3's new "sample" mode.
For now I haven't added any new ELF hwcap flags. We probably need
to add a couple, for example:
T2 and T3 both support the population count instruction in hardware.
T3 supports VIS3 instructions, including support (finally) for
partitioned shift. One can also now move directly between float
and integer registers.
T3 supports instructions meant to help with Galois Field and other HPC
calculations, such as XOR multiply. Also there are "OP and negate"
instructions, for example "fnmul" which is multiply-and-negate.
T3 recognizes the transactional memory opcodes, however since
transactional memory isn't supported: 1) 'commit' behaves as a NOP and
2) 'chkpt' always branches 3) 'rdcps' returns all zeros and 4) 'wrcps'
behaves as a NOP.
So we'll need about 3 new elf capability flags in the end to represent
all of these things.
Signed-off-by: David S. Miller <davem@davemloft.net>
2011-07-27 22:06:16 -06:00
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case SUN4V_CHIP_NIAGARA3:
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perf_hsvc_group = HV_GRP_KT_CPU;
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break;
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2009-01-21 22:30:23 -07:00
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default:
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return -ENODEV;
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}
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perf_hsvc_major = 1;
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perf_hsvc_minor = 0;
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if (sun4v_hvapi_register(perf_hsvc_group,
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perf_hsvc_major,
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&perf_hsvc_minor)) {
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printk("perfmon: Could not register hvapi.\n");
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return -ENODEV;
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}
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}
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return 0;
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}
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static void __init unregister_perf_hsvc(void)
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{
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if (tlb_type != hypervisor)
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return;
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sun4v_hvapi_unregister(perf_hsvc_group);
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}
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int __init pcr_arch_init(void)
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{
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int err = register_perf_hsvc();
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if (err)
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return err;
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switch (tlb_type) {
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case hypervisor:
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pcr_ops = &n2_pcr_ops;
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2009-01-29 22:22:47 -07:00
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pcr_enable = PCR_N2_ENABLE;
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picl_shift = 2;
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2009-01-21 22:30:23 -07:00
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break;
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case cheetah:
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case cheetah_plus:
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pcr_ops = &direct_pcr_ops;
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2009-01-29 22:22:47 -07:00
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pcr_enable = PCR_SUN4U_ENABLE;
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2009-01-21 22:30:23 -07:00
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break;
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2009-02-06 00:59:04 -07:00
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case spitfire:
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/* UltraSPARC-I/II and derivatives lack a profile
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* counter overflow interrupt so we can't make use of
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* their hardware currently.
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*/
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/* fallthrough */
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2009-01-21 22:30:23 -07:00
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default:
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err = -ENODEV;
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goto out_unregister;
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}
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2009-01-29 22:22:47 -07:00
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return nmi_init();
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2009-01-21 22:30:23 -07:00
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out_unregister:
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unregister_perf_hsvc();
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return err;
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}
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