37 lines
1.1 KiB
C
37 lines
1.1 KiB
C
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/* Board information for the SBCPowerQUICCII, which should be generic for
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* all 8260 boards. The IMMR is now given to us so the hard define
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* will soon be removed. All of the clock values are computed from
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* the configuration SCMR and the Power-On-Reset word.
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*/
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#ifndef __PPC_SBC82xx_H__
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#define __PPC_SBC82xx_H__
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#include <asm/ppcboot.h>
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#define CPM_MAP_ADDR 0xf0000000
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#define SBC82xx_TODC_NVRAM_ADDR 0xd0000000
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#define SBC82xx_MACADDR_NVRAM_FCC1 0x220000c9 /* JP6B */
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#define SBC82xx_MACADDR_NVRAM_SCC1 0x220000cf /* JP6A */
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#define SBC82xx_MACADDR_NVRAM_FCC2 0x220000d5 /* JP7A */
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#define SBC82xx_MACADDR_NVRAM_FCC3 0x220000db /* JP7B */
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/* For our show_cpuinfo hooks. */
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#define CPUINFO_VENDOR "Wind River"
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#define CPUINFO_MACHINE "SBC PowerQUICC II"
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#define BOOTROM_RESTART_ADDR ((uint)0x40000104)
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#define SBC82xx_PC_IRQA (NR_SIU_INTS+0)
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#define SBC82xx_PC_IRQB (NR_SIU_INTS+1)
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#define SBC82xx_MPC185_IRQ (NR_SIU_INTS+2)
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#define SBC82xx_ATM_IRQ (NR_SIU_INTS+3)
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#define SBC82xx_PIRQA (NR_SIU_INTS+4)
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#define SBC82xx_PIRQB (NR_SIU_INTS+5)
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#define SBC82xx_PIRQC (NR_SIU_INTS+6)
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#define SBC82xx_PIRQD (NR_SIU_INTS+7)
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#endif /* __PPC_SBC82xx_H__ */
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