usb: Introduce DesignWare USB3 DRD Driver
The DesignWare USB3 is a highly
configurable IP Core which can be
instantiated as Dual-Role Device (DRD),
Peripheral Only and Host Only (XHCI)
configurations.
Several other parameters can be configured
like amount of FIFO space, amount of TX and
RX endpoints, amount of Host Interrupters,
etc.
The current driver has been validated with
a virtual model of version 1.73a of that core
and with an FPGA burned with version 1.83a
of the DRD core. We have support for PCIe
bus, which is used on FPGA prototyping, and
for the OMAP5, more adaptation (or glue)
layers can be easily added and the driver
is half prepared to handle any possible
configuration the HW engineer has chosen
considering we have the information on
one of the GHWPARAMS registers to do
runtime checking of certain features.
More runtime checks can, and should, be added
in order to make this driver even more flexible
with regards to number of endpoints, FIFO sizes,
transfer types, etc.
While this supports only the device side, for
now, we will add support for Host side (xHCI -
see the updated series Sebastian has sent [1])
and OTG after we have it all stabilized.
[1] http://marc.info/?l=linux-usb&m=131341992020339&w=2
Signed-off-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2011-08-19 09:10:58 -06:00
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/**
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* gadget.h - DesignWare USB3 DRD Gadget Header
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*
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* Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com
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*
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* Authors: Felipe Balbi <balbi@ti.com>,
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* Sebastian Andrzej Siewior <bigeasy@linutronix.de>
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions, and the following disclaimer,
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* without modification.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. The names of the above-listed copyright holders may not be used
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* to endorse or promote products derived from this software without
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* specific prior written permission.
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*
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* ALTERNATIVELY, this software may be distributed under the terms of the
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* GNU General Public License ("GPL") version 2, as published by the Free
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* Software Foundation.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
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* IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
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* THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
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* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
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* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
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* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
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* PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
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* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
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* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
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* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef __DRIVERS_USB_DWC3_GADGET_H
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#define __DRIVERS_USB_DWC3_GADGET_H
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#include <linux/list.h>
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#include <linux/usb/gadget.h>
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#include "io.h"
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struct dwc3;
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#define to_dwc3_ep(ep) (container_of(ep, struct dwc3_ep, endpoint))
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#define gadget_to_dwc(g) (container_of(g, struct dwc3, gadget))
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2011-09-30 01:58:51 -06:00
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/* DEPCFG parameter 1 */
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#define DWC3_DEPCFG_INT_NUM(n) ((n) << 0)
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#define DWC3_DEPCFG_XFER_COMPLETE_EN (1 << 8)
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#define DWC3_DEPCFG_XFER_IN_PROGRESS_EN (1 << 9)
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#define DWC3_DEPCFG_XFER_NOT_READY_EN (1 << 10)
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#define DWC3_DEPCFG_FIFO_ERROR_EN (1 << 11)
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#define DWC3_DEPCFG_STREAM_EVENT_EN (1 << 13)
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#define DWC3_DEPCFG_BINTERVAL_M1(n) ((n) << 16)
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#define DWC3_DEPCFG_STREAM_CAPABLE (1 << 24)
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#define DWC3_DEPCFG_EP_NUMBER(n) ((n) << 25)
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#define DWC3_DEPCFG_BULK_BASED (1 << 30)
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#define DWC3_DEPCFG_FIFO_BASED (1 << 31)
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/* DEPCFG parameter 0 */
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#define DWC3_DEPCFG_EP_TYPE(n) ((n) << 1)
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#define DWC3_DEPCFG_MAX_PACKET_SIZE(n) ((n) << 3)
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#define DWC3_DEPCFG_FIFO_NUMBER(n) ((n) << 17)
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#define DWC3_DEPCFG_BURST_SIZE(n) ((n) << 22)
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#define DWC3_DEPCFG_DATA_SEQ_NUM(n) ((n) << 26)
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2012-02-15 19:56:58 -07:00
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/* This applies for core versions earlier than 1.94a */
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2011-09-30 01:58:51 -06:00
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#define DWC3_DEPCFG_IGN_SEQ_NUM (1 << 31)
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2012-02-15 19:56:58 -07:00
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/* These apply for core versions 1.94a and later */
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#define DWC3_DEPCFG_ACTION_INIT (0 << 30)
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#define DWC3_DEPCFG_ACTION_RESTORE (1 << 30)
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#define DWC3_DEPCFG_ACTION_MODIFY (2 << 30)
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2011-09-30 01:58:51 -06:00
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/* DEPXFERCFG parameter 0 */
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#define DWC3_DEPXFERCFG_NUM_XFER_RES(n) ((n) & 0xffff)
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usb: Introduce DesignWare USB3 DRD Driver
The DesignWare USB3 is a highly
configurable IP Core which can be
instantiated as Dual-Role Device (DRD),
Peripheral Only and Host Only (XHCI)
configurations.
Several other parameters can be configured
like amount of FIFO space, amount of TX and
RX endpoints, amount of Host Interrupters,
etc.
The current driver has been validated with
a virtual model of version 1.73a of that core
and with an FPGA burned with version 1.83a
of the DRD core. We have support for PCIe
bus, which is used on FPGA prototyping, and
for the OMAP5, more adaptation (or glue)
layers can be easily added and the driver
is half prepared to handle any possible
configuration the HW engineer has chosen
considering we have the information on
one of the GHWPARAMS registers to do
runtime checking of certain features.
More runtime checks can, and should, be added
in order to make this driver even more flexible
with regards to number of endpoints, FIFO sizes,
transfer types, etc.
While this supports only the device side, for
now, we will add support for Host side (xHCI -
see the updated series Sebastian has sent [1])
and OTG after we have it all stabilized.
[1] http://marc.info/?l=linux-usb&m=131341992020339&w=2
Signed-off-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2011-08-19 09:10:58 -06:00
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struct dwc3_gadget_ep_cmd_params {
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2011-09-30 01:58:51 -06:00
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u32 param2;
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u32 param1;
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u32 param0;
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};
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usb: Introduce DesignWare USB3 DRD Driver
The DesignWare USB3 is a highly
configurable IP Core which can be
instantiated as Dual-Role Device (DRD),
Peripheral Only and Host Only (XHCI)
configurations.
Several other parameters can be configured
like amount of FIFO space, amount of TX and
RX endpoints, amount of Host Interrupters,
etc.
The current driver has been validated with
a virtual model of version 1.73a of that core
and with an FPGA burned with version 1.83a
of the DRD core. We have support for PCIe
bus, which is used on FPGA prototyping, and
for the OMAP5, more adaptation (or glue)
layers can be easily added and the driver
is half prepared to handle any possible
configuration the HW engineer has chosen
considering we have the information on
one of the GHWPARAMS registers to do
runtime checking of certain features.
More runtime checks can, and should, be added
in order to make this driver even more flexible
with regards to number of endpoints, FIFO sizes,
transfer types, etc.
While this supports only the device side, for
now, we will add support for Host side (xHCI -
see the updated series Sebastian has sent [1])
and OTG after we have it all stabilized.
[1] http://marc.info/?l=linux-usb&m=131341992020339&w=2
Signed-off-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2011-08-19 09:10:58 -06:00
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/* -------------------------------------------------------------------------- */
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#define to_dwc3_request(r) (container_of(r, struct dwc3_request, request))
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static inline struct dwc3_request *next_request(struct list_head *list)
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{
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if (list_empty(list))
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return NULL;
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return list_first_entry(list, struct dwc3_request, list);
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}
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static inline void dwc3_gadget_move_request_queued(struct dwc3_request *req)
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{
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struct dwc3_ep *dep = req->dep;
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req->queued = true;
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list_move_tail(&req->list, &dep->req_queued);
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}
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void dwc3_gadget_giveback(struct dwc3_ep *dep, struct dwc3_request *req,
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int status);
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2012-01-02 09:25:43 -07:00
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int dwc3_gadget_set_test_mode(struct dwc3 *dwc, int mode);
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2012-01-02 09:55:57 -07:00
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int dwc3_gadget_set_link_state(struct dwc3 *dwc, enum dwc3_link_state state);
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2012-01-02 09:25:43 -07:00
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2011-11-04 04:32:47 -06:00
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void dwc3_ep0_interrupt(struct dwc3 *dwc,
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const struct dwc3_event_depevt *event);
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usb: Introduce DesignWare USB3 DRD Driver
The DesignWare USB3 is a highly
configurable IP Core which can be
instantiated as Dual-Role Device (DRD),
Peripheral Only and Host Only (XHCI)
configurations.
Several other parameters can be configured
like amount of FIFO space, amount of TX and
RX endpoints, amount of Host Interrupters,
etc.
The current driver has been validated with
a virtual model of version 1.73a of that core
and with an FPGA burned with version 1.83a
of the DRD core. We have support for PCIe
bus, which is used on FPGA prototyping, and
for the OMAP5, more adaptation (or glue)
layers can be easily added and the driver
is half prepared to handle any possible
configuration the HW engineer has chosen
considering we have the information on
one of the GHWPARAMS registers to do
runtime checking of certain features.
More runtime checks can, and should, be added
in order to make this driver even more flexible
with regards to number of endpoints, FIFO sizes,
transfer types, etc.
While this supports only the device side, for
now, we will add support for Host side (xHCI -
see the updated series Sebastian has sent [1])
and OTG after we have it all stabilized.
[1] http://marc.info/?l=linux-usb&m=131341992020339&w=2
Signed-off-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2011-08-19 09:10:58 -06:00
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void dwc3_ep0_out_start(struct dwc3 *dwc);
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2012-06-25 11:10:43 -06:00
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int dwc3_gadget_ep0_set_halt(struct usb_ep *ep, int value);
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usb: Introduce DesignWare USB3 DRD Driver
The DesignWare USB3 is a highly
configurable IP Core which can be
instantiated as Dual-Role Device (DRD),
Peripheral Only and Host Only (XHCI)
configurations.
Several other parameters can be configured
like amount of FIFO space, amount of TX and
RX endpoints, amount of Host Interrupters,
etc.
The current driver has been validated with
a virtual model of version 1.73a of that core
and with an FPGA burned with version 1.83a
of the DRD core. We have support for PCIe
bus, which is used on FPGA prototyping, and
for the OMAP5, more adaptation (or glue)
layers can be easily added and the driver
is half prepared to handle any possible
configuration the HW engineer has chosen
considering we have the information on
one of the GHWPARAMS registers to do
runtime checking of certain features.
More runtime checks can, and should, be added
in order to make this driver even more flexible
with regards to number of endpoints, FIFO sizes,
transfer types, etc.
While this supports only the device side, for
now, we will add support for Host side (xHCI -
see the updated series Sebastian has sent [1])
and OTG after we have it all stabilized.
[1] http://marc.info/?l=linux-usb&m=131341992020339&w=2
Signed-off-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2011-08-19 09:10:58 -06:00
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int dwc3_gadget_ep0_queue(struct usb_ep *ep, struct usb_request *request,
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gfp_t gfp_flags);
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int __dwc3_gadget_ep_set_halt(struct dwc3_ep *dep, int value);
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int dwc3_send_gadget_ep_cmd(struct dwc3 *dwc, unsigned ep,
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unsigned cmd, struct dwc3_gadget_ep_cmd_params *params);
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2012-04-24 07:19:11 -06:00
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int dwc3_send_gadget_generic_command(struct dwc3 *dwc, int cmd, u32 param);
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usb: Introduce DesignWare USB3 DRD Driver
The DesignWare USB3 is a highly
configurable IP Core which can be
instantiated as Dual-Role Device (DRD),
Peripheral Only and Host Only (XHCI)
configurations.
Several other parameters can be configured
like amount of FIFO space, amount of TX and
RX endpoints, amount of Host Interrupters,
etc.
The current driver has been validated with
a virtual model of version 1.73a of that core
and with an FPGA burned with version 1.83a
of the DRD core. We have support for PCIe
bus, which is used on FPGA prototyping, and
for the OMAP5, more adaptation (or glue)
layers can be easily added and the driver
is half prepared to handle any possible
configuration the HW engineer has chosen
considering we have the information on
one of the GHWPARAMS registers to do
runtime checking of certain features.
More runtime checks can, and should, be added
in order to make this driver even more flexible
with regards to number of endpoints, FIFO sizes,
transfer types, etc.
While this supports only the device side, for
now, we will add support for Host side (xHCI -
see the updated series Sebastian has sent [1])
and OTG after we have it all stabilized.
[1] http://marc.info/?l=linux-usb&m=131341992020339&w=2
Signed-off-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
2011-08-19 09:10:58 -06:00
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/**
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* dwc3_gadget_ep_get_transfer_index - Gets transfer index from HW
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* @dwc: DesignWare USB3 Pointer
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* @number: DWC endpoint number
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*
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* Caller should take care of locking
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*/
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static inline u32 dwc3_gadget_ep_get_transfer_index(struct dwc3 *dwc, u8 number)
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{
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u32 res_id;
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res_id = dwc3_readl(dwc->regs, DWC3_DEPCMD(number));
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return DWC3_DEPCMD_GET_RSC_IDX(res_id);
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}
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/**
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* dwc3_gadget_event_string - returns event name
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* @event: the event code
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*/
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static inline const char *dwc3_gadget_event_string(u8 event)
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{
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switch (event) {
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case DWC3_DEVICE_EVENT_DISCONNECT:
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return "Disconnect";
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case DWC3_DEVICE_EVENT_RESET:
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return "Reset";
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case DWC3_DEVICE_EVENT_CONNECT_DONE:
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return "Connection Done";
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case DWC3_DEVICE_EVENT_LINK_STATUS_CHANGE:
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return "Link Status Change";
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case DWC3_DEVICE_EVENT_WAKEUP:
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return "WakeUp";
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case DWC3_DEVICE_EVENT_EOPF:
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return "End-Of-Frame";
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case DWC3_DEVICE_EVENT_SOF:
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return "Start-Of-Frame";
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case DWC3_DEVICE_EVENT_ERRATIC_ERROR:
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return "Erratic Error";
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case DWC3_DEVICE_EVENT_CMD_CMPL:
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return "Command Complete";
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case DWC3_DEVICE_EVENT_OVERFLOW:
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return "Overflow";
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}
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return "UNKNOWN";
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}
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/**
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* dwc3_ep_event_string - returns event name
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* @event: then event code
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*/
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static inline const char *dwc3_ep_event_string(u8 event)
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{
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switch (event) {
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case DWC3_DEPEVT_XFERCOMPLETE:
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return "Transfer Complete";
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case DWC3_DEPEVT_XFERINPROGRESS:
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return "Transfer In-Progress";
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case DWC3_DEPEVT_XFERNOTREADY:
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return "Transfer Not Ready";
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case DWC3_DEPEVT_RXTXFIFOEVT:
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return "FIFO";
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case DWC3_DEPEVT_STREAMEVT:
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return "Stream";
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case DWC3_DEPEVT_EPCMDCMPLT:
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return "Endpoint Command Complete";
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}
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return "UNKNOWN";
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}
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#endif /* __DRIVERS_USB_DWC3_GADGET_H */
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