2011-01-20 10:50:14 -07:00
|
|
|
/*
|
|
|
|
* Definitions for the NVM Express interface
|
2014-04-11 08:37:39 -06:00
|
|
|
* Copyright (c) 2011-2014, Intel Corporation.
|
2011-01-20 10:50:14 -07:00
|
|
|
*
|
|
|
|
* This program is free software; you can redistribute it and/or modify it
|
|
|
|
* under the terms and conditions of the GNU General Public License,
|
|
|
|
* version 2, as published by the Free Software Foundation.
|
|
|
|
*
|
|
|
|
* This program is distributed in the hope it will be useful, but WITHOUT
|
|
|
|
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
|
|
|
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
|
|
|
* more details.
|
|
|
|
*/
|
|
|
|
|
|
|
|
#ifndef _LINUX_NVME_H
|
|
|
|
#define _LINUX_NVME_H
|
|
|
|
|
2013-06-25 13:14:56 -06:00
|
|
|
#include <uapi/linux/nvme.h>
|
|
|
|
#include <linux/pci.h>
|
|
|
|
#include <linux/miscdevice.h>
|
|
|
|
#include <linux/kref.h>
|
2014-11-04 08:20:14 -07:00
|
|
|
#include <linux/blk-mq.h>
|
2011-01-20 10:50:14 -07:00
|
|
|
|
|
|
|
struct nvme_bar {
|
|
|
|
__u64 cap; /* Controller Capabilities */
|
|
|
|
__u32 vs; /* Version */
|
2011-02-14 10:20:15 -07:00
|
|
|
__u32 intms; /* Interrupt Mask Set */
|
|
|
|
__u32 intmc; /* Interrupt Mask Clear */
|
2011-01-20 10:50:14 -07:00
|
|
|
__u32 cc; /* Controller Configuration */
|
2011-02-14 10:20:15 -07:00
|
|
|
__u32 rsvd1; /* Reserved */
|
2011-01-20 10:50:14 -07:00
|
|
|
__u32 csts; /* Controller Status */
|
2011-02-14 10:20:15 -07:00
|
|
|
__u32 rsvd2; /* Reserved */
|
2011-01-20 10:50:14 -07:00
|
|
|
__u32 aqa; /* Admin Queue Attributes */
|
|
|
|
__u64 asq; /* Admin SQ Base Address */
|
|
|
|
__u64 acq; /* Admin CQ Base Address */
|
|
|
|
};
|
|
|
|
|
2012-07-27 11:57:23 -06:00
|
|
|
#define NVME_CAP_MQES(cap) ((cap) & 0xffff)
|
2011-04-19 13:04:20 -06:00
|
|
|
#define NVME_CAP_TIMEOUT(cap) (((cap) >> 24) & 0xff)
|
2011-10-20 15:00:41 -06:00
|
|
|
#define NVME_CAP_STRIDE(cap) (((cap) >> 32) & 0xf)
|
2012-07-26 11:29:57 -06:00
|
|
|
#define NVME_CAP_MPSMIN(cap) (((cap) >> 48) & 0xf)
|
2014-06-23 11:34:01 -06:00
|
|
|
#define NVME_CAP_MPSMAX(cap) (((cap) >> 52) & 0xf)
|
2011-04-19 13:04:20 -06:00
|
|
|
|
2011-01-20 10:50:14 -07:00
|
|
|
enum {
|
|
|
|
NVME_CC_ENABLE = 1 << 0,
|
|
|
|
NVME_CC_CSS_NVM = 0 << 4,
|
|
|
|
NVME_CC_MPS_SHIFT = 7,
|
|
|
|
NVME_CC_ARB_RR = 0 << 11,
|
|
|
|
NVME_CC_ARB_WRRU = 1 << 11,
|
2011-03-22 13:55:45 -06:00
|
|
|
NVME_CC_ARB_VS = 7 << 11,
|
|
|
|
NVME_CC_SHN_NONE = 0 << 14,
|
|
|
|
NVME_CC_SHN_NORMAL = 1 << 14,
|
|
|
|
NVME_CC_SHN_ABRUPT = 2 << 14,
|
2013-07-15 15:02:22 -06:00
|
|
|
NVME_CC_SHN_MASK = 3 << 14,
|
2011-03-22 13:55:45 -06:00
|
|
|
NVME_CC_IOSQES = 6 << 16,
|
|
|
|
NVME_CC_IOCQES = 4 << 20,
|
2011-01-20 10:50:14 -07:00
|
|
|
NVME_CSTS_RDY = 1 << 0,
|
|
|
|
NVME_CSTS_CFS = 1 << 1,
|
|
|
|
NVME_CSTS_SHST_NORMAL = 0 << 2,
|
|
|
|
NVME_CSTS_SHST_OCCUR = 1 << 2,
|
|
|
|
NVME_CSTS_SHST_CMPLT = 2 << 2,
|
2013-07-15 15:02:22 -06:00
|
|
|
NVME_CSTS_SHST_MASK = 3 << 2,
|
2011-01-20 10:50:14 -07:00
|
|
|
};
|
|
|
|
|
|
|
|
#define NVME_VS(major, minor) (major << 16 | minor)
|
|
|
|
|
2014-06-03 21:04:30 -06:00
|
|
|
extern unsigned char nvme_io_timeout;
|
|
|
|
#define NVME_IO_TIMEOUT (nvme_io_timeout * HZ)
|
2013-03-04 18:40:57 -07:00
|
|
|
|
|
|
|
/*
|
|
|
|
* Represents an NVM Express device. Each nvme_dev is a PCI function.
|
|
|
|
*/
|
|
|
|
struct nvme_dev {
|
|
|
|
struct list_head node;
|
2014-11-04 08:20:14 -07:00
|
|
|
struct nvme_queue **queues;
|
|
|
|
struct request_queue *admin_q;
|
|
|
|
struct blk_mq_tag_set tagset;
|
|
|
|
struct blk_mq_tag_set admin_tagset;
|
2013-03-04 18:40:57 -07:00
|
|
|
u32 __iomem *dbs;
|
|
|
|
struct pci_dev *pci_dev;
|
|
|
|
struct dma_pool *prp_page_pool;
|
|
|
|
struct dma_pool *prp_small_pool;
|
|
|
|
int instance;
|
2014-03-24 10:46:25 -06:00
|
|
|
unsigned queue_count;
|
|
|
|
unsigned online_queues;
|
|
|
|
unsigned max_qid;
|
|
|
|
int q_depth;
|
2013-09-09 21:25:37 -06:00
|
|
|
u32 db_stride;
|
2013-03-04 18:40:57 -07:00
|
|
|
u32 ctrl_config;
|
|
|
|
struct msix_entry *entry;
|
|
|
|
struct nvme_bar __iomem *bar;
|
|
|
|
struct list_head namespaces;
|
2013-02-19 10:17:58 -07:00
|
|
|
struct kref kref;
|
|
|
|
struct miscdevice miscdev;
|
2014-03-07 08:24:49 -07:00
|
|
|
work_func_t reset_workfn;
|
2013-12-10 13:10:36 -07:00
|
|
|
struct work_struct reset_work;
|
2013-02-19 10:17:58 -07:00
|
|
|
char name[12];
|
2013-03-04 18:40:57 -07:00
|
|
|
char serial[20];
|
|
|
|
char model[40];
|
|
|
|
char firmware_rev[8];
|
|
|
|
u32 max_hw_sectors;
|
2013-04-09 17:13:20 -06:00
|
|
|
u32 stripe_size;
|
2014-06-23 11:34:01 -06:00
|
|
|
u32 page_size;
|
2013-03-04 18:40:57 -07:00
|
|
|
u16 oncs;
|
2013-12-10 13:10:38 -07:00
|
|
|
u16 abort_limit;
|
2014-06-18 13:58:57 -06:00
|
|
|
u8 event_limit;
|
2014-04-29 11:41:28 -06:00
|
|
|
u8 vwc;
|
2013-12-10 13:10:37 -07:00
|
|
|
u8 initialized;
|
2013-03-04 18:40:57 -07:00
|
|
|
};
|
|
|
|
|
|
|
|
/*
|
|
|
|
* An NVM Express namespace is equivalent to a SCSI LUN
|
|
|
|
*/
|
|
|
|
struct nvme_ns {
|
|
|
|
struct list_head list;
|
|
|
|
|
|
|
|
struct nvme_dev *dev;
|
|
|
|
struct request_queue *queue;
|
|
|
|
struct gendisk *disk;
|
|
|
|
|
2013-07-08 15:26:25 -06:00
|
|
|
unsigned ns_id;
|
2013-03-04 18:40:57 -07:00
|
|
|
int lba_shift;
|
2013-04-23 17:23:59 -06:00
|
|
|
int ms;
|
2013-03-04 18:40:58 -07:00
|
|
|
u64 mode_select_num_blocks;
|
|
|
|
u32 mode_select_block_len;
|
2013-03-04 18:40:57 -07:00
|
|
|
};
|
|
|
|
|
|
|
|
/*
|
|
|
|
* The nvme_iod describes the data in an I/O, including the list of PRP
|
|
|
|
* entries. You can't see it in this data structure because C doesn't let
|
|
|
|
* me express that. Use nvme_alloc_iod to ensure there's enough space
|
|
|
|
* allocated to store the PRP list.
|
|
|
|
*/
|
|
|
|
struct nvme_iod {
|
|
|
|
void *private; /* For the use of the submitter of the I/O */
|
|
|
|
int npages; /* In the PRP list. 0 means small pool in use */
|
|
|
|
int offset; /* Of PRP list */
|
|
|
|
int nents; /* Used in scatterlist */
|
|
|
|
int length; /* Of data, in bytes */
|
|
|
|
dma_addr_t first_dma;
|
2014-04-03 16:45:23 -06:00
|
|
|
struct list_head node;
|
2013-03-04 18:40:57 -07:00
|
|
|
struct scatterlist sg[0];
|
|
|
|
};
|
2013-03-04 18:40:58 -07:00
|
|
|
|
2013-03-27 19:28:22 -06:00
|
|
|
static inline u64 nvme_block_nr(struct nvme_ns *ns, sector_t sector)
|
|
|
|
{
|
|
|
|
return (sector >> (ns->lba_shift - 9));
|
|
|
|
}
|
|
|
|
|
2013-03-04 18:40:58 -07:00
|
|
|
/**
|
|
|
|
* nvme_free_iod - frees an nvme_iod
|
|
|
|
* @dev: The device that the I/O was submitted to
|
|
|
|
* @iod: The memory to free
|
|
|
|
*/
|
|
|
|
void nvme_free_iod(struct nvme_dev *dev, struct nvme_iod *iod);
|
|
|
|
|
2014-11-04 08:20:14 -07:00
|
|
|
int nvme_setup_prps(struct nvme_dev *, struct nvme_iod *, int, gfp_t);
|
2013-03-04 18:40:58 -07:00
|
|
|
struct nvme_iod *nvme_map_user_pages(struct nvme_dev *dev, int write,
|
|
|
|
unsigned long addr, unsigned length);
|
|
|
|
void nvme_unmap_user_pages(struct nvme_dev *dev, int write,
|
|
|
|
struct nvme_iod *iod);
|
2014-11-04 08:20:14 -07:00
|
|
|
int nvme_submit_io_cmd(struct nvme_dev *, struct nvme_ns *,
|
|
|
|
struct nvme_command *, u32 *);
|
|
|
|
int nvme_submit_flush_data(struct nvme_queue *nvmeq, struct nvme_ns *ns);
|
2013-03-04 18:40:58 -07:00
|
|
|
int nvme_submit_admin_cmd(struct nvme_dev *, struct nvme_command *,
|
|
|
|
u32 *result);
|
|
|
|
int nvme_identify(struct nvme_dev *, unsigned nsid, unsigned cns,
|
|
|
|
dma_addr_t dma_addr);
|
|
|
|
int nvme_get_features(struct nvme_dev *dev, unsigned fid, unsigned nsid,
|
|
|
|
dma_addr_t dma_addr, u32 *result);
|
|
|
|
int nvme_set_features(struct nvme_dev *dev, unsigned fid, unsigned dword11,
|
|
|
|
dma_addr_t dma_addr, u32 *result);
|
|
|
|
|
|
|
|
struct sg_io_hdr;
|
|
|
|
|
|
|
|
int nvme_sg_io(struct nvme_ns *ns, struct sg_io_hdr __user *u_hdr);
|
2013-10-23 13:07:34 -06:00
|
|
|
int nvme_sg_io32(struct nvme_ns *ns, unsigned long arg);
|
2013-03-04 18:40:58 -07:00
|
|
|
int nvme_sg_get_version_num(int __user *ip);
|
|
|
|
|
2011-01-20 10:50:14 -07:00
|
|
|
#endif /* _LINUX_NVME_H */
|