59 lines
1.5 KiB
C
59 lines
1.5 KiB
C
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/*
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* abyss.h: Header for the abyss tms380tr module
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*
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* Authors:
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* - Adam Fritzler <mid@auk.cx>
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*/
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#ifndef __LINUX_MADGETR_H
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#define __LINUX_MADGETR_H
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#ifdef __KERNEL__
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/*
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* For Madge Smart 16/4 PCI Mk2. Since we increment the base address
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* to get everything correct for the TMS SIF, we do these as negatives
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* as they fall below the SIF in addressing.
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*/
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#define PCIBM2_INT_STATUS_REG ((short)-15)/* 0x01 */
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#define PCIBM2_INT_CONTROL_REG ((short)-14)/* 0x02 */
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#define PCIBM2_RESET_REG ((short)-12)/* 0x04 */
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#define PCIBM2_SEEPROM_REG ((short)-9) /* 0x07 */
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#define PCIBM2_INT_CONTROL_REG_SINTEN 0x02
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#define PCIBM2_INT_CONTROL_REG_PCI_ERR_ENABLE 0x80
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#define PCIBM2_INT_STATUS_REG_PCI_ERR 0x80
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#define PCIBM2_RESET_REG_CHIP_NRES 0x01
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#define PCIBM2_RESET_REG_FIFO_NRES 0x02
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#define PCIBM2_RESET_REG_SIF_NRES 0x04
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#define PCIBM2_FIFO_THRESHOLD 0x21
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#define PCIBM2_BURST_LENGTH 0x22
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/*
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* Bits in PCIBM2_SEEPROM_REG.
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*/
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#define AT24_ENABLE 0x04
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#define AT24_DATA 0x02
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#define AT24_CLOCK 0x01
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/*
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* AT24 Commands.
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*/
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#define AT24_WRITE 0xA0
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#define AT24_READ 0xA1
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/*
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* Addresses in AT24 SEEPROM.
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*/
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#define PCIBM2_SEEPROM_BIA 0x12
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#define PCIBM2_SEEPROM_RING_SPEED 0x18
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#define PCIBM2_SEEPROM_RAM_SIZE 0x1A
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#define PCIBM2_SEEPROM_HWF1 0x1C
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#define PCIBM2_SEEPROM_HWF2 0x1E
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#endif /* __KERNEL__ */
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#endif /* __LINUX_MADGETR_H */
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