154 lines
5.6 KiB
C
154 lines
5.6 KiB
C
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/* Copyright (c) 2009, Code Aurora Forum. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are
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* met:
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* * Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* * Redistributions in binary form must reproduce the above
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* copyright notice, this list of conditions and the following
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* disclaimer in the documentation and/or other materials provided
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* with the distribution.
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* * Neither the name of Code Aurora Forum, Inc. nor the names of its
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* contributors may be used to endorse or promote products derived
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* from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED
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* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
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* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT
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* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS
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* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
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* BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
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* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
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* OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
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* IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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*/
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#ifndef __ARCH_ARM_MACH_MSM_CLOCK_PCOM_H
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#define __ARCH_ARM_MACH_MSM_CLOCK_PCOM_H
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/* clock IDs used by the modem processor */
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#define P_ACPU_CLK 0 /* Applications processor clock */
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#define P_ADM_CLK 1 /* Applications data mover clock */
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#define P_ADSP_CLK 2 /* ADSP clock */
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#define P_EBI1_CLK 3 /* External bus interface 1 clock */
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#define P_EBI2_CLK 4 /* External bus interface 2 clock */
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#define P_ECODEC_CLK 5 /* External CODEC clock */
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#define P_EMDH_CLK 6 /* External MDDI host clock */
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#define P_GP_CLK 7 /* General purpose clock */
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#define P_GRP_3D_CLK 8 /* Graphics clock */
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#define P_I2C_CLK 9 /* I2C clock */
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#define P_ICODEC_RX_CLK 10 /* Internal CODEX RX clock */
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#define P_ICODEC_TX_CLK 11 /* Internal CODEX TX clock */
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#define P_IMEM_CLK 12 /* Internal graphics memory clock */
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#define P_MDC_CLK 13 /* MDDI client clock */
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#define P_MDP_CLK 14 /* Mobile display processor clock */
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#define P_PBUS_CLK 15 /* Peripheral bus clock */
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#define P_PCM_CLK 16 /* PCM clock */
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#define P_PMDH_CLK 17 /* Primary MDDI host clock */
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#define P_SDAC_CLK 18 /* Stereo DAC clock */
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#define P_SDC1_CLK 19 /* Secure Digital Card clocks */
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#define P_SDC1_P_CLK 20
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#define P_SDC2_CLK 21
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#define P_SDC2_P_CLK 22
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#define P_SDC3_CLK 23
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#define P_SDC3_P_CLK 24
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#define P_SDC4_CLK 25
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#define P_SDC4_P_CLK 26
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#define P_TSIF_CLK 27 /* Transport Stream Interface clocks */
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#define P_TSIF_REF_CLK 28
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#define P_TV_DAC_CLK 29 /* TV clocks */
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#define P_TV_ENC_CLK 30
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#define P_UART1_CLK 31 /* UART clocks */
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#define P_UART2_CLK 32
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#define P_UART3_CLK 33
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#define P_UART1DM_CLK 34
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#define P_UART2DM_CLK 35
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#define P_USB_HS_CLK 36 /* High speed USB core clock */
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#define P_USB_HS_P_CLK 37 /* High speed USB pbus clock */
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#define P_USB_OTG_CLK 38 /* Full speed USB clock */
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#define P_VDC_CLK 39 /* Video controller clock */
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#define P_VFE_MDC_CLK 40 /* Camera / Video Front End clock */
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#define P_VFE_CLK 41 /* VFE MDDI client clock */
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#define P_MDP_LCDC_PCLK_CLK 42
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#define P_MDP_LCDC_PAD_PCLK_CLK 43
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#define P_MDP_VSYNC_CLK 44
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#define P_SPI_CLK 45
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#define P_VFE_AXI_CLK 46
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#define P_USB_HS2_CLK 47 /* High speed USB 2 core clock */
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#define P_USB_HS2_P_CLK 48 /* High speed USB 2 pbus clock */
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#define P_USB_HS3_CLK 49 /* High speed USB 3 core clock */
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#define P_USB_HS3_P_CLK 50 /* High speed USB 3 pbus clock */
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#define P_GRP_3D_P_CLK 51 /* Graphics pbus clock */
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#define P_USB_PHY_CLK 52 /* USB PHY clock */
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#define P_USB_HS_CORE_CLK 53 /* High speed USB 1 core clock */
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#define P_USB_HS2_CORE_CLK 54 /* High speed USB 2 core clock */
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#define P_USB_HS3_CORE_CLK 55 /* High speed USB 3 core clock */
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#define P_CAM_M_CLK 56
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#define P_CAMIF_PAD_P_CLK 57
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#define P_GRP_2D_CLK 58
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#define P_GRP_2D_P_CLK 59
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#define P_I2S_CLK 60
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#define P_JPEG_CLK 61
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#define P_JPEG_P_CLK 62
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#define P_LPA_CODEC_CLK 63
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#define P_LPA_CORE_CLK 64
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#define P_LPA_P_CLK 65
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#define P_MDC_IO_CLK 66
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#define P_MDC_P_CLK 67
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#define P_MFC_CLK 68
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#define P_MFC_DIV2_CLK 69
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#define P_MFC_P_CLK 70
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#define P_QUP_I2C_CLK 71
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#define P_ROTATOR_IMEM_CLK 72
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#define P_ROTATOR_P_CLK 73
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#define P_VFE_CAMIF_CLK 74
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#define P_VFE_P_CLK 75
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#define P_VPE_CLK 76
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#define P_I2C_2_CLK 77
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#define P_MI2S_CODEC_RX_S_CLK 78
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#define P_MI2S_CODEC_RX_M_CLK 79
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#define P_MI2S_CODEC_TX_S_CLK 80
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#define P_MI2S_CODEC_TX_M_CLK 81
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#define P_PMDH_P_CLK 82
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#define P_EMDH_P_CLK 83
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#define P_SPI_P_CLK 84
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#define P_TSIF_P_CLK 85
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#define P_MDP_P_CLK 86
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#define P_SDAC_M_CLK 87
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#define P_MI2S_S_CLK 88
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#define P_MI2S_M_CLK 89
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#define P_AXI_ROTATOR_CLK 90
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#define P_HDMI_CLK 91
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#define P_CSI0_CLK 92
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#define P_CSI0_VFE_CLK 93
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#define P_CSI0_P_CLK 94
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#define P_CSI1_CLK 95
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#define P_CSI1_VFE_CLK 96
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#define P_CSI1_P_CLK 97
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#define P_GSBI_CLK 98
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#define P_GSBI_P_CLK 99
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#define P_NR_CLKS 100
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struct clk_ops;
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extern struct clk_ops clk_ops_pcom;
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int pc_clk_reset(unsigned id, enum clk_reset_action action);
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#define CLK_PCOM(clk_name, clk_id, clk_dev, clk_flags) { \
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.name = clk_name, \
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.id = P_##clk_id, \
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.remote_id = P_##clk_id, \
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.ops = &clk_ops_pcom, \
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.flags = clk_flags, \
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.dev = clk_dev, \
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.dbg_name = #clk_id, \
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}
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#endif
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