atmel-mci: Driver for Atmel on-chip MMC controllers
This is a driver for the MMC controller on the AP7000 chips from
Atmel. It should in theory work on AT91 systems too with some
tweaking, but since the DMA interface is quite different, it's not
entirely clear if it's worth merging this with the at91_mci driver.
This driver has been around for a while in BSPs and kernel sources
provided by Atmel, but this particular version uses the generic DMA
Engine framework (with the slave extensions) instead of an
avr32-only DMA controller framework.
This driver can also use PIO transfers when no DMA channels are
available, and for transfers where using DMA may be difficult or
impractical for some reason (e.g. the DMA setup overhead is usually
not worth it for very short transfers, and badly aligned buffers or
lengths are difficult to handle.)
Currently, the driver only support PIO transfers. DMA support has been
split out to a separate patch to hopefully make it easier to review.
The driver has been tested using mmc-block and ext3fs on several SD,
SDHC and MMC+ cards. Reads and writes work fine, with read transfer
rates up to 3.5 MiB/s on fast cards with debugging disabled.
The driver has also been tested using the mmc_test module on the same
cards. All tests except 7, 9, 15 and 17 succeed. The first two are
unsupported by all the cards I have, so I don't know if the driver
handles this correctly. The last two fail because the hardware flags a
Data CRC Error instead of a Data Timeout error. I'm not sure how to deal
with that.
Documentation for this controller can be found in many data sheets from
Atmel, including the AT32AP7000 data sheet which can be found here:
http://www.atmel.com/dyn/products/datasheets.asp?family_id=682
Signed-off-by: Haavard Skinnemoen <haavard.skinnemoen@atmel.com>
Signed-off-by: Pierre Ossman <drzeus@drzeus.cx>
2008-06-30 10:35:03 -06:00
|
|
|
/*
|
|
|
|
* Atmel MultiMedia Card Interface driver
|
|
|
|
*
|
|
|
|
* Copyright (C) 2004-2008 Atmel Corporation
|
|
|
|
*
|
|
|
|
* This program is free software; you can redistribute it and/or modify
|
|
|
|
* it under the terms of the GNU General Public License version 2 as
|
|
|
|
* published by the Free Software Foundation.
|
|
|
|
*/
|
|
|
|
#include <linux/blkdev.h>
|
|
|
|
#include <linux/clk.h>
|
2008-07-24 06:18:59 -06:00
|
|
|
#include <linux/debugfs.h>
|
atmel-mci: Driver for Atmel on-chip MMC controllers
This is a driver for the MMC controller on the AP7000 chips from
Atmel. It should in theory work on AT91 systems too with some
tweaking, but since the DMA interface is quite different, it's not
entirely clear if it's worth merging this with the at91_mci driver.
This driver has been around for a while in BSPs and kernel sources
provided by Atmel, but this particular version uses the generic DMA
Engine framework (with the slave extensions) instead of an
avr32-only DMA controller framework.
This driver can also use PIO transfers when no DMA channels are
available, and for transfers where using DMA may be difficult or
impractical for some reason (e.g. the DMA setup overhead is usually
not worth it for very short transfers, and badly aligned buffers or
lengths are difficult to handle.)
Currently, the driver only support PIO transfers. DMA support has been
split out to a separate patch to hopefully make it easier to review.
The driver has been tested using mmc-block and ext3fs on several SD,
SDHC and MMC+ cards. Reads and writes work fine, with read transfer
rates up to 3.5 MiB/s on fast cards with debugging disabled.
The driver has also been tested using the mmc_test module on the same
cards. All tests except 7, 9, 15 and 17 succeed. The first two are
unsupported by all the cards I have, so I don't know if the driver
handles this correctly. The last two fail because the hardware flags a
Data CRC Error instead of a Data Timeout error. I'm not sure how to deal
with that.
Documentation for this controller can be found in many data sheets from
Atmel, including the AT32AP7000 data sheet which can be found here:
http://www.atmel.com/dyn/products/datasheets.asp?family_id=682
Signed-off-by: Haavard Skinnemoen <haavard.skinnemoen@atmel.com>
Signed-off-by: Pierre Ossman <drzeus@drzeus.cx>
2008-06-30 10:35:03 -06:00
|
|
|
#include <linux/device.h>
|
2008-07-30 12:29:03 -06:00
|
|
|
#include <linux/dmaengine.h>
|
|
|
|
#include <linux/dma-mapping.h>
|
2008-07-18 00:48:09 -06:00
|
|
|
#include <linux/err.h>
|
2008-07-27 03:34:45 -06:00
|
|
|
#include <linux/gpio.h>
|
atmel-mci: Driver for Atmel on-chip MMC controllers
This is a driver for the MMC controller on the AP7000 chips from
Atmel. It should in theory work on AT91 systems too with some
tweaking, but since the DMA interface is quite different, it's not
entirely clear if it's worth merging this with the at91_mci driver.
This driver has been around for a while in BSPs and kernel sources
provided by Atmel, but this particular version uses the generic DMA
Engine framework (with the slave extensions) instead of an
avr32-only DMA controller framework.
This driver can also use PIO transfers when no DMA channels are
available, and for transfers where using DMA may be difficult or
impractical for some reason (e.g. the DMA setup overhead is usually
not worth it for very short transfers, and badly aligned buffers or
lengths are difficult to handle.)
Currently, the driver only support PIO transfers. DMA support has been
split out to a separate patch to hopefully make it easier to review.
The driver has been tested using mmc-block and ext3fs on several SD,
SDHC and MMC+ cards. Reads and writes work fine, with read transfer
rates up to 3.5 MiB/s on fast cards with debugging disabled.
The driver has also been tested using the mmc_test module on the same
cards. All tests except 7, 9, 15 and 17 succeed. The first two are
unsupported by all the cards I have, so I don't know if the driver
handles this correctly. The last two fail because the hardware flags a
Data CRC Error instead of a Data Timeout error. I'm not sure how to deal
with that.
Documentation for this controller can be found in many data sheets from
Atmel, including the AT32AP7000 data sheet which can be found here:
http://www.atmel.com/dyn/products/datasheets.asp?family_id=682
Signed-off-by: Haavard Skinnemoen <haavard.skinnemoen@atmel.com>
Signed-off-by: Pierre Ossman <drzeus@drzeus.cx>
2008-06-30 10:35:03 -06:00
|
|
|
#include <linux/init.h>
|
|
|
|
#include <linux/interrupt.h>
|
2014-09-23 06:51:48 -06:00
|
|
|
#include <linux/io.h>
|
atmel-mci: Driver for Atmel on-chip MMC controllers
This is a driver for the MMC controller on the AP7000 chips from
Atmel. It should in theory work on AT91 systems too with some
tweaking, but since the DMA interface is quite different, it's not
entirely clear if it's worth merging this with the at91_mci driver.
This driver has been around for a while in BSPs and kernel sources
provided by Atmel, but this particular version uses the generic DMA
Engine framework (with the slave extensions) instead of an
avr32-only DMA controller framework.
This driver can also use PIO transfers when no DMA channels are
available, and for transfers where using DMA may be difficult or
impractical for some reason (e.g. the DMA setup overhead is usually
not worth it for very short transfers, and badly aligned buffers or
lengths are difficult to handle.)
Currently, the driver only support PIO transfers. DMA support has been
split out to a separate patch to hopefully make it easier to review.
The driver has been tested using mmc-block and ext3fs on several SD,
SDHC and MMC+ cards. Reads and writes work fine, with read transfer
rates up to 3.5 MiB/s on fast cards with debugging disabled.
The driver has also been tested using the mmc_test module on the same
cards. All tests except 7, 9, 15 and 17 succeed. The first two are
unsupported by all the cards I have, so I don't know if the driver
handles this correctly. The last two fail because the hardware flags a
Data CRC Error instead of a Data Timeout error. I'm not sure how to deal
with that.
Documentation for this controller can be found in many data sheets from
Atmel, including the AT32AP7000 data sheet which can be found here:
http://www.atmel.com/dyn/products/datasheets.asp?family_id=682
Signed-off-by: Haavard Skinnemoen <haavard.skinnemoen@atmel.com>
Signed-off-by: Pierre Ossman <drzeus@drzeus.cx>
2008-06-30 10:35:03 -06:00
|
|
|
#include <linux/ioport.h>
|
|
|
|
#include <linux/module.h>
|
2012-07-24 07:30:03 -06:00
|
|
|
#include <linux/of.h>
|
|
|
|
#include <linux/of_device.h>
|
|
|
|
#include <linux/of_gpio.h>
|
atmel-mci: Driver for Atmel on-chip MMC controllers
This is a driver for the MMC controller on the AP7000 chips from
Atmel. It should in theory work on AT91 systems too with some
tweaking, but since the DMA interface is quite different, it's not
entirely clear if it's worth merging this with the at91_mci driver.
This driver has been around for a while in BSPs and kernel sources
provided by Atmel, but this particular version uses the generic DMA
Engine framework (with the slave extensions) instead of an
avr32-only DMA controller framework.
This driver can also use PIO transfers when no DMA channels are
available, and for transfers where using DMA may be difficult or
impractical for some reason (e.g. the DMA setup overhead is usually
not worth it for very short transfers, and badly aligned buffers or
lengths are difficult to handle.)
Currently, the driver only support PIO transfers. DMA support has been
split out to a separate patch to hopefully make it easier to review.
The driver has been tested using mmc-block and ext3fs on several SD,
SDHC and MMC+ cards. Reads and writes work fine, with read transfer
rates up to 3.5 MiB/s on fast cards with debugging disabled.
The driver has also been tested using the mmc_test module on the same
cards. All tests except 7, 9, 15 and 17 succeed. The first two are
unsupported by all the cards I have, so I don't know if the driver
handles this correctly. The last two fail because the hardware flags a
Data CRC Error instead of a Data Timeout error. I'm not sure how to deal
with that.
Documentation for this controller can be found in many data sheets from
Atmel, including the AT32AP7000 data sheet which can be found here:
http://www.atmel.com/dyn/products/datasheets.asp?family_id=682
Signed-off-by: Haavard Skinnemoen <haavard.skinnemoen@atmel.com>
Signed-off-by: Pierre Ossman <drzeus@drzeus.cx>
2008-06-30 10:35:03 -06:00
|
|
|
#include <linux/platform_device.h>
|
|
|
|
#include <linux/scatterlist.h>
|
2008-07-24 06:18:59 -06:00
|
|
|
#include <linux/seq_file.h>
|
include cleanup: Update gfp.h and slab.h includes to prepare for breaking implicit slab.h inclusion from percpu.h
percpu.h is included by sched.h and module.h and thus ends up being
included when building most .c files. percpu.h includes slab.h which
in turn includes gfp.h making everything defined by the two files
universally available and complicating inclusion dependencies.
percpu.h -> slab.h dependency is about to be removed. Prepare for
this change by updating users of gfp and slab facilities include those
headers directly instead of assuming availability. As this conversion
needs to touch large number of source files, the following script is
used as the basis of conversion.
http://userweb.kernel.org/~tj/misc/slabh-sweep.py
The script does the followings.
* Scan files for gfp and slab usages and update includes such that
only the necessary includes are there. ie. if only gfp is used,
gfp.h, if slab is used, slab.h.
* When the script inserts a new include, it looks at the include
blocks and try to put the new include such that its order conforms
to its surrounding. It's put in the include block which contains
core kernel includes, in the same order that the rest are ordered -
alphabetical, Christmas tree, rev-Xmas-tree or at the end if there
doesn't seem to be any matching order.
* If the script can't find a place to put a new include (mostly
because the file doesn't have fitting include block), it prints out
an error message indicating which .h file needs to be added to the
file.
The conversion was done in the following steps.
1. The initial automatic conversion of all .c files updated slightly
over 4000 files, deleting around 700 includes and adding ~480 gfp.h
and ~3000 slab.h inclusions. The script emitted errors for ~400
files.
2. Each error was manually checked. Some didn't need the inclusion,
some needed manual addition while adding it to implementation .h or
embedding .c file was more appropriate for others. This step added
inclusions to around 150 files.
3. The script was run again and the output was compared to the edits
from #2 to make sure no file was left behind.
4. Several build tests were done and a couple of problems were fixed.
e.g. lib/decompress_*.c used malloc/free() wrappers around slab
APIs requiring slab.h to be added manually.
5. The script was run on all .h files but without automatically
editing them as sprinkling gfp.h and slab.h inclusions around .h
files could easily lead to inclusion dependency hell. Most gfp.h
inclusion directives were ignored as stuff from gfp.h was usually
wildly available and often used in preprocessor macros. Each
slab.h inclusion directive was examined and added manually as
necessary.
6. percpu.h was updated not to include slab.h.
7. Build test were done on the following configurations and failures
were fixed. CONFIG_GCOV_KERNEL was turned off for all tests (as my
distributed build env didn't work with gcov compiles) and a few
more options had to be turned off depending on archs to make things
build (like ipr on powerpc/64 which failed due to missing writeq).
* x86 and x86_64 UP and SMP allmodconfig and a custom test config.
* powerpc and powerpc64 SMP allmodconfig
* sparc and sparc64 SMP allmodconfig
* ia64 SMP allmodconfig
* s390 SMP allmodconfig
* alpha SMP allmodconfig
* um on x86_64 SMP allmodconfig
8. percpu.h modifications were reverted so that it could be applied as
a separate patch and serve as bisection point.
Given the fact that I had only a couple of failures from tests on step
6, I'm fairly confident about the coverage of this conversion patch.
If there is a breakage, it's likely to be something in one of the arch
headers which should be easily discoverable easily on most builds of
the specific arch.
Signed-off-by: Tejun Heo <tj@kernel.org>
Guess-its-ok-by: Christoph Lameter <cl@linux-foundation.org>
Cc: Ingo Molnar <mingo@redhat.com>
Cc: Lee Schermerhorn <Lee.Schermerhorn@hp.com>
2010-03-24 02:04:11 -06:00
|
|
|
#include <linux/slab.h>
|
2008-07-24 06:18:59 -06:00
|
|
|
#include <linux/stat.h>
|
2012-02-01 03:42:27 -07:00
|
|
|
#include <linux/types.h>
|
atmel-mci: Driver for Atmel on-chip MMC controllers
This is a driver for the MMC controller on the AP7000 chips from
Atmel. It should in theory work on AT91 systems too with some
tweaking, but since the DMA interface is quite different, it's not
entirely clear if it's worth merging this with the at91_mci driver.
This driver has been around for a while in BSPs and kernel sources
provided by Atmel, but this particular version uses the generic DMA
Engine framework (with the slave extensions) instead of an
avr32-only DMA controller framework.
This driver can also use PIO transfers when no DMA channels are
available, and for transfers where using DMA may be difficult or
impractical for some reason (e.g. the DMA setup overhead is usually
not worth it for very short transfers, and badly aligned buffers or
lengths are difficult to handle.)
Currently, the driver only support PIO transfers. DMA support has been
split out to a separate patch to hopefully make it easier to review.
The driver has been tested using mmc-block and ext3fs on several SD,
SDHC and MMC+ cards. Reads and writes work fine, with read transfer
rates up to 3.5 MiB/s on fast cards with debugging disabled.
The driver has also been tested using the mmc_test module on the same
cards. All tests except 7, 9, 15 and 17 succeed. The first two are
unsupported by all the cards I have, so I don't know if the driver
handles this correctly. The last two fail because the hardware flags a
Data CRC Error instead of a Data Timeout error. I'm not sure how to deal
with that.
Documentation for this controller can be found in many data sheets from
Atmel, including the AT32AP7000 data sheet which can be found here:
http://www.atmel.com/dyn/products/datasheets.asp?family_id=682
Signed-off-by: Haavard Skinnemoen <haavard.skinnemoen@atmel.com>
Signed-off-by: Pierre Ossman <drzeus@drzeus.cx>
2008-06-30 10:35:03 -06:00
|
|
|
|
|
|
|
#include <linux/mmc/host.h>
|
2010-12-10 11:14:32 -07:00
|
|
|
#include <linux/mmc/sdio.h>
|
2009-12-14 19:01:30 -07:00
|
|
|
|
2008-11-20 07:59:12 -07:00
|
|
|
#include <linux/atmel-mci.h>
|
2011-08-11 09:25:44 -06:00
|
|
|
#include <linux/atmel_pdc.h>
|
2014-10-29 22:00:41 -06:00
|
|
|
#include <linux/pm.h>
|
|
|
|
#include <linux/pm_runtime.h>
|
2014-11-06 17:48:13 -07:00
|
|
|
#include <linux/pinctrl/consumer.h>
|
atmel-mci: Driver for Atmel on-chip MMC controllers
This is a driver for the MMC controller on the AP7000 chips from
Atmel. It should in theory work on AT91 systems too with some
tweaking, but since the DMA interface is quite different, it's not
entirely clear if it's worth merging this with the at91_mci driver.
This driver has been around for a while in BSPs and kernel sources
provided by Atmel, but this particular version uses the generic DMA
Engine framework (with the slave extensions) instead of an
avr32-only DMA controller framework.
This driver can also use PIO transfers when no DMA channels are
available, and for transfers where using DMA may be difficult or
impractical for some reason (e.g. the DMA setup overhead is usually
not worth it for very short transfers, and badly aligned buffers or
lengths are difficult to handle.)
Currently, the driver only support PIO transfers. DMA support has been
split out to a separate patch to hopefully make it easier to review.
The driver has been tested using mmc-block and ext3fs on several SD,
SDHC and MMC+ cards. Reads and writes work fine, with read transfer
rates up to 3.5 MiB/s on fast cards with debugging disabled.
The driver has also been tested using the mmc_test module on the same
cards. All tests except 7, 9, 15 and 17 succeed. The first two are
unsupported by all the cards I have, so I don't know if the driver
handles this correctly. The last two fail because the hardware flags a
Data CRC Error instead of a Data Timeout error. I'm not sure how to deal
with that.
Documentation for this controller can be found in many data sheets from
Atmel, including the AT32AP7000 data sheet which can be found here:
http://www.atmel.com/dyn/products/datasheets.asp?family_id=682
Signed-off-by: Haavard Skinnemoen <haavard.skinnemoen@atmel.com>
Signed-off-by: Pierre Ossman <drzeus@drzeus.cx>
2008-06-30 10:35:03 -06:00
|
|
|
|
2014-06-05 15:14:38 -06:00
|
|
|
#include <asm/cacheflush.h>
|
atmel-mci: Driver for Atmel on-chip MMC controllers
This is a driver for the MMC controller on the AP7000 chips from
Atmel. It should in theory work on AT91 systems too with some
tweaking, but since the DMA interface is quite different, it's not
entirely clear if it's worth merging this with the at91_mci driver.
This driver has been around for a while in BSPs and kernel sources
provided by Atmel, but this particular version uses the generic DMA
Engine framework (with the slave extensions) instead of an
avr32-only DMA controller framework.
This driver can also use PIO transfers when no DMA channels are
available, and for transfers where using DMA may be difficult or
impractical for some reason (e.g. the DMA setup overhead is usually
not worth it for very short transfers, and badly aligned buffers or
lengths are difficult to handle.)
Currently, the driver only support PIO transfers. DMA support has been
split out to a separate patch to hopefully make it easier to review.
The driver has been tested using mmc-block and ext3fs on several SD,
SDHC and MMC+ cards. Reads and writes work fine, with read transfer
rates up to 3.5 MiB/s on fast cards with debugging disabled.
The driver has also been tested using the mmc_test module on the same
cards. All tests except 7, 9, 15 and 17 succeed. The first two are
unsupported by all the cards I have, so I don't know if the driver
handles this correctly. The last two fail because the hardware flags a
Data CRC Error instead of a Data Timeout error. I'm not sure how to deal
with that.
Documentation for this controller can be found in many data sheets from
Atmel, including the AT32AP7000 data sheet which can be found here:
http://www.atmel.com/dyn/products/datasheets.asp?family_id=682
Signed-off-by: Haavard Skinnemoen <haavard.skinnemoen@atmel.com>
Signed-off-by: Pierre Ossman <drzeus@drzeus.cx>
2008-06-30 10:35:03 -06:00
|
|
|
#include <asm/io.h>
|
|
|
|
#include <asm/unaligned.h>
|
|
|
|
|
2015-11-23 08:27:30 -07:00
|
|
|
/*
|
|
|
|
* Superset of MCI IP registers integrated in Atmel AVR32 and AT91 Processors
|
|
|
|
* Registers and bitfields marked with [2] are only available in MCI2
|
|
|
|
*/
|
|
|
|
|
|
|
|
/* MCI Register Definitions */
|
|
|
|
#define ATMCI_CR 0x0000 /* Control */
|
|
|
|
#define ATMCI_CR_MCIEN BIT(0) /* MCI Enable */
|
|
|
|
#define ATMCI_CR_MCIDIS BIT(1) /* MCI Disable */
|
|
|
|
#define ATMCI_CR_PWSEN BIT(2) /* Power Save Enable */
|
|
|
|
#define ATMCI_CR_PWSDIS BIT(3) /* Power Save Disable */
|
|
|
|
#define ATMCI_CR_SWRST BIT(7) /* Software Reset */
|
|
|
|
#define ATMCI_MR 0x0004 /* Mode */
|
|
|
|
#define ATMCI_MR_CLKDIV(x) ((x) << 0) /* Clock Divider */
|
|
|
|
#define ATMCI_MR_PWSDIV(x) ((x) << 8) /* Power Saving Divider */
|
|
|
|
#define ATMCI_MR_RDPROOF BIT(11) /* Read Proof */
|
|
|
|
#define ATMCI_MR_WRPROOF BIT(12) /* Write Proof */
|
|
|
|
#define ATMCI_MR_PDCFBYTE BIT(13) /* Force Byte Transfer */
|
|
|
|
#define ATMCI_MR_PDCPADV BIT(14) /* Padding Value */
|
|
|
|
#define ATMCI_MR_PDCMODE BIT(15) /* PDC-oriented Mode */
|
|
|
|
#define ATMCI_MR_CLKODD(x) ((x) << 16) /* LSB of Clock Divider */
|
|
|
|
#define ATMCI_DTOR 0x0008 /* Data Timeout */
|
|
|
|
#define ATMCI_DTOCYC(x) ((x) << 0) /* Data Timeout Cycles */
|
|
|
|
#define ATMCI_DTOMUL(x) ((x) << 4) /* Data Timeout Multiplier */
|
|
|
|
#define ATMCI_SDCR 0x000c /* SD Card / SDIO */
|
|
|
|
#define ATMCI_SDCSEL_SLOT_A (0 << 0) /* Select SD slot A */
|
|
|
|
#define ATMCI_SDCSEL_SLOT_B (1 << 0) /* Select SD slot A */
|
|
|
|
#define ATMCI_SDCSEL_MASK (3 << 0)
|
|
|
|
#define ATMCI_SDCBUS_1BIT (0 << 6) /* 1-bit data bus */
|
|
|
|
#define ATMCI_SDCBUS_4BIT (2 << 6) /* 4-bit data bus */
|
|
|
|
#define ATMCI_SDCBUS_8BIT (3 << 6) /* 8-bit data bus[2] */
|
|
|
|
#define ATMCI_SDCBUS_MASK (3 << 6)
|
|
|
|
#define ATMCI_ARGR 0x0010 /* Command Argument */
|
|
|
|
#define ATMCI_CMDR 0x0014 /* Command */
|
|
|
|
#define ATMCI_CMDR_CMDNB(x) ((x) << 0) /* Command Opcode */
|
|
|
|
#define ATMCI_CMDR_RSPTYP_NONE (0 << 6) /* No response */
|
|
|
|
#define ATMCI_CMDR_RSPTYP_48BIT (1 << 6) /* 48-bit response */
|
|
|
|
#define ATMCI_CMDR_RSPTYP_136BIT (2 << 6) /* 136-bit response */
|
|
|
|
#define ATMCI_CMDR_SPCMD_INIT (1 << 8) /* Initialization command */
|
|
|
|
#define ATMCI_CMDR_SPCMD_SYNC (2 << 8) /* Synchronized command */
|
|
|
|
#define ATMCI_CMDR_SPCMD_INT (4 << 8) /* Interrupt command */
|
|
|
|
#define ATMCI_CMDR_SPCMD_INTRESP (5 << 8) /* Interrupt response */
|
|
|
|
#define ATMCI_CMDR_OPDCMD (1 << 11) /* Open Drain */
|
|
|
|
#define ATMCI_CMDR_MAXLAT_5CYC (0 << 12) /* Max latency 5 cycles */
|
|
|
|
#define ATMCI_CMDR_MAXLAT_64CYC (1 << 12) /* Max latency 64 cycles */
|
|
|
|
#define ATMCI_CMDR_START_XFER (1 << 16) /* Start data transfer */
|
|
|
|
#define ATMCI_CMDR_STOP_XFER (2 << 16) /* Stop data transfer */
|
|
|
|
#define ATMCI_CMDR_TRDIR_WRITE (0 << 18) /* Write data */
|
|
|
|
#define ATMCI_CMDR_TRDIR_READ (1 << 18) /* Read data */
|
|
|
|
#define ATMCI_CMDR_BLOCK (0 << 19) /* Single-block transfer */
|
|
|
|
#define ATMCI_CMDR_MULTI_BLOCK (1 << 19) /* Multi-block transfer */
|
|
|
|
#define ATMCI_CMDR_STREAM (2 << 19) /* MMC Stream transfer */
|
|
|
|
#define ATMCI_CMDR_SDIO_BYTE (4 << 19) /* SDIO Byte transfer */
|
|
|
|
#define ATMCI_CMDR_SDIO_BLOCK (5 << 19) /* SDIO Block transfer */
|
|
|
|
#define ATMCI_CMDR_SDIO_SUSPEND (1 << 24) /* SDIO Suspend Command */
|
|
|
|
#define ATMCI_CMDR_SDIO_RESUME (2 << 24) /* SDIO Resume Command */
|
|
|
|
#define ATMCI_BLKR 0x0018 /* Block */
|
|
|
|
#define ATMCI_BCNT(x) ((x) << 0) /* Data Block Count */
|
|
|
|
#define ATMCI_BLKLEN(x) ((x) << 16) /* Data Block Length */
|
|
|
|
#define ATMCI_CSTOR 0x001c /* Completion Signal Timeout[2] */
|
|
|
|
#define ATMCI_CSTOCYC(x) ((x) << 0) /* CST cycles */
|
|
|
|
#define ATMCI_CSTOMUL(x) ((x) << 4) /* CST multiplier */
|
|
|
|
#define ATMCI_RSPR 0x0020 /* Response 0 */
|
|
|
|
#define ATMCI_RSPR1 0x0024 /* Response 1 */
|
|
|
|
#define ATMCI_RSPR2 0x0028 /* Response 2 */
|
|
|
|
#define ATMCI_RSPR3 0x002c /* Response 3 */
|
|
|
|
#define ATMCI_RDR 0x0030 /* Receive Data */
|
|
|
|
#define ATMCI_TDR 0x0034 /* Transmit Data */
|
|
|
|
#define ATMCI_SR 0x0040 /* Status */
|
|
|
|
#define ATMCI_IER 0x0044 /* Interrupt Enable */
|
|
|
|
#define ATMCI_IDR 0x0048 /* Interrupt Disable */
|
|
|
|
#define ATMCI_IMR 0x004c /* Interrupt Mask */
|
|
|
|
#define ATMCI_CMDRDY BIT(0) /* Command Ready */
|
|
|
|
#define ATMCI_RXRDY BIT(1) /* Receiver Ready */
|
|
|
|
#define ATMCI_TXRDY BIT(2) /* Transmitter Ready */
|
|
|
|
#define ATMCI_BLKE BIT(3) /* Data Block Ended */
|
|
|
|
#define ATMCI_DTIP BIT(4) /* Data Transfer In Progress */
|
|
|
|
#define ATMCI_NOTBUSY BIT(5) /* Data Not Busy */
|
|
|
|
#define ATMCI_ENDRX BIT(6) /* End of RX Buffer */
|
|
|
|
#define ATMCI_ENDTX BIT(7) /* End of TX Buffer */
|
|
|
|
#define ATMCI_SDIOIRQA BIT(8) /* SDIO IRQ in slot A */
|
|
|
|
#define ATMCI_SDIOIRQB BIT(9) /* SDIO IRQ in slot B */
|
|
|
|
#define ATMCI_SDIOWAIT BIT(12) /* SDIO Read Wait Operation Status */
|
|
|
|
#define ATMCI_CSRCV BIT(13) /* CE-ATA Completion Signal Received */
|
|
|
|
#define ATMCI_RXBUFF BIT(14) /* RX Buffer Full */
|
|
|
|
#define ATMCI_TXBUFE BIT(15) /* TX Buffer Empty */
|
|
|
|
#define ATMCI_RINDE BIT(16) /* Response Index Error */
|
|
|
|
#define ATMCI_RDIRE BIT(17) /* Response Direction Error */
|
|
|
|
#define ATMCI_RCRCE BIT(18) /* Response CRC Error */
|
|
|
|
#define ATMCI_RENDE BIT(19) /* Response End Bit Error */
|
|
|
|
#define ATMCI_RTOE BIT(20) /* Response Time-Out Error */
|
|
|
|
#define ATMCI_DCRCE BIT(21) /* Data CRC Error */
|
|
|
|
#define ATMCI_DTOE BIT(22) /* Data Time-Out Error */
|
|
|
|
#define ATMCI_CSTOE BIT(23) /* Completion Signal Time-out Error */
|
|
|
|
#define ATMCI_BLKOVRE BIT(24) /* DMA Block Overrun Error */
|
|
|
|
#define ATMCI_DMADONE BIT(25) /* DMA Transfer Done */
|
|
|
|
#define ATMCI_FIFOEMPTY BIT(26) /* FIFO Empty Flag */
|
|
|
|
#define ATMCI_XFRDONE BIT(27) /* Transfer Done Flag */
|
|
|
|
#define ATMCI_ACKRCV BIT(28) /* Boot Operation Acknowledge Received */
|
|
|
|
#define ATMCI_ACKRCVE BIT(29) /* Boot Operation Acknowledge Error */
|
|
|
|
#define ATMCI_OVRE BIT(30) /* RX Overrun Error */
|
|
|
|
#define ATMCI_UNRE BIT(31) /* TX Underrun Error */
|
|
|
|
#define ATMCI_DMA 0x0050 /* DMA Configuration[2] */
|
|
|
|
#define ATMCI_DMA_OFFSET(x) ((x) << 0) /* DMA Write Buffer Offset */
|
|
|
|
#define ATMCI_DMA_CHKSIZE(x) ((x) << 4) /* DMA Channel Read and Write Chunk Size */
|
|
|
|
#define ATMCI_DMAEN BIT(8) /* DMA Hardware Handshaking Enable */
|
|
|
|
#define ATMCI_CFG 0x0054 /* Configuration[2] */
|
|
|
|
#define ATMCI_CFG_FIFOMODE_1DATA BIT(0) /* MCI Internal FIFO control mode */
|
|
|
|
#define ATMCI_CFG_FERRCTRL_COR BIT(4) /* Flow Error flag reset control mode */
|
|
|
|
#define ATMCI_CFG_HSMODE BIT(8) /* High Speed Mode */
|
|
|
|
#define ATMCI_CFG_LSYNC BIT(12) /* Synchronize on the last block */
|
|
|
|
#define ATMCI_WPMR 0x00e4 /* Write Protection Mode[2] */
|
|
|
|
#define ATMCI_WP_EN BIT(0) /* WP Enable */
|
|
|
|
#define ATMCI_WP_KEY (0x4d4349 << 8) /* WP Key */
|
|
|
|
#define ATMCI_WPSR 0x00e8 /* Write Protection Status[2] */
|
|
|
|
#define ATMCI_GET_WP_VS(x) ((x) & 0x0f)
|
|
|
|
#define ATMCI_GET_WP_VSRC(x) (((x) >> 8) & 0xffff)
|
|
|
|
#define ATMCI_VERSION 0x00FC /* Version */
|
|
|
|
#define ATMCI_FIFO_APERTURE 0x0200 /* FIFO Aperture[2] */
|
|
|
|
|
|
|
|
/* This is not including the FIFO Aperture on MCI2 */
|
|
|
|
#define ATMCI_REGS_SIZE 0x100
|
|
|
|
|
|
|
|
/* Register access macros */
|
|
|
|
#define atmci_readl(port, reg) \
|
|
|
|
__raw_readl((port)->regs + reg)
|
|
|
|
#define atmci_writel(port, reg, value) \
|
|
|
|
__raw_writel((value), (port)->regs + reg)
|
|
|
|
|
|
|
|
/* On AVR chips the Peripheral DMA Controller is not connected to MCI. */
|
|
|
|
#ifdef CONFIG_AVR32
|
|
|
|
# define ATMCI_PDC_CONNECTED 0
|
|
|
|
#else
|
|
|
|
# define ATMCI_PDC_CONNECTED 1
|
|
|
|
#endif
|
|
|
|
|
2014-10-29 22:00:41 -06:00
|
|
|
#define AUTOSUSPEND_DELAY 50
|
|
|
|
|
2011-08-11 09:25:41 -06:00
|
|
|
#define ATMCI_DATA_ERROR_FLAGS (ATMCI_DCRCE | ATMCI_DTOE | ATMCI_OVRE | ATMCI_UNRE)
|
2008-07-30 12:29:03 -06:00
|
|
|
#define ATMCI_DMA_THRESHOLD 16
|
atmel-mci: Driver for Atmel on-chip MMC controllers
This is a driver for the MMC controller on the AP7000 chips from
Atmel. It should in theory work on AT91 systems too with some
tweaking, but since the DMA interface is quite different, it's not
entirely clear if it's worth merging this with the at91_mci driver.
This driver has been around for a while in BSPs and kernel sources
provided by Atmel, but this particular version uses the generic DMA
Engine framework (with the slave extensions) instead of an
avr32-only DMA controller framework.
This driver can also use PIO transfers when no DMA channels are
available, and for transfers where using DMA may be difficult or
impractical for some reason (e.g. the DMA setup overhead is usually
not worth it for very short transfers, and badly aligned buffers or
lengths are difficult to handle.)
Currently, the driver only support PIO transfers. DMA support has been
split out to a separate patch to hopefully make it easier to review.
The driver has been tested using mmc-block and ext3fs on several SD,
SDHC and MMC+ cards. Reads and writes work fine, with read transfer
rates up to 3.5 MiB/s on fast cards with debugging disabled.
The driver has also been tested using the mmc_test module on the same
cards. All tests except 7, 9, 15 and 17 succeed. The first two are
unsupported by all the cards I have, so I don't know if the driver
handles this correctly. The last two fail because the hardware flags a
Data CRC Error instead of a Data Timeout error. I'm not sure how to deal
with that.
Documentation for this controller can be found in many data sheets from
Atmel, including the AT32AP7000 data sheet which can be found here:
http://www.atmel.com/dyn/products/datasheets.asp?family_id=682
Signed-off-by: Haavard Skinnemoen <haavard.skinnemoen@atmel.com>
Signed-off-by: Pierre Ossman <drzeus@drzeus.cx>
2008-06-30 10:35:03 -06:00
|
|
|
|
|
|
|
enum {
|
2012-05-16 07:25:59 -06:00
|
|
|
EVENT_CMD_RDY = 0,
|
atmel-mci: Driver for Atmel on-chip MMC controllers
This is a driver for the MMC controller on the AP7000 chips from
Atmel. It should in theory work on AT91 systems too with some
tweaking, but since the DMA interface is quite different, it's not
entirely clear if it's worth merging this with the at91_mci driver.
This driver has been around for a while in BSPs and kernel sources
provided by Atmel, but this particular version uses the generic DMA
Engine framework (with the slave extensions) instead of an
avr32-only DMA controller framework.
This driver can also use PIO transfers when no DMA channels are
available, and for transfers where using DMA may be difficult or
impractical for some reason (e.g. the DMA setup overhead is usually
not worth it for very short transfers, and badly aligned buffers or
lengths are difficult to handle.)
Currently, the driver only support PIO transfers. DMA support has been
split out to a separate patch to hopefully make it easier to review.
The driver has been tested using mmc-block and ext3fs on several SD,
SDHC and MMC+ cards. Reads and writes work fine, with read transfer
rates up to 3.5 MiB/s on fast cards with debugging disabled.
The driver has also been tested using the mmc_test module on the same
cards. All tests except 7, 9, 15 and 17 succeed. The first two are
unsupported by all the cards I have, so I don't know if the driver
handles this correctly. The last two fail because the hardware flags a
Data CRC Error instead of a Data Timeout error. I'm not sure how to deal
with that.
Documentation for this controller can be found in many data sheets from
Atmel, including the AT32AP7000 data sheet which can be found here:
http://www.atmel.com/dyn/products/datasheets.asp?family_id=682
Signed-off-by: Haavard Skinnemoen <haavard.skinnemoen@atmel.com>
Signed-off-by: Pierre Ossman <drzeus@drzeus.cx>
2008-06-30 10:35:03 -06:00
|
|
|
EVENT_XFER_COMPLETE,
|
2012-05-16 07:25:59 -06:00
|
|
|
EVENT_NOTBUSY,
|
2008-07-31 06:49:16 -06:00
|
|
|
EVENT_DATA_ERROR,
|
|
|
|
};
|
|
|
|
|
|
|
|
enum atmel_mci_state {
|
atmel-mci: support multiple mmc slots
The Atmel MCI controller can drive multiple cards through separate sets
of pins, but only one at a time. This patch adds support for
multiplexing access to the controller so that multiple card slots can be
used as if they were hooked up to separate mmc controllers.
The atmel-mci driver registers each slot as a separate mmc_host. Both
access the same common controller state, but they also have some state
on their own for card detection/write protect handling, and separate
shadows of the MR and SDCR registers.
When one of the slots receives a request from the mmc core, the common
controller state is checked. If it's idle, the request is submitted
immediately. If not, the request is added to a queue. When a request is
done, the queue is checked and if there is a queued request, it is
submitted before the completion callback is called.
This patch also includes a few cleanups and fixes, including a locking
overhaul. I had to change the locking extensively in any case, so I
might as well try to get it right. The driver no longer takes any
irq-safe locks, which may or may not improve the overall system
performance.
This patch also adds a bit of documentation of the internal data
structures.
Signed-off-by: Haavard Skinnemoen <haavard.skinnemoen@atmel.com>
2008-09-17 12:53:55 -06:00
|
|
|
STATE_IDLE = 0,
|
|
|
|
STATE_SENDING_CMD,
|
2012-05-16 07:25:59 -06:00
|
|
|
STATE_DATA_XFER,
|
|
|
|
STATE_WAITING_NOTBUSY,
|
2008-07-31 06:49:16 -06:00
|
|
|
STATE_SENDING_STOP,
|
2012-05-16 07:25:59 -06:00
|
|
|
STATE_END_REQUEST,
|
atmel-mci: Driver for Atmel on-chip MMC controllers
This is a driver for the MMC controller on the AP7000 chips from
Atmel. It should in theory work on AT91 systems too with some
tweaking, but since the DMA interface is quite different, it's not
entirely clear if it's worth merging this with the at91_mci driver.
This driver has been around for a while in BSPs and kernel sources
provided by Atmel, but this particular version uses the generic DMA
Engine framework (with the slave extensions) instead of an
avr32-only DMA controller framework.
This driver can also use PIO transfers when no DMA channels are
available, and for transfers where using DMA may be difficult or
impractical for some reason (e.g. the DMA setup overhead is usually
not worth it for very short transfers, and badly aligned buffers or
lengths are difficult to handle.)
Currently, the driver only support PIO transfers. DMA support has been
split out to a separate patch to hopefully make it easier to review.
The driver has been tested using mmc-block and ext3fs on several SD,
SDHC and MMC+ cards. Reads and writes work fine, with read transfer
rates up to 3.5 MiB/s on fast cards with debugging disabled.
The driver has also been tested using the mmc_test module on the same
cards. All tests except 7, 9, 15 and 17 succeed. The first two are
unsupported by all the cards I have, so I don't know if the driver
handles this correctly. The last two fail because the hardware flags a
Data CRC Error instead of a Data Timeout error. I'm not sure how to deal
with that.
Documentation for this controller can be found in many data sheets from
Atmel, including the AT32AP7000 data sheet which can be found here:
http://www.atmel.com/dyn/products/datasheets.asp?family_id=682
Signed-off-by: Haavard Skinnemoen <haavard.skinnemoen@atmel.com>
Signed-off-by: Pierre Ossman <drzeus@drzeus.cx>
2008-06-30 10:35:03 -06:00
|
|
|
};
|
|
|
|
|
2011-08-11 09:25:44 -06:00
|
|
|
enum atmci_xfer_dir {
|
|
|
|
XFER_RECEIVE = 0,
|
|
|
|
XFER_TRANSMIT,
|
|
|
|
};
|
|
|
|
|
|
|
|
enum atmci_pdc_buf {
|
|
|
|
PDC_FIRST_BUF = 0,
|
|
|
|
PDC_SECOND_BUF,
|
|
|
|
};
|
|
|
|
|
|
|
|
struct atmel_mci_caps {
|
2012-08-30 10:34:38 -06:00
|
|
|
bool has_dma_conf_reg;
|
2011-08-11 09:25:44 -06:00
|
|
|
bool has_pdc;
|
|
|
|
bool has_cfg_reg;
|
|
|
|
bool has_cstor_reg;
|
|
|
|
bool has_highspeed;
|
|
|
|
bool has_rwproof;
|
2012-03-21 09:41:23 -06:00
|
|
|
bool has_odd_clk_div;
|
2012-05-16 07:26:00 -06:00
|
|
|
bool has_bad_data_ordering;
|
|
|
|
bool need_reset_after_xfer;
|
|
|
|
bool need_blksz_mul_4;
|
2012-07-24 03:42:04 -06:00
|
|
|
bool need_notbusy_for_read_ops;
|
2011-08-11 09:25:44 -06:00
|
|
|
};
|
|
|
|
|
2008-07-30 12:29:03 -06:00
|
|
|
struct atmel_mci_dma {
|
|
|
|
struct dma_chan *chan;
|
|
|
|
struct dma_async_tx_descriptor *data_desc;
|
|
|
|
};
|
|
|
|
|
atmel-mci: support multiple mmc slots
The Atmel MCI controller can drive multiple cards through separate sets
of pins, but only one at a time. This patch adds support for
multiplexing access to the controller so that multiple card slots can be
used as if they were hooked up to separate mmc controllers.
The atmel-mci driver registers each slot as a separate mmc_host. Both
access the same common controller state, but they also have some state
on their own for card detection/write protect handling, and separate
shadows of the MR and SDCR registers.
When one of the slots receives a request from the mmc core, the common
controller state is checked. If it's idle, the request is submitted
immediately. If not, the request is added to a queue. When a request is
done, the queue is checked and if there is a queued request, it is
submitted before the completion callback is called.
This patch also includes a few cleanups and fixes, including a locking
overhaul. I had to change the locking extensively in any case, so I
might as well try to get it right. The driver no longer takes any
irq-safe locks, which may or may not improve the overall system
performance.
This patch also adds a bit of documentation of the internal data
structures.
Signed-off-by: Haavard Skinnemoen <haavard.skinnemoen@atmel.com>
2008-09-17 12:53:55 -06:00
|
|
|
/**
|
|
|
|
* struct atmel_mci - MMC controller state shared between all slots
|
|
|
|
* @lock: Spinlock protecting the queue and associated data.
|
|
|
|
* @regs: Pointer to MMIO registers.
|
2011-08-11 09:25:44 -06:00
|
|
|
* @sg: Scatterlist entry currently being processed by PIO or PDC code.
|
atmel-mci: support multiple mmc slots
The Atmel MCI controller can drive multiple cards through separate sets
of pins, but only one at a time. This patch adds support for
multiplexing access to the controller so that multiple card slots can be
used as if they were hooked up to separate mmc controllers.
The atmel-mci driver registers each slot as a separate mmc_host. Both
access the same common controller state, but they also have some state
on their own for card detection/write protect handling, and separate
shadows of the MR and SDCR registers.
When one of the slots receives a request from the mmc core, the common
controller state is checked. If it's idle, the request is submitted
immediately. If not, the request is added to a queue. When a request is
done, the queue is checked and if there is a queued request, it is
submitted before the completion callback is called.
This patch also includes a few cleanups and fixes, including a locking
overhaul. I had to change the locking extensively in any case, so I
might as well try to get it right. The driver no longer takes any
irq-safe locks, which may or may not improve the overall system
performance.
This patch also adds a bit of documentation of the internal data
structures.
Signed-off-by: Haavard Skinnemoen <haavard.skinnemoen@atmel.com>
2008-09-17 12:53:55 -06:00
|
|
|
* @pio_offset: Offset into the current scatterlist entry.
|
2012-05-16 07:25:58 -06:00
|
|
|
* @buffer: Buffer used if we don't have the r/w proof capability. We
|
|
|
|
* don't have the time to switch pdc buffers so we have to use only
|
|
|
|
* one buffer for the full transaction.
|
|
|
|
* @buf_size: size of the buffer.
|
|
|
|
* @phys_buf_addr: buffer address needed for pdc.
|
atmel-mci: support multiple mmc slots
The Atmel MCI controller can drive multiple cards through separate sets
of pins, but only one at a time. This patch adds support for
multiplexing access to the controller so that multiple card slots can be
used as if they were hooked up to separate mmc controllers.
The atmel-mci driver registers each slot as a separate mmc_host. Both
access the same common controller state, but they also have some state
on their own for card detection/write protect handling, and separate
shadows of the MR and SDCR registers.
When one of the slots receives a request from the mmc core, the common
controller state is checked. If it's idle, the request is submitted
immediately. If not, the request is added to a queue. When a request is
done, the queue is checked and if there is a queued request, it is
submitted before the completion callback is called.
This patch also includes a few cleanups and fixes, including a locking
overhaul. I had to change the locking extensively in any case, so I
might as well try to get it right. The driver no longer takes any
irq-safe locks, which may or may not improve the overall system
performance.
This patch also adds a bit of documentation of the internal data
structures.
Signed-off-by: Haavard Skinnemoen <haavard.skinnemoen@atmel.com>
2008-09-17 12:53:55 -06:00
|
|
|
* @cur_slot: The slot which is currently using the controller.
|
|
|
|
* @mrq: The request currently being processed on @cur_slot,
|
|
|
|
* or NULL if the controller is idle.
|
|
|
|
* @cmd: The command currently being sent to the card, or NULL.
|
|
|
|
* @data: The data currently being transferred, or NULL if no data
|
|
|
|
* transfer is in progress.
|
2011-08-11 09:25:44 -06:00
|
|
|
* @data_size: just data->blocks * data->blksz.
|
2008-07-30 12:29:03 -06:00
|
|
|
* @dma: DMA client state.
|
|
|
|
* @data_chan: DMA channel being used for the current data transfer.
|
atmel-mci: support multiple mmc slots
The Atmel MCI controller can drive multiple cards through separate sets
of pins, but only one at a time. This patch adds support for
multiplexing access to the controller so that multiple card slots can be
used as if they were hooked up to separate mmc controllers.
The atmel-mci driver registers each slot as a separate mmc_host. Both
access the same common controller state, but they also have some state
on their own for card detection/write protect handling, and separate
shadows of the MR and SDCR registers.
When one of the slots receives a request from the mmc core, the common
controller state is checked. If it's idle, the request is submitted
immediately. If not, the request is added to a queue. When a request is
done, the queue is checked and if there is a queued request, it is
submitted before the completion callback is called.
This patch also includes a few cleanups and fixes, including a locking
overhaul. I had to change the locking extensively in any case, so I
might as well try to get it right. The driver no longer takes any
irq-safe locks, which may or may not improve the overall system
performance.
This patch also adds a bit of documentation of the internal data
structures.
Signed-off-by: Haavard Skinnemoen <haavard.skinnemoen@atmel.com>
2008-09-17 12:53:55 -06:00
|
|
|
* @cmd_status: Snapshot of SR taken upon completion of the current
|
|
|
|
* command. Only valid when EVENT_CMD_COMPLETE is pending.
|
|
|
|
* @data_status: Snapshot of SR taken upon completion of the current
|
|
|
|
* data transfer. Only valid when EVENT_DATA_COMPLETE or
|
|
|
|
* EVENT_DATA_ERROR is pending.
|
|
|
|
* @stop_cmdr: Value to be loaded into CMDR when the stop command is
|
|
|
|
* to be sent.
|
|
|
|
* @tasklet: Tasklet running the request state machine.
|
|
|
|
* @pending_events: Bitmask of events flagged by the interrupt handler
|
|
|
|
* to be processed by the tasklet.
|
|
|
|
* @completed_events: Bitmask of events which the state machine has
|
|
|
|
* processed.
|
|
|
|
* @state: Tasklet state.
|
|
|
|
* @queue: List of slots waiting for access to the controller.
|
|
|
|
* @need_clock_update: Update the clock rate before the next request.
|
|
|
|
* @need_reset: Reset controller before next request.
|
2012-05-16 07:26:00 -06:00
|
|
|
* @timer: Timer to balance the data timeout error flag which cannot rise.
|
atmel-mci: support multiple mmc slots
The Atmel MCI controller can drive multiple cards through separate sets
of pins, but only one at a time. This patch adds support for
multiplexing access to the controller so that multiple card slots can be
used as if they were hooked up to separate mmc controllers.
The atmel-mci driver registers each slot as a separate mmc_host. Both
access the same common controller state, but they also have some state
on their own for card detection/write protect handling, and separate
shadows of the MR and SDCR registers.
When one of the slots receives a request from the mmc core, the common
controller state is checked. If it's idle, the request is submitted
immediately. If not, the request is added to a queue. When a request is
done, the queue is checked and if there is a queued request, it is
submitted before the completion callback is called.
This patch also includes a few cleanups and fixes, including a locking
overhaul. I had to change the locking extensively in any case, so I
might as well try to get it right. The driver no longer takes any
irq-safe locks, which may or may not improve the overall system
performance.
This patch also adds a bit of documentation of the internal data
structures.
Signed-off-by: Haavard Skinnemoen <haavard.skinnemoen@atmel.com>
2008-09-17 12:53:55 -06:00
|
|
|
* @mode_reg: Value of the MR register.
|
2009-12-14 19:01:31 -07:00
|
|
|
* @cfg_reg: Value of the CFG register.
|
atmel-mci: support multiple mmc slots
The Atmel MCI controller can drive multiple cards through separate sets
of pins, but only one at a time. This patch adds support for
multiplexing access to the controller so that multiple card slots can be
used as if they were hooked up to separate mmc controllers.
The atmel-mci driver registers each slot as a separate mmc_host. Both
access the same common controller state, but they also have some state
on their own for card detection/write protect handling, and separate
shadows of the MR and SDCR registers.
When one of the slots receives a request from the mmc core, the common
controller state is checked. If it's idle, the request is submitted
immediately. If not, the request is added to a queue. When a request is
done, the queue is checked and if there is a queued request, it is
submitted before the completion callback is called.
This patch also includes a few cleanups and fixes, including a locking
overhaul. I had to change the locking extensively in any case, so I
might as well try to get it right. The driver no longer takes any
irq-safe locks, which may or may not improve the overall system
performance.
This patch also adds a bit of documentation of the internal data
structures.
Signed-off-by: Haavard Skinnemoen <haavard.skinnemoen@atmel.com>
2008-09-17 12:53:55 -06:00
|
|
|
* @bus_hz: The rate of @mck in Hz. This forms the basis for MMC bus
|
|
|
|
* rate and timeout calculations.
|
|
|
|
* @mapbase: Physical address of the MMIO registers.
|
|
|
|
* @mck: The peripheral bus clock hooked up to the MMC controller.
|
|
|
|
* @pdev: Platform device associated with the MMC controller.
|
|
|
|
* @slot: Slots sharing this MMC controller.
|
2011-08-11 09:25:44 -06:00
|
|
|
* @caps: MCI capabilities depending on MCI version.
|
|
|
|
* @prepare_data: function to setup MCI before data transfer which
|
|
|
|
* depends on MCI capabilities.
|
|
|
|
* @submit_data: function to start data transfer which depends on MCI
|
|
|
|
* capabilities.
|
|
|
|
* @stop_transfer: function to stop data transfer which depends on MCI
|
|
|
|
* capabilities.
|
atmel-mci: support multiple mmc slots
The Atmel MCI controller can drive multiple cards through separate sets
of pins, but only one at a time. This patch adds support for
multiplexing access to the controller so that multiple card slots can be
used as if they were hooked up to separate mmc controllers.
The atmel-mci driver registers each slot as a separate mmc_host. Both
access the same common controller state, but they also have some state
on their own for card detection/write protect handling, and separate
shadows of the MR and SDCR registers.
When one of the slots receives a request from the mmc core, the common
controller state is checked. If it's idle, the request is submitted
immediately. If not, the request is added to a queue. When a request is
done, the queue is checked and if there is a queued request, it is
submitted before the completion callback is called.
This patch also includes a few cleanups and fixes, including a locking
overhaul. I had to change the locking extensively in any case, so I
might as well try to get it right. The driver no longer takes any
irq-safe locks, which may or may not improve the overall system
performance.
This patch also adds a bit of documentation of the internal data
structures.
Signed-off-by: Haavard Skinnemoen <haavard.skinnemoen@atmel.com>
2008-09-17 12:53:55 -06:00
|
|
|
*
|
|
|
|
* Locking
|
|
|
|
* =======
|
|
|
|
*
|
|
|
|
* @lock is a softirq-safe spinlock protecting @queue as well as
|
|
|
|
* @cur_slot, @mrq and @state. These must always be updated
|
|
|
|
* at the same time while holding @lock.
|
|
|
|
*
|
|
|
|
* @lock also protects mode_reg and need_clock_update since these are
|
|
|
|
* used to synchronize mode register updates with the queue
|
|
|
|
* processing.
|
|
|
|
*
|
|
|
|
* The @mrq field of struct atmel_mci_slot is also protected by @lock,
|
|
|
|
* and must always be written at the same time as the slot is added to
|
|
|
|
* @queue.
|
|
|
|
*
|
|
|
|
* @pending_events and @completed_events are accessed using atomic bit
|
|
|
|
* operations, so they don't need any locking.
|
|
|
|
*
|
|
|
|
* None of the fields touched by the interrupt handler need any
|
|
|
|
* locking. However, ordering is important: Before EVENT_DATA_ERROR or
|
|
|
|
* EVENT_DATA_COMPLETE is set in @pending_events, all data-related
|
|
|
|
* interrupts must be disabled and @data_status updated with a
|
|
|
|
* snapshot of SR. Similarly, before EVENT_CMD_COMPLETE is set, the
|
2011-03-30 19:57:33 -06:00
|
|
|
* CMDRDY interrupt must be disabled and @cmd_status updated with a
|
atmel-mci: support multiple mmc slots
The Atmel MCI controller can drive multiple cards through separate sets
of pins, but only one at a time. This patch adds support for
multiplexing access to the controller so that multiple card slots can be
used as if they were hooked up to separate mmc controllers.
The atmel-mci driver registers each slot as a separate mmc_host. Both
access the same common controller state, but they also have some state
on their own for card detection/write protect handling, and separate
shadows of the MR and SDCR registers.
When one of the slots receives a request from the mmc core, the common
controller state is checked. If it's idle, the request is submitted
immediately. If not, the request is added to a queue. When a request is
done, the queue is checked and if there is a queued request, it is
submitted before the completion callback is called.
This patch also includes a few cleanups and fixes, including a locking
overhaul. I had to change the locking extensively in any case, so I
might as well try to get it right. The driver no longer takes any
irq-safe locks, which may or may not improve the overall system
performance.
This patch also adds a bit of documentation of the internal data
structures.
Signed-off-by: Haavard Skinnemoen <haavard.skinnemoen@atmel.com>
2008-09-17 12:53:55 -06:00
|
|
|
* snapshot of SR, and before EVENT_XFER_COMPLETE can be set, the
|
|
|
|
* bytes_xfered field of @data must be written. This is ensured by
|
|
|
|
* using barriers.
|
|
|
|
*/
|
atmel-mci: Driver for Atmel on-chip MMC controllers
This is a driver for the MMC controller on the AP7000 chips from
Atmel. It should in theory work on AT91 systems too with some
tweaking, but since the DMA interface is quite different, it's not
entirely clear if it's worth merging this with the at91_mci driver.
This driver has been around for a while in BSPs and kernel sources
provided by Atmel, but this particular version uses the generic DMA
Engine framework (with the slave extensions) instead of an
avr32-only DMA controller framework.
This driver can also use PIO transfers when no DMA channels are
available, and for transfers where using DMA may be difficult or
impractical for some reason (e.g. the DMA setup overhead is usually
not worth it for very short transfers, and badly aligned buffers or
lengths are difficult to handle.)
Currently, the driver only support PIO transfers. DMA support has been
split out to a separate patch to hopefully make it easier to review.
The driver has been tested using mmc-block and ext3fs on several SD,
SDHC and MMC+ cards. Reads and writes work fine, with read transfer
rates up to 3.5 MiB/s on fast cards with debugging disabled.
The driver has also been tested using the mmc_test module on the same
cards. All tests except 7, 9, 15 and 17 succeed. The first two are
unsupported by all the cards I have, so I don't know if the driver
handles this correctly. The last two fail because the hardware flags a
Data CRC Error instead of a Data Timeout error. I'm not sure how to deal
with that.
Documentation for this controller can be found in many data sheets from
Atmel, including the AT32AP7000 data sheet which can be found here:
http://www.atmel.com/dyn/products/datasheets.asp?family_id=682
Signed-off-by: Haavard Skinnemoen <haavard.skinnemoen@atmel.com>
Signed-off-by: Pierre Ossman <drzeus@drzeus.cx>
2008-06-30 10:35:03 -06:00
|
|
|
struct atmel_mci {
|
atmel-mci: support multiple mmc slots
The Atmel MCI controller can drive multiple cards through separate sets
of pins, but only one at a time. This patch adds support for
multiplexing access to the controller so that multiple card slots can be
used as if they were hooked up to separate mmc controllers.
The atmel-mci driver registers each slot as a separate mmc_host. Both
access the same common controller state, but they also have some state
on their own for card detection/write protect handling, and separate
shadows of the MR and SDCR registers.
When one of the slots receives a request from the mmc core, the common
controller state is checked. If it's idle, the request is submitted
immediately. If not, the request is added to a queue. When a request is
done, the queue is checked and if there is a queued request, it is
submitted before the completion callback is called.
This patch also includes a few cleanups and fixes, including a locking
overhaul. I had to change the locking extensively in any case, so I
might as well try to get it right. The driver no longer takes any
irq-safe locks, which may or may not improve the overall system
performance.
This patch also adds a bit of documentation of the internal data
structures.
Signed-off-by: Haavard Skinnemoen <haavard.skinnemoen@atmel.com>
2008-09-17 12:53:55 -06:00
|
|
|
spinlock_t lock;
|
atmel-mci: Driver for Atmel on-chip MMC controllers
This is a driver for the MMC controller on the AP7000 chips from
Atmel. It should in theory work on AT91 systems too with some
tweaking, but since the DMA interface is quite different, it's not
entirely clear if it's worth merging this with the at91_mci driver.
This driver has been around for a while in BSPs and kernel sources
provided by Atmel, but this particular version uses the generic DMA
Engine framework (with the slave extensions) instead of an
avr32-only DMA controller framework.
This driver can also use PIO transfers when no DMA channels are
available, and for transfers where using DMA may be difficult or
impractical for some reason (e.g. the DMA setup overhead is usually
not worth it for very short transfers, and badly aligned buffers or
lengths are difficult to handle.)
Currently, the driver only support PIO transfers. DMA support has been
split out to a separate patch to hopefully make it easier to review.
The driver has been tested using mmc-block and ext3fs on several SD,
SDHC and MMC+ cards. Reads and writes work fine, with read transfer
rates up to 3.5 MiB/s on fast cards with debugging disabled.
The driver has also been tested using the mmc_test module on the same
cards. All tests except 7, 9, 15 and 17 succeed. The first two are
unsupported by all the cards I have, so I don't know if the driver
handles this correctly. The last two fail because the hardware flags a
Data CRC Error instead of a Data Timeout error. I'm not sure how to deal
with that.
Documentation for this controller can be found in many data sheets from
Atmel, including the AT32AP7000 data sheet which can be found here:
http://www.atmel.com/dyn/products/datasheets.asp?family_id=682
Signed-off-by: Haavard Skinnemoen <haavard.skinnemoen@atmel.com>
Signed-off-by: Pierre Ossman <drzeus@drzeus.cx>
2008-06-30 10:35:03 -06:00
|
|
|
void __iomem *regs;
|
|
|
|
|
|
|
|
struct scatterlist *sg;
|
2013-04-08 10:05:47 -06:00
|
|
|
unsigned int sg_len;
|
atmel-mci: Driver for Atmel on-chip MMC controllers
This is a driver for the MMC controller on the AP7000 chips from
Atmel. It should in theory work on AT91 systems too with some
tweaking, but since the DMA interface is quite different, it's not
entirely clear if it's worth merging this with the at91_mci driver.
This driver has been around for a while in BSPs and kernel sources
provided by Atmel, but this particular version uses the generic DMA
Engine framework (with the slave extensions) instead of an
avr32-only DMA controller framework.
This driver can also use PIO transfers when no DMA channels are
available, and for transfers where using DMA may be difficult or
impractical for some reason (e.g. the DMA setup overhead is usually
not worth it for very short transfers, and badly aligned buffers or
lengths are difficult to handle.)
Currently, the driver only support PIO transfers. DMA support has been
split out to a separate patch to hopefully make it easier to review.
The driver has been tested using mmc-block and ext3fs on several SD,
SDHC and MMC+ cards. Reads and writes work fine, with read transfer
rates up to 3.5 MiB/s on fast cards with debugging disabled.
The driver has also been tested using the mmc_test module on the same
cards. All tests except 7, 9, 15 and 17 succeed. The first two are
unsupported by all the cards I have, so I don't know if the driver
handles this correctly. The last two fail because the hardware flags a
Data CRC Error instead of a Data Timeout error. I'm not sure how to deal
with that.
Documentation for this controller can be found in many data sheets from
Atmel, including the AT32AP7000 data sheet which can be found here:
http://www.atmel.com/dyn/products/datasheets.asp?family_id=682
Signed-off-by: Haavard Skinnemoen <haavard.skinnemoen@atmel.com>
Signed-off-by: Pierre Ossman <drzeus@drzeus.cx>
2008-06-30 10:35:03 -06:00
|
|
|
unsigned int pio_offset;
|
2012-05-16 07:25:58 -06:00
|
|
|
unsigned int *buffer;
|
|
|
|
unsigned int buf_size;
|
|
|
|
dma_addr_t buf_phys_addr;
|
atmel-mci: Driver for Atmel on-chip MMC controllers
This is a driver for the MMC controller on the AP7000 chips from
Atmel. It should in theory work on AT91 systems too with some
tweaking, but since the DMA interface is quite different, it's not
entirely clear if it's worth merging this with the at91_mci driver.
This driver has been around for a while in BSPs and kernel sources
provided by Atmel, but this particular version uses the generic DMA
Engine framework (with the slave extensions) instead of an
avr32-only DMA controller framework.
This driver can also use PIO transfers when no DMA channels are
available, and for transfers where using DMA may be difficult or
impractical for some reason (e.g. the DMA setup overhead is usually
not worth it for very short transfers, and badly aligned buffers or
lengths are difficult to handle.)
Currently, the driver only support PIO transfers. DMA support has been
split out to a separate patch to hopefully make it easier to review.
The driver has been tested using mmc-block and ext3fs on several SD,
SDHC and MMC+ cards. Reads and writes work fine, with read transfer
rates up to 3.5 MiB/s on fast cards with debugging disabled.
The driver has also been tested using the mmc_test module on the same
cards. All tests except 7, 9, 15 and 17 succeed. The first two are
unsupported by all the cards I have, so I don't know if the driver
handles this correctly. The last two fail because the hardware flags a
Data CRC Error instead of a Data Timeout error. I'm not sure how to deal
with that.
Documentation for this controller can be found in many data sheets from
Atmel, including the AT32AP7000 data sheet which can be found here:
http://www.atmel.com/dyn/products/datasheets.asp?family_id=682
Signed-off-by: Haavard Skinnemoen <haavard.skinnemoen@atmel.com>
Signed-off-by: Pierre Ossman <drzeus@drzeus.cx>
2008-06-30 10:35:03 -06:00
|
|
|
|
atmel-mci: support multiple mmc slots
The Atmel MCI controller can drive multiple cards through separate sets
of pins, but only one at a time. This patch adds support for
multiplexing access to the controller so that multiple card slots can be
used as if they were hooked up to separate mmc controllers.
The atmel-mci driver registers each slot as a separate mmc_host. Both
access the same common controller state, but they also have some state
on their own for card detection/write protect handling, and separate
shadows of the MR and SDCR registers.
When one of the slots receives a request from the mmc core, the common
controller state is checked. If it's idle, the request is submitted
immediately. If not, the request is added to a queue. When a request is
done, the queue is checked and if there is a queued request, it is
submitted before the completion callback is called.
This patch also includes a few cleanups and fixes, including a locking
overhaul. I had to change the locking extensively in any case, so I
might as well try to get it right. The driver no longer takes any
irq-safe locks, which may or may not improve the overall system
performance.
This patch also adds a bit of documentation of the internal data
structures.
Signed-off-by: Haavard Skinnemoen <haavard.skinnemoen@atmel.com>
2008-09-17 12:53:55 -06:00
|
|
|
struct atmel_mci_slot *cur_slot;
|
atmel-mci: Driver for Atmel on-chip MMC controllers
This is a driver for the MMC controller on the AP7000 chips from
Atmel. It should in theory work on AT91 systems too with some
tweaking, but since the DMA interface is quite different, it's not
entirely clear if it's worth merging this with the at91_mci driver.
This driver has been around for a while in BSPs and kernel sources
provided by Atmel, but this particular version uses the generic DMA
Engine framework (with the slave extensions) instead of an
avr32-only DMA controller framework.
This driver can also use PIO transfers when no DMA channels are
available, and for transfers where using DMA may be difficult or
impractical for some reason (e.g. the DMA setup overhead is usually
not worth it for very short transfers, and badly aligned buffers or
lengths are difficult to handle.)
Currently, the driver only support PIO transfers. DMA support has been
split out to a separate patch to hopefully make it easier to review.
The driver has been tested using mmc-block and ext3fs on several SD,
SDHC and MMC+ cards. Reads and writes work fine, with read transfer
rates up to 3.5 MiB/s on fast cards with debugging disabled.
The driver has also been tested using the mmc_test module on the same
cards. All tests except 7, 9, 15 and 17 succeed. The first two are
unsupported by all the cards I have, so I don't know if the driver
handles this correctly. The last two fail because the hardware flags a
Data CRC Error instead of a Data Timeout error. I'm not sure how to deal
with that.
Documentation for this controller can be found in many data sheets from
Atmel, including the AT32AP7000 data sheet which can be found here:
http://www.atmel.com/dyn/products/datasheets.asp?family_id=682
Signed-off-by: Haavard Skinnemoen <haavard.skinnemoen@atmel.com>
Signed-off-by: Pierre Ossman <drzeus@drzeus.cx>
2008-06-30 10:35:03 -06:00
|
|
|
struct mmc_request *mrq;
|
|
|
|
struct mmc_command *cmd;
|
|
|
|
struct mmc_data *data;
|
2011-08-11 09:25:44 -06:00
|
|
|
unsigned int data_size;
|
atmel-mci: Driver for Atmel on-chip MMC controllers
This is a driver for the MMC controller on the AP7000 chips from
Atmel. It should in theory work on AT91 systems too with some
tweaking, but since the DMA interface is quite different, it's not
entirely clear if it's worth merging this with the at91_mci driver.
This driver has been around for a while in BSPs and kernel sources
provided by Atmel, but this particular version uses the generic DMA
Engine framework (with the slave extensions) instead of an
avr32-only DMA controller framework.
This driver can also use PIO transfers when no DMA channels are
available, and for transfers where using DMA may be difficult or
impractical for some reason (e.g. the DMA setup overhead is usually
not worth it for very short transfers, and badly aligned buffers or
lengths are difficult to handle.)
Currently, the driver only support PIO transfers. DMA support has been
split out to a separate patch to hopefully make it easier to review.
The driver has been tested using mmc-block and ext3fs on several SD,
SDHC and MMC+ cards. Reads and writes work fine, with read transfer
rates up to 3.5 MiB/s on fast cards with debugging disabled.
The driver has also been tested using the mmc_test module on the same
cards. All tests except 7, 9, 15 and 17 succeed. The first two are
unsupported by all the cards I have, so I don't know if the driver
handles this correctly. The last two fail because the hardware flags a
Data CRC Error instead of a Data Timeout error. I'm not sure how to deal
with that.
Documentation for this controller can be found in many data sheets from
Atmel, including the AT32AP7000 data sheet which can be found here:
http://www.atmel.com/dyn/products/datasheets.asp?family_id=682
Signed-off-by: Haavard Skinnemoen <haavard.skinnemoen@atmel.com>
Signed-off-by: Pierre Ossman <drzeus@drzeus.cx>
2008-06-30 10:35:03 -06:00
|
|
|
|
2008-07-30 12:29:03 -06:00
|
|
|
struct atmel_mci_dma dma;
|
|
|
|
struct dma_chan *data_chan;
|
2012-02-01 03:42:27 -07:00
|
|
|
struct dma_slave_config dma_conf;
|
2008-07-30 12:29:03 -06:00
|
|
|
|
atmel-mci: Driver for Atmel on-chip MMC controllers
This is a driver for the MMC controller on the AP7000 chips from
Atmel. It should in theory work on AT91 systems too with some
tweaking, but since the DMA interface is quite different, it's not
entirely clear if it's worth merging this with the at91_mci driver.
This driver has been around for a while in BSPs and kernel sources
provided by Atmel, but this particular version uses the generic DMA
Engine framework (with the slave extensions) instead of an
avr32-only DMA controller framework.
This driver can also use PIO transfers when no DMA channels are
available, and for transfers where using DMA may be difficult or
impractical for some reason (e.g. the DMA setup overhead is usually
not worth it for very short transfers, and badly aligned buffers or
lengths are difficult to handle.)
Currently, the driver only support PIO transfers. DMA support has been
split out to a separate patch to hopefully make it easier to review.
The driver has been tested using mmc-block and ext3fs on several SD,
SDHC and MMC+ cards. Reads and writes work fine, with read transfer
rates up to 3.5 MiB/s on fast cards with debugging disabled.
The driver has also been tested using the mmc_test module on the same
cards. All tests except 7, 9, 15 and 17 succeed. The first two are
unsupported by all the cards I have, so I don't know if the driver
handles this correctly. The last two fail because the hardware flags a
Data CRC Error instead of a Data Timeout error. I'm not sure how to deal
with that.
Documentation for this controller can be found in many data sheets from
Atmel, including the AT32AP7000 data sheet which can be found here:
http://www.atmel.com/dyn/products/datasheets.asp?family_id=682
Signed-off-by: Haavard Skinnemoen <haavard.skinnemoen@atmel.com>
Signed-off-by: Pierre Ossman <drzeus@drzeus.cx>
2008-06-30 10:35:03 -06:00
|
|
|
u32 cmd_status;
|
|
|
|
u32 data_status;
|
|
|
|
u32 stop_cmdr;
|
|
|
|
|
|
|
|
struct tasklet_struct tasklet;
|
|
|
|
unsigned long pending_events;
|
|
|
|
unsigned long completed_events;
|
2008-07-31 06:49:16 -06:00
|
|
|
enum atmel_mci_state state;
|
atmel-mci: support multiple mmc slots
The Atmel MCI controller can drive multiple cards through separate sets
of pins, but only one at a time. This patch adds support for
multiplexing access to the controller so that multiple card slots can be
used as if they were hooked up to separate mmc controllers.
The atmel-mci driver registers each slot as a separate mmc_host. Both
access the same common controller state, but they also have some state
on their own for card detection/write protect handling, and separate
shadows of the MR and SDCR registers.
When one of the slots receives a request from the mmc core, the common
controller state is checked. If it's idle, the request is submitted
immediately. If not, the request is added to a queue. When a request is
done, the queue is checked and if there is a queued request, it is
submitted before the completion callback is called.
This patch also includes a few cleanups and fixes, including a locking
overhaul. I had to change the locking extensively in any case, so I
might as well try to get it right. The driver no longer takes any
irq-safe locks, which may or may not improve the overall system
performance.
This patch also adds a bit of documentation of the internal data
structures.
Signed-off-by: Haavard Skinnemoen <haavard.skinnemoen@atmel.com>
2008-09-17 12:53:55 -06:00
|
|
|
struct list_head queue;
|
atmel-mci: Driver for Atmel on-chip MMC controllers
This is a driver for the MMC controller on the AP7000 chips from
Atmel. It should in theory work on AT91 systems too with some
tweaking, but since the DMA interface is quite different, it's not
entirely clear if it's worth merging this with the at91_mci driver.
This driver has been around for a while in BSPs and kernel sources
provided by Atmel, but this particular version uses the generic DMA
Engine framework (with the slave extensions) instead of an
avr32-only DMA controller framework.
This driver can also use PIO transfers when no DMA channels are
available, and for transfers where using DMA may be difficult or
impractical for some reason (e.g. the DMA setup overhead is usually
not worth it for very short transfers, and badly aligned buffers or
lengths are difficult to handle.)
Currently, the driver only support PIO transfers. DMA support has been
split out to a separate patch to hopefully make it easier to review.
The driver has been tested using mmc-block and ext3fs on several SD,
SDHC and MMC+ cards. Reads and writes work fine, with read transfer
rates up to 3.5 MiB/s on fast cards with debugging disabled.
The driver has also been tested using the mmc_test module on the same
cards. All tests except 7, 9, 15 and 17 succeed. The first two are
unsupported by all the cards I have, so I don't know if the driver
handles this correctly. The last two fail because the hardware flags a
Data CRC Error instead of a Data Timeout error. I'm not sure how to deal
with that.
Documentation for this controller can be found in many data sheets from
Atmel, including the AT32AP7000 data sheet which can be found here:
http://www.atmel.com/dyn/products/datasheets.asp?family_id=682
Signed-off-by: Haavard Skinnemoen <haavard.skinnemoen@atmel.com>
Signed-off-by: Pierre Ossman <drzeus@drzeus.cx>
2008-06-30 10:35:03 -06:00
|
|
|
|
atmel-mci: support multiple mmc slots
The Atmel MCI controller can drive multiple cards through separate sets
of pins, but only one at a time. This patch adds support for
multiplexing access to the controller so that multiple card slots can be
used as if they were hooked up to separate mmc controllers.
The atmel-mci driver registers each slot as a separate mmc_host. Both
access the same common controller state, but they also have some state
on their own for card detection/write protect handling, and separate
shadows of the MR and SDCR registers.
When one of the slots receives a request from the mmc core, the common
controller state is checked. If it's idle, the request is submitted
immediately. If not, the request is added to a queue. When a request is
done, the queue is checked and if there is a queued request, it is
submitted before the completion callback is called.
This patch also includes a few cleanups and fixes, including a locking
overhaul. I had to change the locking extensively in any case, so I
might as well try to get it right. The driver no longer takes any
irq-safe locks, which may or may not improve the overall system
performance.
This patch also adds a bit of documentation of the internal data
structures.
Signed-off-by: Haavard Skinnemoen <haavard.skinnemoen@atmel.com>
2008-09-17 12:53:55 -06:00
|
|
|
bool need_clock_update;
|
|
|
|
bool need_reset;
|
2012-05-16 07:26:00 -06:00
|
|
|
struct timer_list timer;
|
atmel-mci: support multiple mmc slots
The Atmel MCI controller can drive multiple cards through separate sets
of pins, but only one at a time. This patch adds support for
multiplexing access to the controller so that multiple card slots can be
used as if they were hooked up to separate mmc controllers.
The atmel-mci driver registers each slot as a separate mmc_host. Both
access the same common controller state, but they also have some state
on their own for card detection/write protect handling, and separate
shadows of the MR and SDCR registers.
When one of the slots receives a request from the mmc core, the common
controller state is checked. If it's idle, the request is submitted
immediately. If not, the request is added to a queue. When a request is
done, the queue is checked and if there is a queued request, it is
submitted before the completion callback is called.
This patch also includes a few cleanups and fixes, including a locking
overhaul. I had to change the locking extensively in any case, so I
might as well try to get it right. The driver no longer takes any
irq-safe locks, which may or may not improve the overall system
performance.
This patch also adds a bit of documentation of the internal data
structures.
Signed-off-by: Haavard Skinnemoen <haavard.skinnemoen@atmel.com>
2008-09-17 12:53:55 -06:00
|
|
|
u32 mode_reg;
|
2009-12-14 19:01:31 -07:00
|
|
|
u32 cfg_reg;
|
atmel-mci: Driver for Atmel on-chip MMC controllers
This is a driver for the MMC controller on the AP7000 chips from
Atmel. It should in theory work on AT91 systems too with some
tweaking, but since the DMA interface is quite different, it's not
entirely clear if it's worth merging this with the at91_mci driver.
This driver has been around for a while in BSPs and kernel sources
provided by Atmel, but this particular version uses the generic DMA
Engine framework (with the slave extensions) instead of an
avr32-only DMA controller framework.
This driver can also use PIO transfers when no DMA channels are
available, and for transfers where using DMA may be difficult or
impractical for some reason (e.g. the DMA setup overhead is usually
not worth it for very short transfers, and badly aligned buffers or
lengths are difficult to handle.)
Currently, the driver only support PIO transfers. DMA support has been
split out to a separate patch to hopefully make it easier to review.
The driver has been tested using mmc-block and ext3fs on several SD,
SDHC and MMC+ cards. Reads and writes work fine, with read transfer
rates up to 3.5 MiB/s on fast cards with debugging disabled.
The driver has also been tested using the mmc_test module on the same
cards. All tests except 7, 9, 15 and 17 succeed. The first two are
unsupported by all the cards I have, so I don't know if the driver
handles this correctly. The last two fail because the hardware flags a
Data CRC Error instead of a Data Timeout error. I'm not sure how to deal
with that.
Documentation for this controller can be found in many data sheets from
Atmel, including the AT32AP7000 data sheet which can be found here:
http://www.atmel.com/dyn/products/datasheets.asp?family_id=682
Signed-off-by: Haavard Skinnemoen <haavard.skinnemoen@atmel.com>
Signed-off-by: Pierre Ossman <drzeus@drzeus.cx>
2008-06-30 10:35:03 -06:00
|
|
|
unsigned long bus_hz;
|
|
|
|
unsigned long mapbase;
|
|
|
|
struct clk *mck;
|
|
|
|
struct platform_device *pdev;
|
atmel-mci: support multiple mmc slots
The Atmel MCI controller can drive multiple cards through separate sets
of pins, but only one at a time. This patch adds support for
multiplexing access to the controller so that multiple card slots can be
used as if they were hooked up to separate mmc controllers.
The atmel-mci driver registers each slot as a separate mmc_host. Both
access the same common controller state, but they also have some state
on their own for card detection/write protect handling, and separate
shadows of the MR and SDCR registers.
When one of the slots receives a request from the mmc core, the common
controller state is checked. If it's idle, the request is submitted
immediately. If not, the request is added to a queue. When a request is
done, the queue is checked and if there is a queued request, it is
submitted before the completion callback is called.
This patch also includes a few cleanups and fixes, including a locking
overhaul. I had to change the locking extensively in any case, so I
might as well try to get it right. The driver no longer takes any
irq-safe locks, which may or may not improve the overall system
performance.
This patch also adds a bit of documentation of the internal data
structures.
Signed-off-by: Haavard Skinnemoen <haavard.skinnemoen@atmel.com>
2008-09-17 12:53:55 -06:00
|
|
|
|
2011-08-11 09:25:41 -06:00
|
|
|
struct atmel_mci_slot *slot[ATMCI_MAX_NR_SLOTS];
|
2011-08-11 09:25:44 -06:00
|
|
|
|
|
|
|
struct atmel_mci_caps caps;
|
|
|
|
|
|
|
|
u32 (*prepare_data)(struct atmel_mci *host, struct mmc_data *data);
|
|
|
|
void (*submit_data)(struct atmel_mci *host, struct mmc_data *data);
|
|
|
|
void (*stop_transfer)(struct atmel_mci *host);
|
atmel-mci: support multiple mmc slots
The Atmel MCI controller can drive multiple cards through separate sets
of pins, but only one at a time. This patch adds support for
multiplexing access to the controller so that multiple card slots can be
used as if they were hooked up to separate mmc controllers.
The atmel-mci driver registers each slot as a separate mmc_host. Both
access the same common controller state, but they also have some state
on their own for card detection/write protect handling, and separate
shadows of the MR and SDCR registers.
When one of the slots receives a request from the mmc core, the common
controller state is checked. If it's idle, the request is submitted
immediately. If not, the request is added to a queue. When a request is
done, the queue is checked and if there is a queued request, it is
submitted before the completion callback is called.
This patch also includes a few cleanups and fixes, including a locking
overhaul. I had to change the locking extensively in any case, so I
might as well try to get it right. The driver no longer takes any
irq-safe locks, which may or may not improve the overall system
performance.
This patch also adds a bit of documentation of the internal data
structures.
Signed-off-by: Haavard Skinnemoen <haavard.skinnemoen@atmel.com>
2008-09-17 12:53:55 -06:00
|
|
|
};
|
|
|
|
|
|
|
|
/**
|
|
|
|
* struct atmel_mci_slot - MMC slot state
|
|
|
|
* @mmc: The mmc_host representing this slot.
|
|
|
|
* @host: The MMC controller this slot is using.
|
|
|
|
* @sdc_reg: Value of SDCR to be written before using this slot.
|
2010-05-26 15:42:01 -06:00
|
|
|
* @sdio_irq: SDIO irq mask for this slot.
|
atmel-mci: support multiple mmc slots
The Atmel MCI controller can drive multiple cards through separate sets
of pins, but only one at a time. This patch adds support for
multiplexing access to the controller so that multiple card slots can be
used as if they were hooked up to separate mmc controllers.
The atmel-mci driver registers each slot as a separate mmc_host. Both
access the same common controller state, but they also have some state
on their own for card detection/write protect handling, and separate
shadows of the MR and SDCR registers.
When one of the slots receives a request from the mmc core, the common
controller state is checked. If it's idle, the request is submitted
immediately. If not, the request is added to a queue. When a request is
done, the queue is checked and if there is a queued request, it is
submitted before the completion callback is called.
This patch also includes a few cleanups and fixes, including a locking
overhaul. I had to change the locking extensively in any case, so I
might as well try to get it right. The driver no longer takes any
irq-safe locks, which may or may not improve the overall system
performance.
This patch also adds a bit of documentation of the internal data
structures.
Signed-off-by: Haavard Skinnemoen <haavard.skinnemoen@atmel.com>
2008-09-17 12:53:55 -06:00
|
|
|
* @mrq: mmc_request currently being processed or waiting to be
|
|
|
|
* processed, or NULL when the slot is idle.
|
|
|
|
* @queue_node: List node for placing this node in the @queue list of
|
|
|
|
* &struct atmel_mci.
|
|
|
|
* @clock: Clock rate configured by set_ios(). Protected by host->lock.
|
|
|
|
* @flags: Random state bits associated with the slot.
|
|
|
|
* @detect_pin: GPIO pin used for card detection, or negative if not
|
|
|
|
* available.
|
|
|
|
* @wp_pin: GPIO pin used for card write protect sending, or negative
|
|
|
|
* if not available.
|
2009-03-31 03:16:48 -06:00
|
|
|
* @detect_is_active_high: The state of the detect pin when it is active.
|
atmel-mci: support multiple mmc slots
The Atmel MCI controller can drive multiple cards through separate sets
of pins, but only one at a time. This patch adds support for
multiplexing access to the controller so that multiple card slots can be
used as if they were hooked up to separate mmc controllers.
The atmel-mci driver registers each slot as a separate mmc_host. Both
access the same common controller state, but they also have some state
on their own for card detection/write protect handling, and separate
shadows of the MR and SDCR registers.
When one of the slots receives a request from the mmc core, the common
controller state is checked. If it's idle, the request is submitted
immediately. If not, the request is added to a queue. When a request is
done, the queue is checked and if there is a queued request, it is
submitted before the completion callback is called.
This patch also includes a few cleanups and fixes, including a locking
overhaul. I had to change the locking extensively in any case, so I
might as well try to get it right. The driver no longer takes any
irq-safe locks, which may or may not improve the overall system
performance.
This patch also adds a bit of documentation of the internal data
structures.
Signed-off-by: Haavard Skinnemoen <haavard.skinnemoen@atmel.com>
2008-09-17 12:53:55 -06:00
|
|
|
* @detect_timer: Timer used for debouncing @detect_pin interrupts.
|
|
|
|
*/
|
|
|
|
struct atmel_mci_slot {
|
|
|
|
struct mmc_host *mmc;
|
|
|
|
struct atmel_mci *host;
|
|
|
|
|
|
|
|
u32 sdc_reg;
|
2010-05-26 15:42:01 -06:00
|
|
|
u32 sdio_irq;
|
atmel-mci: support multiple mmc slots
The Atmel MCI controller can drive multiple cards through separate sets
of pins, but only one at a time. This patch adds support for
multiplexing access to the controller so that multiple card slots can be
used as if they were hooked up to separate mmc controllers.
The atmel-mci driver registers each slot as a separate mmc_host. Both
access the same common controller state, but they also have some state
on their own for card detection/write protect handling, and separate
shadows of the MR and SDCR registers.
When one of the slots receives a request from the mmc core, the common
controller state is checked. If it's idle, the request is submitted
immediately. If not, the request is added to a queue. When a request is
done, the queue is checked and if there is a queued request, it is
submitted before the completion callback is called.
This patch also includes a few cleanups and fixes, including a locking
overhaul. I had to change the locking extensively in any case, so I
might as well try to get it right. The driver no longer takes any
irq-safe locks, which may or may not improve the overall system
performance.
This patch also adds a bit of documentation of the internal data
structures.
Signed-off-by: Haavard Skinnemoen <haavard.skinnemoen@atmel.com>
2008-09-17 12:53:55 -06:00
|
|
|
|
|
|
|
struct mmc_request *mrq;
|
|
|
|
struct list_head queue_node;
|
|
|
|
|
|
|
|
unsigned int clock;
|
|
|
|
unsigned long flags;
|
|
|
|
#define ATMCI_CARD_PRESENT 0
|
|
|
|
#define ATMCI_CARD_NEED_INIT 1
|
|
|
|
#define ATMCI_SHUTDOWN 2
|
|
|
|
|
|
|
|
int detect_pin;
|
|
|
|
int wp_pin;
|
2009-03-31 03:16:48 -06:00
|
|
|
bool detect_is_active_high;
|
atmel-mci: support multiple mmc slots
The Atmel MCI controller can drive multiple cards through separate sets
of pins, but only one at a time. This patch adds support for
multiplexing access to the controller so that multiple card slots can be
used as if they were hooked up to separate mmc controllers.
The atmel-mci driver registers each slot as a separate mmc_host. Both
access the same common controller state, but they also have some state
on their own for card detection/write protect handling, and separate
shadows of the MR and SDCR registers.
When one of the slots receives a request from the mmc core, the common
controller state is checked. If it's idle, the request is submitted
immediately. If not, the request is added to a queue. When a request is
done, the queue is checked and if there is a queued request, it is
submitted before the completion callback is called.
This patch also includes a few cleanups and fixes, including a locking
overhaul. I had to change the locking extensively in any case, so I
might as well try to get it right. The driver no longer takes any
irq-safe locks, which may or may not improve the overall system
performance.
This patch also adds a bit of documentation of the internal data
structures.
Signed-off-by: Haavard Skinnemoen <haavard.skinnemoen@atmel.com>
2008-09-17 12:53:55 -06:00
|
|
|
|
|
|
|
struct timer_list detect_timer;
|
atmel-mci: Driver for Atmel on-chip MMC controllers
This is a driver for the MMC controller on the AP7000 chips from
Atmel. It should in theory work on AT91 systems too with some
tweaking, but since the DMA interface is quite different, it's not
entirely clear if it's worth merging this with the at91_mci driver.
This driver has been around for a while in BSPs and kernel sources
provided by Atmel, but this particular version uses the generic DMA
Engine framework (with the slave extensions) instead of an
avr32-only DMA controller framework.
This driver can also use PIO transfers when no DMA channels are
available, and for transfers where using DMA may be difficult or
impractical for some reason (e.g. the DMA setup overhead is usually
not worth it for very short transfers, and badly aligned buffers or
lengths are difficult to handle.)
Currently, the driver only support PIO transfers. DMA support has been
split out to a separate patch to hopefully make it easier to review.
The driver has been tested using mmc-block and ext3fs on several SD,
SDHC and MMC+ cards. Reads and writes work fine, with read transfer
rates up to 3.5 MiB/s on fast cards with debugging disabled.
The driver has also been tested using the mmc_test module on the same
cards. All tests except 7, 9, 15 and 17 succeed. The first two are
unsupported by all the cards I have, so I don't know if the driver
handles this correctly. The last two fail because the hardware flags a
Data CRC Error instead of a Data Timeout error. I'm not sure how to deal
with that.
Documentation for this controller can be found in many data sheets from
Atmel, including the AT32AP7000 data sheet which can be found here:
http://www.atmel.com/dyn/products/datasheets.asp?family_id=682
Signed-off-by: Haavard Skinnemoen <haavard.skinnemoen@atmel.com>
Signed-off-by: Pierre Ossman <drzeus@drzeus.cx>
2008-06-30 10:35:03 -06:00
|
|
|
};
|
|
|
|
|
|
|
|
#define atmci_test_and_clear_pending(host, event) \
|
|
|
|
test_and_clear_bit(event, &host->pending_events)
|
|
|
|
#define atmci_set_completed(host, event) \
|
|
|
|
set_bit(event, &host->completed_events)
|
|
|
|
#define atmci_set_pending(host, event) \
|
|
|
|
set_bit(event, &host->pending_events)
|
|
|
|
|
2008-07-24 06:18:59 -06:00
|
|
|
/*
|
|
|
|
* The debugfs stuff below is mostly optimized away when
|
|
|
|
* CONFIG_DEBUG_FS is not set.
|
|
|
|
*/
|
|
|
|
static int atmci_req_show(struct seq_file *s, void *v)
|
|
|
|
{
|
atmel-mci: support multiple mmc slots
The Atmel MCI controller can drive multiple cards through separate sets
of pins, but only one at a time. This patch adds support for
multiplexing access to the controller so that multiple card slots can be
used as if they were hooked up to separate mmc controllers.
The atmel-mci driver registers each slot as a separate mmc_host. Both
access the same common controller state, but they also have some state
on their own for card detection/write protect handling, and separate
shadows of the MR and SDCR registers.
When one of the slots receives a request from the mmc core, the common
controller state is checked. If it's idle, the request is submitted
immediately. If not, the request is added to a queue. When a request is
done, the queue is checked and if there is a queued request, it is
submitted before the completion callback is called.
This patch also includes a few cleanups and fixes, including a locking
overhaul. I had to change the locking extensively in any case, so I
might as well try to get it right. The driver no longer takes any
irq-safe locks, which may or may not improve the overall system
performance.
This patch also adds a bit of documentation of the internal data
structures.
Signed-off-by: Haavard Skinnemoen <haavard.skinnemoen@atmel.com>
2008-09-17 12:53:55 -06:00
|
|
|
struct atmel_mci_slot *slot = s->private;
|
|
|
|
struct mmc_request *mrq;
|
2008-07-24 06:18:59 -06:00
|
|
|
struct mmc_command *cmd;
|
|
|
|
struct mmc_command *stop;
|
|
|
|
struct mmc_data *data;
|
|
|
|
|
|
|
|
/* Make sure we get a consistent snapshot */
|
atmel-mci: support multiple mmc slots
The Atmel MCI controller can drive multiple cards through separate sets
of pins, but only one at a time. This patch adds support for
multiplexing access to the controller so that multiple card slots can be
used as if they were hooked up to separate mmc controllers.
The atmel-mci driver registers each slot as a separate mmc_host. Both
access the same common controller state, but they also have some state
on their own for card detection/write protect handling, and separate
shadows of the MR and SDCR registers.
When one of the slots receives a request from the mmc core, the common
controller state is checked. If it's idle, the request is submitted
immediately. If not, the request is added to a queue. When a request is
done, the queue is checked and if there is a queued request, it is
submitted before the completion callback is called.
This patch also includes a few cleanups and fixes, including a locking
overhaul. I had to change the locking extensively in any case, so I
might as well try to get it right. The driver no longer takes any
irq-safe locks, which may or may not improve the overall system
performance.
This patch also adds a bit of documentation of the internal data
structures.
Signed-off-by: Haavard Skinnemoen <haavard.skinnemoen@atmel.com>
2008-09-17 12:53:55 -06:00
|
|
|
spin_lock_bh(&slot->host->lock);
|
|
|
|
mrq = slot->mrq;
|
2008-07-24 06:18:59 -06:00
|
|
|
|
|
|
|
if (mrq) {
|
|
|
|
cmd = mrq->cmd;
|
|
|
|
data = mrq->data;
|
|
|
|
stop = mrq->stop;
|
|
|
|
|
|
|
|
if (cmd)
|
|
|
|
seq_printf(s,
|
|
|
|
"CMD%u(0x%x) flg %x rsp %x %x %x %x err %d\n",
|
|
|
|
cmd->opcode, cmd->arg, cmd->flags,
|
|
|
|
cmd->resp[0], cmd->resp[1], cmd->resp[2],
|
2010-05-11 15:06:50 -06:00
|
|
|
cmd->resp[3], cmd->error);
|
2008-07-24 06:18:59 -06:00
|
|
|
if (data)
|
|
|
|
seq_printf(s, "DATA %u / %u * %u flg %x err %d\n",
|
|
|
|
data->bytes_xfered, data->blocks,
|
|
|
|
data->blksz, data->flags, data->error);
|
|
|
|
if (stop)
|
|
|
|
seq_printf(s,
|
|
|
|
"CMD%u(0x%x) flg %x rsp %x %x %x %x err %d\n",
|
|
|
|
stop->opcode, stop->arg, stop->flags,
|
|
|
|
stop->resp[0], stop->resp[1], stop->resp[2],
|
2010-05-11 15:06:50 -06:00
|
|
|
stop->resp[3], stop->error);
|
2008-07-24 06:18:59 -06:00
|
|
|
}
|
|
|
|
|
atmel-mci: support multiple mmc slots
The Atmel MCI controller can drive multiple cards through separate sets
of pins, but only one at a time. This patch adds support for
multiplexing access to the controller so that multiple card slots can be
used as if they were hooked up to separate mmc controllers.
The atmel-mci driver registers each slot as a separate mmc_host. Both
access the same common controller state, but they also have some state
on their own for card detection/write protect handling, and separate
shadows of the MR and SDCR registers.
When one of the slots receives a request from the mmc core, the common
controller state is checked. If it's idle, the request is submitted
immediately. If not, the request is added to a queue. When a request is
done, the queue is checked and if there is a queued request, it is
submitted before the completion callback is called.
This patch also includes a few cleanups and fixes, including a locking
overhaul. I had to change the locking extensively in any case, so I
might as well try to get it right. The driver no longer takes any
irq-safe locks, which may or may not improve the overall system
performance.
This patch also adds a bit of documentation of the internal data
structures.
Signed-off-by: Haavard Skinnemoen <haavard.skinnemoen@atmel.com>
2008-09-17 12:53:55 -06:00
|
|
|
spin_unlock_bh(&slot->host->lock);
|
2008-07-24 06:18:59 -06:00
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int atmci_req_open(struct inode *inode, struct file *file)
|
|
|
|
{
|
|
|
|
return single_open(file, atmci_req_show, inode->i_private);
|
|
|
|
}
|
|
|
|
|
|
|
|
static const struct file_operations atmci_req_fops = {
|
|
|
|
.owner = THIS_MODULE,
|
|
|
|
.open = atmci_req_open,
|
|
|
|
.read = seq_read,
|
|
|
|
.llseek = seq_lseek,
|
|
|
|
.release = single_release,
|
|
|
|
};
|
|
|
|
|
|
|
|
static void atmci_show_status_reg(struct seq_file *s,
|
|
|
|
const char *regname, u32 value)
|
|
|
|
{
|
|
|
|
static const char *sr_bit[] = {
|
|
|
|
[0] = "CMDRDY",
|
|
|
|
[1] = "RXRDY",
|
|
|
|
[2] = "TXRDY",
|
|
|
|
[3] = "BLKE",
|
|
|
|
[4] = "DTIP",
|
|
|
|
[5] = "NOTBUSY",
|
2009-09-22 17:45:19 -06:00
|
|
|
[6] = "ENDRX",
|
|
|
|
[7] = "ENDTX",
|
2008-07-24 06:18:59 -06:00
|
|
|
[8] = "SDIOIRQA",
|
|
|
|
[9] = "SDIOIRQB",
|
2009-09-22 17:45:19 -06:00
|
|
|
[12] = "SDIOWAIT",
|
|
|
|
[14] = "RXBUFF",
|
|
|
|
[15] = "TXBUFE",
|
2008-07-24 06:18:59 -06:00
|
|
|
[16] = "RINDE",
|
|
|
|
[17] = "RDIRE",
|
|
|
|
[18] = "RCRCE",
|
|
|
|
[19] = "RENDE",
|
|
|
|
[20] = "RTOE",
|
|
|
|
[21] = "DCRCE",
|
|
|
|
[22] = "DTOE",
|
2009-09-22 17:45:19 -06:00
|
|
|
[23] = "CSTOE",
|
|
|
|
[24] = "BLKOVRE",
|
|
|
|
[25] = "DMADONE",
|
|
|
|
[26] = "FIFOEMPTY",
|
|
|
|
[27] = "XFRDONE",
|
2008-07-24 06:18:59 -06:00
|
|
|
[30] = "OVRE",
|
|
|
|
[31] = "UNRE",
|
|
|
|
};
|
|
|
|
unsigned int i;
|
|
|
|
|
|
|
|
seq_printf(s, "%s:\t0x%08x", regname, value);
|
|
|
|
for (i = 0; i < ARRAY_SIZE(sr_bit); i++) {
|
|
|
|
if (value & (1 << i)) {
|
|
|
|
if (sr_bit[i])
|
|
|
|
seq_printf(s, " %s", sr_bit[i]);
|
|
|
|
else
|
|
|
|
seq_puts(s, " UNKNOWN");
|
|
|
|
}
|
|
|
|
}
|
|
|
|
seq_putc(s, '\n');
|
|
|
|
}
|
|
|
|
|
|
|
|
static int atmci_regs_show(struct seq_file *s, void *v)
|
|
|
|
{
|
|
|
|
struct atmel_mci *host = s->private;
|
|
|
|
u32 *buf;
|
2013-07-18 01:38:52 -06:00
|
|
|
int ret = 0;
|
|
|
|
|
2008-07-24 06:18:59 -06:00
|
|
|
|
2011-08-11 09:25:41 -06:00
|
|
|
buf = kmalloc(ATMCI_REGS_SIZE, GFP_KERNEL);
|
2008-07-24 06:18:59 -06:00
|
|
|
if (!buf)
|
|
|
|
return -ENOMEM;
|
|
|
|
|
2014-10-29 22:00:41 -06:00
|
|
|
pm_runtime_get_sync(&host->pdev->dev);
|
|
|
|
|
atmel-mci: support multiple mmc slots
The Atmel MCI controller can drive multiple cards through separate sets
of pins, but only one at a time. This patch adds support for
multiplexing access to the controller so that multiple card slots can be
used as if they were hooked up to separate mmc controllers.
The atmel-mci driver registers each slot as a separate mmc_host. Both
access the same common controller state, but they also have some state
on their own for card detection/write protect handling, and separate
shadows of the MR and SDCR registers.
When one of the slots receives a request from the mmc core, the common
controller state is checked. If it's idle, the request is submitted
immediately. If not, the request is added to a queue. When a request is
done, the queue is checked and if there is a queued request, it is
submitted before the completion callback is called.
This patch also includes a few cleanups and fixes, including a locking
overhaul. I had to change the locking extensively in any case, so I
might as well try to get it right. The driver no longer takes any
irq-safe locks, which may or may not improve the overall system
performance.
This patch also adds a bit of documentation of the internal data
structures.
Signed-off-by: Haavard Skinnemoen <haavard.skinnemoen@atmel.com>
2008-09-17 12:53:55 -06:00
|
|
|
/*
|
|
|
|
* Grab a more or less consistent snapshot. Note that we're
|
|
|
|
* not disabling interrupts, so IMR and SR may not be
|
|
|
|
* consistent.
|
|
|
|
*/
|
|
|
|
spin_lock_bh(&host->lock);
|
2011-08-11 09:25:41 -06:00
|
|
|
memcpy_fromio(buf, host->regs, ATMCI_REGS_SIZE);
|
atmel-mci: support multiple mmc slots
The Atmel MCI controller can drive multiple cards through separate sets
of pins, but only one at a time. This patch adds support for
multiplexing access to the controller so that multiple card slots can be
used as if they were hooked up to separate mmc controllers.
The atmel-mci driver registers each slot as a separate mmc_host. Both
access the same common controller state, but they also have some state
on their own for card detection/write protect handling, and separate
shadows of the MR and SDCR registers.
When one of the slots receives a request from the mmc core, the common
controller state is checked. If it's idle, the request is submitted
immediately. If not, the request is added to a queue. When a request is
done, the queue is checked and if there is a queued request, it is
submitted before the completion callback is called.
This patch also includes a few cleanups and fixes, including a locking
overhaul. I had to change the locking extensively in any case, so I
might as well try to get it right. The driver no longer takes any
irq-safe locks, which may or may not improve the overall system
performance.
This patch also adds a bit of documentation of the internal data
structures.
Signed-off-by: Haavard Skinnemoen <haavard.skinnemoen@atmel.com>
2008-09-17 12:53:55 -06:00
|
|
|
spin_unlock_bh(&host->lock);
|
2008-07-24 06:18:59 -06:00
|
|
|
|
2014-10-29 22:00:41 -06:00
|
|
|
pm_runtime_mark_last_busy(&host->pdev->dev);
|
|
|
|
pm_runtime_put_autosuspend(&host->pdev->dev);
|
2013-07-18 01:38:52 -06:00
|
|
|
|
2012-07-06 04:11:51 -06:00
|
|
|
seq_printf(s, "MR:\t0x%08x%s%s ",
|
2011-08-11 09:25:41 -06:00
|
|
|
buf[ATMCI_MR / 4],
|
|
|
|
buf[ATMCI_MR / 4] & ATMCI_MR_RDPROOF ? " RDPROOF" : "",
|
2012-07-06 04:11:51 -06:00
|
|
|
buf[ATMCI_MR / 4] & ATMCI_MR_WRPROOF ? " WRPROOF" : "");
|
|
|
|
if (host->caps.has_odd_clk_div)
|
|
|
|
seq_printf(s, "{CLKDIV,CLKODD}=%u\n",
|
|
|
|
((buf[ATMCI_MR / 4] & 0xff) << 1)
|
|
|
|
| ((buf[ATMCI_MR / 4] >> 16) & 1));
|
|
|
|
else
|
|
|
|
seq_printf(s, "CLKDIV=%u\n",
|
|
|
|
(buf[ATMCI_MR / 4] & 0xff));
|
2011-08-11 09:25:41 -06:00
|
|
|
seq_printf(s, "DTOR:\t0x%08x\n", buf[ATMCI_DTOR / 4]);
|
|
|
|
seq_printf(s, "SDCR:\t0x%08x\n", buf[ATMCI_SDCR / 4]);
|
|
|
|
seq_printf(s, "ARGR:\t0x%08x\n", buf[ATMCI_ARGR / 4]);
|
2008-07-24 06:18:59 -06:00
|
|
|
seq_printf(s, "BLKR:\t0x%08x BCNT=%u BLKLEN=%u\n",
|
2011-08-11 09:25:41 -06:00
|
|
|
buf[ATMCI_BLKR / 4],
|
|
|
|
buf[ATMCI_BLKR / 4] & 0xffff,
|
|
|
|
(buf[ATMCI_BLKR / 4] >> 16) & 0xffff);
|
2011-08-11 09:25:44 -06:00
|
|
|
if (host->caps.has_cstor_reg)
|
2011-08-11 09:25:41 -06:00
|
|
|
seq_printf(s, "CSTOR:\t0x%08x\n", buf[ATMCI_CSTOR / 4]);
|
2008-07-24 06:18:59 -06:00
|
|
|
|
|
|
|
/* Don't read RSPR and RDR; it will consume the data there */
|
|
|
|
|
2011-08-11 09:25:41 -06:00
|
|
|
atmci_show_status_reg(s, "SR", buf[ATMCI_SR / 4]);
|
|
|
|
atmci_show_status_reg(s, "IMR", buf[ATMCI_IMR / 4]);
|
2008-07-24 06:18:59 -06:00
|
|
|
|
2012-08-30 10:34:38 -06:00
|
|
|
if (host->caps.has_dma_conf_reg) {
|
2009-12-14 19:01:31 -07:00
|
|
|
u32 val;
|
|
|
|
|
2011-08-11 09:25:41 -06:00
|
|
|
val = buf[ATMCI_DMA / 4];
|
2009-12-14 19:01:31 -07:00
|
|
|
seq_printf(s, "DMA:\t0x%08x OFFSET=%u CHKSIZE=%u%s\n",
|
|
|
|
val, val & 3,
|
|
|
|
((val >> 4) & 3) ?
|
|
|
|
1 << (((val >> 4) & 3) + 1) : 1,
|
2011-08-11 09:25:41 -06:00
|
|
|
val & ATMCI_DMAEN ? " DMAEN" : "");
|
2011-08-11 09:25:44 -06:00
|
|
|
}
|
|
|
|
if (host->caps.has_cfg_reg) {
|
|
|
|
u32 val;
|
2009-12-14 19:01:31 -07:00
|
|
|
|
2011-08-11 09:25:41 -06:00
|
|
|
val = buf[ATMCI_CFG / 4];
|
2009-12-14 19:01:31 -07:00
|
|
|
seq_printf(s, "CFG:\t0x%08x%s%s%s%s\n",
|
|
|
|
val,
|
2011-08-11 09:25:41 -06:00
|
|
|
val & ATMCI_CFG_FIFOMODE_1DATA ? " FIFOMODE_ONE_DATA" : "",
|
|
|
|
val & ATMCI_CFG_FERRCTRL_COR ? " FERRCTRL_CLEAR_ON_READ" : "",
|
|
|
|
val & ATMCI_CFG_HSMODE ? " HSMODE" : "",
|
|
|
|
val & ATMCI_CFG_LSYNC ? " LSYNC" : "");
|
2009-12-14 19:01:31 -07:00
|
|
|
}
|
|
|
|
|
2008-09-19 13:09:28 -06:00
|
|
|
kfree(buf);
|
|
|
|
|
2013-07-18 01:38:52 -06:00
|
|
|
return ret;
|
2008-07-24 06:18:59 -06:00
|
|
|
}
|
|
|
|
|
|
|
|
static int atmci_regs_open(struct inode *inode, struct file *file)
|
|
|
|
{
|
|
|
|
return single_open(file, atmci_regs_show, inode->i_private);
|
|
|
|
}
|
|
|
|
|
|
|
|
static const struct file_operations atmci_regs_fops = {
|
|
|
|
.owner = THIS_MODULE,
|
|
|
|
.open = atmci_regs_open,
|
|
|
|
.read = seq_read,
|
|
|
|
.llseek = seq_lseek,
|
|
|
|
.release = single_release,
|
|
|
|
};
|
|
|
|
|
atmel-mci: support multiple mmc slots
The Atmel MCI controller can drive multiple cards through separate sets
of pins, but only one at a time. This patch adds support for
multiplexing access to the controller so that multiple card slots can be
used as if they were hooked up to separate mmc controllers.
The atmel-mci driver registers each slot as a separate mmc_host. Both
access the same common controller state, but they also have some state
on their own for card detection/write protect handling, and separate
shadows of the MR and SDCR registers.
When one of the slots receives a request from the mmc core, the common
controller state is checked. If it's idle, the request is submitted
immediately. If not, the request is added to a queue. When a request is
done, the queue is checked and if there is a queued request, it is
submitted before the completion callback is called.
This patch also includes a few cleanups and fixes, including a locking
overhaul. I had to change the locking extensively in any case, so I
might as well try to get it right. The driver no longer takes any
irq-safe locks, which may or may not improve the overall system
performance.
This patch also adds a bit of documentation of the internal data
structures.
Signed-off-by: Haavard Skinnemoen <haavard.skinnemoen@atmel.com>
2008-09-17 12:53:55 -06:00
|
|
|
static void atmci_init_debugfs(struct atmel_mci_slot *slot)
|
2008-07-24 06:18:59 -06:00
|
|
|
{
|
atmel-mci: support multiple mmc slots
The Atmel MCI controller can drive multiple cards through separate sets
of pins, but only one at a time. This patch adds support for
multiplexing access to the controller so that multiple card slots can be
used as if they were hooked up to separate mmc controllers.
The atmel-mci driver registers each slot as a separate mmc_host. Both
access the same common controller state, but they also have some state
on their own for card detection/write protect handling, and separate
shadows of the MR and SDCR registers.
When one of the slots receives a request from the mmc core, the common
controller state is checked. If it's idle, the request is submitted
immediately. If not, the request is added to a queue. When a request is
done, the queue is checked and if there is a queued request, it is
submitted before the completion callback is called.
This patch also includes a few cleanups and fixes, including a locking
overhaul. I had to change the locking extensively in any case, so I
might as well try to get it right. The driver no longer takes any
irq-safe locks, which may or may not improve the overall system
performance.
This patch also adds a bit of documentation of the internal data
structures.
Signed-off-by: Haavard Skinnemoen <haavard.skinnemoen@atmel.com>
2008-09-17 12:53:55 -06:00
|
|
|
struct mmc_host *mmc = slot->mmc;
|
|
|
|
struct atmel_mci *host = slot->host;
|
|
|
|
struct dentry *root;
|
|
|
|
struct dentry *node;
|
2008-07-24 06:18:59 -06:00
|
|
|
|
|
|
|
root = mmc->debugfs_root;
|
|
|
|
if (!root)
|
|
|
|
return;
|
|
|
|
|
|
|
|
node = debugfs_create_file("regs", S_IRUSR, root, host,
|
|
|
|
&atmci_regs_fops);
|
|
|
|
if (IS_ERR(node))
|
|
|
|
return;
|
|
|
|
if (!node)
|
|
|
|
goto err;
|
|
|
|
|
atmel-mci: support multiple mmc slots
The Atmel MCI controller can drive multiple cards through separate sets
of pins, but only one at a time. This patch adds support for
multiplexing access to the controller so that multiple card slots can be
used as if they were hooked up to separate mmc controllers.
The atmel-mci driver registers each slot as a separate mmc_host. Both
access the same common controller state, but they also have some state
on their own for card detection/write protect handling, and separate
shadows of the MR and SDCR registers.
When one of the slots receives a request from the mmc core, the common
controller state is checked. If it's idle, the request is submitted
immediately. If not, the request is added to a queue. When a request is
done, the queue is checked and if there is a queued request, it is
submitted before the completion callback is called.
This patch also includes a few cleanups and fixes, including a locking
overhaul. I had to change the locking extensively in any case, so I
might as well try to get it right. The driver no longer takes any
irq-safe locks, which may or may not improve the overall system
performance.
This patch also adds a bit of documentation of the internal data
structures.
Signed-off-by: Haavard Skinnemoen <haavard.skinnemoen@atmel.com>
2008-09-17 12:53:55 -06:00
|
|
|
node = debugfs_create_file("req", S_IRUSR, root, slot, &atmci_req_fops);
|
2008-07-24 06:18:59 -06:00
|
|
|
if (!node)
|
|
|
|
goto err;
|
|
|
|
|
2008-07-31 06:49:16 -06:00
|
|
|
node = debugfs_create_u32("state", S_IRUSR, root, (u32 *)&host->state);
|
|
|
|
if (!node)
|
|
|
|
goto err;
|
|
|
|
|
2008-07-24 06:18:59 -06:00
|
|
|
node = debugfs_create_x32("pending_events", S_IRUSR, root,
|
|
|
|
(u32 *)&host->pending_events);
|
|
|
|
if (!node)
|
|
|
|
goto err;
|
|
|
|
|
|
|
|
node = debugfs_create_x32("completed_events", S_IRUSR, root,
|
|
|
|
(u32 *)&host->completed_events);
|
|
|
|
if (!node)
|
|
|
|
goto err;
|
|
|
|
|
|
|
|
return;
|
|
|
|
|
|
|
|
err:
|
atmel-mci: support multiple mmc slots
The Atmel MCI controller can drive multiple cards through separate sets
of pins, but only one at a time. This patch adds support for
multiplexing access to the controller so that multiple card slots can be
used as if they were hooked up to separate mmc controllers.
The atmel-mci driver registers each slot as a separate mmc_host. Both
access the same common controller state, but they also have some state
on their own for card detection/write protect handling, and separate
shadows of the MR and SDCR registers.
When one of the slots receives a request from the mmc core, the common
controller state is checked. If it's idle, the request is submitted
immediately. If not, the request is added to a queue. When a request is
done, the queue is checked and if there is a queued request, it is
submitted before the completion callback is called.
This patch also includes a few cleanups and fixes, including a locking
overhaul. I had to change the locking extensively in any case, so I
might as well try to get it right. The driver no longer takes any
irq-safe locks, which may or may not improve the overall system
performance.
This patch also adds a bit of documentation of the internal data
structures.
Signed-off-by: Haavard Skinnemoen <haavard.skinnemoen@atmel.com>
2008-09-17 12:53:55 -06:00
|
|
|
dev_err(&mmc->class_dev, "failed to initialize debugfs for slot\n");
|
2008-07-24 06:18:59 -06:00
|
|
|
}
|
atmel-mci: Driver for Atmel on-chip MMC controllers
This is a driver for the MMC controller on the AP7000 chips from
Atmel. It should in theory work on AT91 systems too with some
tweaking, but since the DMA interface is quite different, it's not
entirely clear if it's worth merging this with the at91_mci driver.
This driver has been around for a while in BSPs and kernel sources
provided by Atmel, but this particular version uses the generic DMA
Engine framework (with the slave extensions) instead of an
avr32-only DMA controller framework.
This driver can also use PIO transfers when no DMA channels are
available, and for transfers where using DMA may be difficult or
impractical for some reason (e.g. the DMA setup overhead is usually
not worth it for very short transfers, and badly aligned buffers or
lengths are difficult to handle.)
Currently, the driver only support PIO transfers. DMA support has been
split out to a separate patch to hopefully make it easier to review.
The driver has been tested using mmc-block and ext3fs on several SD,
SDHC and MMC+ cards. Reads and writes work fine, with read transfer
rates up to 3.5 MiB/s on fast cards with debugging disabled.
The driver has also been tested using the mmc_test module on the same
cards. All tests except 7, 9, 15 and 17 succeed. The first two are
unsupported by all the cards I have, so I don't know if the driver
handles this correctly. The last two fail because the hardware flags a
Data CRC Error instead of a Data Timeout error. I'm not sure how to deal
with that.
Documentation for this controller can be found in many data sheets from
Atmel, including the AT32AP7000 data sheet which can be found here:
http://www.atmel.com/dyn/products/datasheets.asp?family_id=682
Signed-off-by: Haavard Skinnemoen <haavard.skinnemoen@atmel.com>
Signed-off-by: Pierre Ossman <drzeus@drzeus.cx>
2008-06-30 10:35:03 -06:00
|
|
|
|
2012-07-24 07:30:03 -06:00
|
|
|
#if defined(CONFIG_OF)
|
|
|
|
static const struct of_device_id atmci_dt_ids[] = {
|
|
|
|
{ .compatible = "atmel,hsmci" },
|
|
|
|
{ /* sentinel */ }
|
|
|
|
};
|
|
|
|
|
|
|
|
MODULE_DEVICE_TABLE(of, atmci_dt_ids);
|
|
|
|
|
2012-11-19 11:23:06 -07:00
|
|
|
static struct mci_platform_data*
|
2012-07-24 07:30:03 -06:00
|
|
|
atmci_of_init(struct platform_device *pdev)
|
|
|
|
{
|
|
|
|
struct device_node *np = pdev->dev.of_node;
|
|
|
|
struct device_node *cnp;
|
|
|
|
struct mci_platform_data *pdata;
|
|
|
|
u32 slot_id;
|
|
|
|
|
|
|
|
if (!np) {
|
|
|
|
dev_err(&pdev->dev, "device node not found\n");
|
|
|
|
return ERR_PTR(-EINVAL);
|
|
|
|
}
|
|
|
|
|
|
|
|
pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL);
|
|
|
|
if (!pdata) {
|
|
|
|
dev_err(&pdev->dev, "could not allocate memory for pdata\n");
|
|
|
|
return ERR_PTR(-ENOMEM);
|
|
|
|
}
|
|
|
|
|
|
|
|
for_each_child_of_node(np, cnp) {
|
|
|
|
if (of_property_read_u32(cnp, "reg", &slot_id)) {
|
|
|
|
dev_warn(&pdev->dev, "reg property is missing for %s\n",
|
|
|
|
cnp->full_name);
|
|
|
|
continue;
|
|
|
|
}
|
|
|
|
|
|
|
|
if (slot_id >= ATMCI_MAX_NR_SLOTS) {
|
|
|
|
dev_warn(&pdev->dev, "can't have more than %d slots\n",
|
|
|
|
ATMCI_MAX_NR_SLOTS);
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
|
|
|
|
if (of_property_read_u32(cnp, "bus-width",
|
|
|
|
&pdata->slot[slot_id].bus_width))
|
|
|
|
pdata->slot[slot_id].bus_width = 1;
|
|
|
|
|
|
|
|
pdata->slot[slot_id].detect_pin =
|
|
|
|
of_get_named_gpio(cnp, "cd-gpios", 0);
|
|
|
|
|
|
|
|
pdata->slot[slot_id].detect_is_active_high =
|
|
|
|
of_property_read_bool(cnp, "cd-inverted");
|
|
|
|
|
2014-11-03 04:12:59 -07:00
|
|
|
pdata->slot[slot_id].non_removable =
|
|
|
|
of_property_read_bool(cnp, "non-removable");
|
|
|
|
|
2012-07-24 07:30:03 -06:00
|
|
|
pdata->slot[slot_id].wp_pin =
|
|
|
|
of_get_named_gpio(cnp, "wp-gpios", 0);
|
|
|
|
}
|
|
|
|
|
|
|
|
return pdata;
|
|
|
|
}
|
|
|
|
#else /* CONFIG_OF */
|
|
|
|
static inline struct mci_platform_data*
|
|
|
|
atmci_of_init(struct platform_device *dev)
|
|
|
|
{
|
|
|
|
return ERR_PTR(-EINVAL);
|
|
|
|
}
|
|
|
|
#endif
|
|
|
|
|
2012-05-16 07:25:58 -06:00
|
|
|
static inline unsigned int atmci_get_version(struct atmel_mci *host)
|
|
|
|
{
|
|
|
|
return atmci_readl(host, ATMCI_VERSION) & 0x00000fff;
|
|
|
|
}
|
|
|
|
|
2015-11-23 08:27:32 -07:00
|
|
|
/*
|
|
|
|
* Fix sconfig's burst size according to atmel MCI. We need to convert them as:
|
|
|
|
* 1 -> 0, 4 -> 1, 8 -> 2, 16 -> 3.
|
|
|
|
* With version 0x600, we need to convert them as: 1 -> 0, 2 -> 1, 4 -> 2,
|
|
|
|
* 8 -> 3, 16 -> 4.
|
|
|
|
*
|
|
|
|
* This can be done by finding most significant bit set.
|
|
|
|
*/
|
|
|
|
static inline unsigned int atmci_convert_chksize(struct atmel_mci *host,
|
|
|
|
unsigned int maxburst)
|
|
|
|
{
|
|
|
|
unsigned int version = atmci_get_version(host);
|
|
|
|
unsigned int offset = 2;
|
|
|
|
|
|
|
|
if (version >= 0x600)
|
|
|
|
offset = 1;
|
|
|
|
|
|
|
|
if (maxburst > 1)
|
|
|
|
return fls(maxburst) - offset;
|
|
|
|
else
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2012-05-16 07:26:00 -06:00
|
|
|
static void atmci_timeout_timer(unsigned long data)
|
|
|
|
{
|
|
|
|
struct atmel_mci *host;
|
|
|
|
|
|
|
|
host = (struct atmel_mci *)data;
|
|
|
|
|
|
|
|
dev_dbg(&host->pdev->dev, "software timeout\n");
|
|
|
|
|
|
|
|
if (host->mrq->cmd->data) {
|
|
|
|
host->mrq->cmd->data->error = -ETIMEDOUT;
|
|
|
|
host->data = NULL;
|
2013-09-09 09:29:56 -06:00
|
|
|
/*
|
|
|
|
* With some SDIO modules, sometimes DMA transfer hangs. If
|
|
|
|
* stop_transfer() is not called then the DMA request is not
|
|
|
|
* removed, following ones are queued and never computed.
|
|
|
|
*/
|
|
|
|
if (host->state == STATE_DATA_XFER)
|
|
|
|
host->stop_transfer(host);
|
2012-05-16 07:26:00 -06:00
|
|
|
} else {
|
|
|
|
host->mrq->cmd->error = -ETIMEDOUT;
|
|
|
|
host->cmd = NULL;
|
|
|
|
}
|
|
|
|
host->need_reset = 1;
|
|
|
|
host->state = STATE_END_REQUEST;
|
|
|
|
smp_wmb();
|
|
|
|
tasklet_schedule(&host->tasklet);
|
|
|
|
}
|
|
|
|
|
2011-08-11 09:25:41 -06:00
|
|
|
static inline unsigned int atmci_ns_to_clocks(struct atmel_mci *host,
|
atmel-mci: Driver for Atmel on-chip MMC controllers
This is a driver for the MMC controller on the AP7000 chips from
Atmel. It should in theory work on AT91 systems too with some
tweaking, but since the DMA interface is quite different, it's not
entirely clear if it's worth merging this with the at91_mci driver.
This driver has been around for a while in BSPs and kernel sources
provided by Atmel, but this particular version uses the generic DMA
Engine framework (with the slave extensions) instead of an
avr32-only DMA controller framework.
This driver can also use PIO transfers when no DMA channels are
available, and for transfers where using DMA may be difficult or
impractical for some reason (e.g. the DMA setup overhead is usually
not worth it for very short transfers, and badly aligned buffers or
lengths are difficult to handle.)
Currently, the driver only support PIO transfers. DMA support has been
split out to a separate patch to hopefully make it easier to review.
The driver has been tested using mmc-block and ext3fs on several SD,
SDHC and MMC+ cards. Reads and writes work fine, with read transfer
rates up to 3.5 MiB/s on fast cards with debugging disabled.
The driver has also been tested using the mmc_test module on the same
cards. All tests except 7, 9, 15 and 17 succeed. The first two are
unsupported by all the cards I have, so I don't know if the driver
handles this correctly. The last two fail because the hardware flags a
Data CRC Error instead of a Data Timeout error. I'm not sure how to deal
with that.
Documentation for this controller can be found in many data sheets from
Atmel, including the AT32AP7000 data sheet which can be found here:
http://www.atmel.com/dyn/products/datasheets.asp?family_id=682
Signed-off-by: Haavard Skinnemoen <haavard.skinnemoen@atmel.com>
Signed-off-by: Pierre Ossman <drzeus@drzeus.cx>
2008-06-30 10:35:03 -06:00
|
|
|
unsigned int ns)
|
|
|
|
{
|
2012-03-28 04:28:33 -06:00
|
|
|
/*
|
|
|
|
* It is easier here to use us instead of ns for the timeout,
|
|
|
|
* it prevents from overflows during calculation.
|
|
|
|
*/
|
|
|
|
unsigned int us = DIV_ROUND_UP(ns, 1000);
|
|
|
|
|
|
|
|
/* Maximum clock frequency is host->bus_hz/2 */
|
|
|
|
return us * (DIV_ROUND_UP(host->bus_hz, 2000000));
|
atmel-mci: Driver for Atmel on-chip MMC controllers
This is a driver for the MMC controller on the AP7000 chips from
Atmel. It should in theory work on AT91 systems too with some
tweaking, but since the DMA interface is quite different, it's not
entirely clear if it's worth merging this with the at91_mci driver.
This driver has been around for a while in BSPs and kernel sources
provided by Atmel, but this particular version uses the generic DMA
Engine framework (with the slave extensions) instead of an
avr32-only DMA controller framework.
This driver can also use PIO transfers when no DMA channels are
available, and for transfers where using DMA may be difficult or
impractical for some reason (e.g. the DMA setup overhead is usually
not worth it for very short transfers, and badly aligned buffers or
lengths are difficult to handle.)
Currently, the driver only support PIO transfers. DMA support has been
split out to a separate patch to hopefully make it easier to review.
The driver has been tested using mmc-block and ext3fs on several SD,
SDHC and MMC+ cards. Reads and writes work fine, with read transfer
rates up to 3.5 MiB/s on fast cards with debugging disabled.
The driver has also been tested using the mmc_test module on the same
cards. All tests except 7, 9, 15 and 17 succeed. The first two are
unsupported by all the cards I have, so I don't know if the driver
handles this correctly. The last two fail because the hardware flags a
Data CRC Error instead of a Data Timeout error. I'm not sure how to deal
with that.
Documentation for this controller can be found in many data sheets from
Atmel, including the AT32AP7000 data sheet which can be found here:
http://www.atmel.com/dyn/products/datasheets.asp?family_id=682
Signed-off-by: Haavard Skinnemoen <haavard.skinnemoen@atmel.com>
Signed-off-by: Pierre Ossman <drzeus@drzeus.cx>
2008-06-30 10:35:03 -06:00
|
|
|
}
|
|
|
|
|
|
|
|
static void atmci_set_timeout(struct atmel_mci *host,
|
atmel-mci: support multiple mmc slots
The Atmel MCI controller can drive multiple cards through separate sets
of pins, but only one at a time. This patch adds support for
multiplexing access to the controller so that multiple card slots can be
used as if they were hooked up to separate mmc controllers.
The atmel-mci driver registers each slot as a separate mmc_host. Both
access the same common controller state, but they also have some state
on their own for card detection/write protect handling, and separate
shadows of the MR and SDCR registers.
When one of the slots receives a request from the mmc core, the common
controller state is checked. If it's idle, the request is submitted
immediately. If not, the request is added to a queue. When a request is
done, the queue is checked and if there is a queued request, it is
submitted before the completion callback is called.
This patch also includes a few cleanups and fixes, including a locking
overhaul. I had to change the locking extensively in any case, so I
might as well try to get it right. The driver no longer takes any
irq-safe locks, which may or may not improve the overall system
performance.
This patch also adds a bit of documentation of the internal data
structures.
Signed-off-by: Haavard Skinnemoen <haavard.skinnemoen@atmel.com>
2008-09-17 12:53:55 -06:00
|
|
|
struct atmel_mci_slot *slot, struct mmc_data *data)
|
atmel-mci: Driver for Atmel on-chip MMC controllers
This is a driver for the MMC controller on the AP7000 chips from
Atmel. It should in theory work on AT91 systems too with some
tweaking, but since the DMA interface is quite different, it's not
entirely clear if it's worth merging this with the at91_mci driver.
This driver has been around for a while in BSPs and kernel sources
provided by Atmel, but this particular version uses the generic DMA
Engine framework (with the slave extensions) instead of an
avr32-only DMA controller framework.
This driver can also use PIO transfers when no DMA channels are
available, and for transfers where using DMA may be difficult or
impractical for some reason (e.g. the DMA setup overhead is usually
not worth it for very short transfers, and badly aligned buffers or
lengths are difficult to handle.)
Currently, the driver only support PIO transfers. DMA support has been
split out to a separate patch to hopefully make it easier to review.
The driver has been tested using mmc-block and ext3fs on several SD,
SDHC and MMC+ cards. Reads and writes work fine, with read transfer
rates up to 3.5 MiB/s on fast cards with debugging disabled.
The driver has also been tested using the mmc_test module on the same
cards. All tests except 7, 9, 15 and 17 succeed. The first two are
unsupported by all the cards I have, so I don't know if the driver
handles this correctly. The last two fail because the hardware flags a
Data CRC Error instead of a Data Timeout error. I'm not sure how to deal
with that.
Documentation for this controller can be found in many data sheets from
Atmel, including the AT32AP7000 data sheet which can be found here:
http://www.atmel.com/dyn/products/datasheets.asp?family_id=682
Signed-off-by: Haavard Skinnemoen <haavard.skinnemoen@atmel.com>
Signed-off-by: Pierre Ossman <drzeus@drzeus.cx>
2008-06-30 10:35:03 -06:00
|
|
|
{
|
|
|
|
static unsigned dtomul_to_shift[] = {
|
|
|
|
0, 4, 7, 8, 10, 12, 16, 20
|
|
|
|
};
|
|
|
|
unsigned timeout;
|
|
|
|
unsigned dtocyc;
|
|
|
|
unsigned dtomul;
|
|
|
|
|
2011-08-11 09:25:41 -06:00
|
|
|
timeout = atmci_ns_to_clocks(host, data->timeout_ns)
|
|
|
|
+ data->timeout_clks;
|
atmel-mci: Driver for Atmel on-chip MMC controllers
This is a driver for the MMC controller on the AP7000 chips from
Atmel. It should in theory work on AT91 systems too with some
tweaking, but since the DMA interface is quite different, it's not
entirely clear if it's worth merging this with the at91_mci driver.
This driver has been around for a while in BSPs and kernel sources
provided by Atmel, but this particular version uses the generic DMA
Engine framework (with the slave extensions) instead of an
avr32-only DMA controller framework.
This driver can also use PIO transfers when no DMA channels are
available, and for transfers where using DMA may be difficult or
impractical for some reason (e.g. the DMA setup overhead is usually
not worth it for very short transfers, and badly aligned buffers or
lengths are difficult to handle.)
Currently, the driver only support PIO transfers. DMA support has been
split out to a separate patch to hopefully make it easier to review.
The driver has been tested using mmc-block and ext3fs on several SD,
SDHC and MMC+ cards. Reads and writes work fine, with read transfer
rates up to 3.5 MiB/s on fast cards with debugging disabled.
The driver has also been tested using the mmc_test module on the same
cards. All tests except 7, 9, 15 and 17 succeed. The first two are
unsupported by all the cards I have, so I don't know if the driver
handles this correctly. The last two fail because the hardware flags a
Data CRC Error instead of a Data Timeout error. I'm not sure how to deal
with that.
Documentation for this controller can be found in many data sheets from
Atmel, including the AT32AP7000 data sheet which can be found here:
http://www.atmel.com/dyn/products/datasheets.asp?family_id=682
Signed-off-by: Haavard Skinnemoen <haavard.skinnemoen@atmel.com>
Signed-off-by: Pierre Ossman <drzeus@drzeus.cx>
2008-06-30 10:35:03 -06:00
|
|
|
|
|
|
|
for (dtomul = 0; dtomul < 8; dtomul++) {
|
|
|
|
unsigned shift = dtomul_to_shift[dtomul];
|
|
|
|
dtocyc = (timeout + (1 << shift) - 1) >> shift;
|
|
|
|
if (dtocyc < 15)
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
|
|
|
|
if (dtomul >= 8) {
|
|
|
|
dtomul = 7;
|
|
|
|
dtocyc = 15;
|
|
|
|
}
|
|
|
|
|
atmel-mci: support multiple mmc slots
The Atmel MCI controller can drive multiple cards through separate sets
of pins, but only one at a time. This patch adds support for
multiplexing access to the controller so that multiple card slots can be
used as if they were hooked up to separate mmc controllers.
The atmel-mci driver registers each slot as a separate mmc_host. Both
access the same common controller state, but they also have some state
on their own for card detection/write protect handling, and separate
shadows of the MR and SDCR registers.
When one of the slots receives a request from the mmc core, the common
controller state is checked. If it's idle, the request is submitted
immediately. If not, the request is added to a queue. When a request is
done, the queue is checked and if there is a queued request, it is
submitted before the completion callback is called.
This patch also includes a few cleanups and fixes, including a locking
overhaul. I had to change the locking extensively in any case, so I
might as well try to get it right. The driver no longer takes any
irq-safe locks, which may or may not improve the overall system
performance.
This patch also adds a bit of documentation of the internal data
structures.
Signed-off-by: Haavard Skinnemoen <haavard.skinnemoen@atmel.com>
2008-09-17 12:53:55 -06:00
|
|
|
dev_vdbg(&slot->mmc->class_dev, "setting timeout to %u cycles\n",
|
atmel-mci: Driver for Atmel on-chip MMC controllers
This is a driver for the MMC controller on the AP7000 chips from
Atmel. It should in theory work on AT91 systems too with some
tweaking, but since the DMA interface is quite different, it's not
entirely clear if it's worth merging this with the at91_mci driver.
This driver has been around for a while in BSPs and kernel sources
provided by Atmel, but this particular version uses the generic DMA
Engine framework (with the slave extensions) instead of an
avr32-only DMA controller framework.
This driver can also use PIO transfers when no DMA channels are
available, and for transfers where using DMA may be difficult or
impractical for some reason (e.g. the DMA setup overhead is usually
not worth it for very short transfers, and badly aligned buffers or
lengths are difficult to handle.)
Currently, the driver only support PIO transfers. DMA support has been
split out to a separate patch to hopefully make it easier to review.
The driver has been tested using mmc-block and ext3fs on several SD,
SDHC and MMC+ cards. Reads and writes work fine, with read transfer
rates up to 3.5 MiB/s on fast cards with debugging disabled.
The driver has also been tested using the mmc_test module on the same
cards. All tests except 7, 9, 15 and 17 succeed. The first two are
unsupported by all the cards I have, so I don't know if the driver
handles this correctly. The last two fail because the hardware flags a
Data CRC Error instead of a Data Timeout error. I'm not sure how to deal
with that.
Documentation for this controller can be found in many data sheets from
Atmel, including the AT32AP7000 data sheet which can be found here:
http://www.atmel.com/dyn/products/datasheets.asp?family_id=682
Signed-off-by: Haavard Skinnemoen <haavard.skinnemoen@atmel.com>
Signed-off-by: Pierre Ossman <drzeus@drzeus.cx>
2008-06-30 10:35:03 -06:00
|
|
|
dtocyc << dtomul_to_shift[dtomul]);
|
2011-08-11 09:25:42 -06:00
|
|
|
atmci_writel(host, ATMCI_DTOR, (ATMCI_DTOMUL(dtomul) | ATMCI_DTOCYC(dtocyc)));
|
atmel-mci: Driver for Atmel on-chip MMC controllers
This is a driver for the MMC controller on the AP7000 chips from
Atmel. It should in theory work on AT91 systems too with some
tweaking, but since the DMA interface is quite different, it's not
entirely clear if it's worth merging this with the at91_mci driver.
This driver has been around for a while in BSPs and kernel sources
provided by Atmel, but this particular version uses the generic DMA
Engine framework (with the slave extensions) instead of an
avr32-only DMA controller framework.
This driver can also use PIO transfers when no DMA channels are
available, and for transfers where using DMA may be difficult or
impractical for some reason (e.g. the DMA setup overhead is usually
not worth it for very short transfers, and badly aligned buffers or
lengths are difficult to handle.)
Currently, the driver only support PIO transfers. DMA support has been
split out to a separate patch to hopefully make it easier to review.
The driver has been tested using mmc-block and ext3fs on several SD,
SDHC and MMC+ cards. Reads and writes work fine, with read transfer
rates up to 3.5 MiB/s on fast cards with debugging disabled.
The driver has also been tested using the mmc_test module on the same
cards. All tests except 7, 9, 15 and 17 succeed. The first two are
unsupported by all the cards I have, so I don't know if the driver
handles this correctly. The last two fail because the hardware flags a
Data CRC Error instead of a Data Timeout error. I'm not sure how to deal
with that.
Documentation for this controller can be found in many data sheets from
Atmel, including the AT32AP7000 data sheet which can be found here:
http://www.atmel.com/dyn/products/datasheets.asp?family_id=682
Signed-off-by: Haavard Skinnemoen <haavard.skinnemoen@atmel.com>
Signed-off-by: Pierre Ossman <drzeus@drzeus.cx>
2008-06-30 10:35:03 -06:00
|
|
|
}
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Return mask with command flags to be enabled for this command.
|
|
|
|
*/
|
|
|
|
static u32 atmci_prepare_command(struct mmc_host *mmc,
|
|
|
|
struct mmc_command *cmd)
|
|
|
|
{
|
|
|
|
struct mmc_data *data;
|
|
|
|
u32 cmdr;
|
|
|
|
|
|
|
|
cmd->error = -EINPROGRESS;
|
|
|
|
|
2011-08-11 09:25:41 -06:00
|
|
|
cmdr = ATMCI_CMDR_CMDNB(cmd->opcode);
|
atmel-mci: Driver for Atmel on-chip MMC controllers
This is a driver for the MMC controller on the AP7000 chips from
Atmel. It should in theory work on AT91 systems too with some
tweaking, but since the DMA interface is quite different, it's not
entirely clear if it's worth merging this with the at91_mci driver.
This driver has been around for a while in BSPs and kernel sources
provided by Atmel, but this particular version uses the generic DMA
Engine framework (with the slave extensions) instead of an
avr32-only DMA controller framework.
This driver can also use PIO transfers when no DMA channels are
available, and for transfers where using DMA may be difficult or
impractical for some reason (e.g. the DMA setup overhead is usually
not worth it for very short transfers, and badly aligned buffers or
lengths are difficult to handle.)
Currently, the driver only support PIO transfers. DMA support has been
split out to a separate patch to hopefully make it easier to review.
The driver has been tested using mmc-block and ext3fs on several SD,
SDHC and MMC+ cards. Reads and writes work fine, with read transfer
rates up to 3.5 MiB/s on fast cards with debugging disabled.
The driver has also been tested using the mmc_test module on the same
cards. All tests except 7, 9, 15 and 17 succeed. The first two are
unsupported by all the cards I have, so I don't know if the driver
handles this correctly. The last two fail because the hardware flags a
Data CRC Error instead of a Data Timeout error. I'm not sure how to deal
with that.
Documentation for this controller can be found in many data sheets from
Atmel, including the AT32AP7000 data sheet which can be found here:
http://www.atmel.com/dyn/products/datasheets.asp?family_id=682
Signed-off-by: Haavard Skinnemoen <haavard.skinnemoen@atmel.com>
Signed-off-by: Pierre Ossman <drzeus@drzeus.cx>
2008-06-30 10:35:03 -06:00
|
|
|
|
|
|
|
if (cmd->flags & MMC_RSP_PRESENT) {
|
|
|
|
if (cmd->flags & MMC_RSP_136)
|
2011-08-11 09:25:41 -06:00
|
|
|
cmdr |= ATMCI_CMDR_RSPTYP_136BIT;
|
atmel-mci: Driver for Atmel on-chip MMC controllers
This is a driver for the MMC controller on the AP7000 chips from
Atmel. It should in theory work on AT91 systems too with some
tweaking, but since the DMA interface is quite different, it's not
entirely clear if it's worth merging this with the at91_mci driver.
This driver has been around for a while in BSPs and kernel sources
provided by Atmel, but this particular version uses the generic DMA
Engine framework (with the slave extensions) instead of an
avr32-only DMA controller framework.
This driver can also use PIO transfers when no DMA channels are
available, and for transfers where using DMA may be difficult or
impractical for some reason (e.g. the DMA setup overhead is usually
not worth it for very short transfers, and badly aligned buffers or
lengths are difficult to handle.)
Currently, the driver only support PIO transfers. DMA support has been
split out to a separate patch to hopefully make it easier to review.
The driver has been tested using mmc-block and ext3fs on several SD,
SDHC and MMC+ cards. Reads and writes work fine, with read transfer
rates up to 3.5 MiB/s on fast cards with debugging disabled.
The driver has also been tested using the mmc_test module on the same
cards. All tests except 7, 9, 15 and 17 succeed. The first two are
unsupported by all the cards I have, so I don't know if the driver
handles this correctly. The last two fail because the hardware flags a
Data CRC Error instead of a Data Timeout error. I'm not sure how to deal
with that.
Documentation for this controller can be found in many data sheets from
Atmel, including the AT32AP7000 data sheet which can be found here:
http://www.atmel.com/dyn/products/datasheets.asp?family_id=682
Signed-off-by: Haavard Skinnemoen <haavard.skinnemoen@atmel.com>
Signed-off-by: Pierre Ossman <drzeus@drzeus.cx>
2008-06-30 10:35:03 -06:00
|
|
|
else
|
2011-08-11 09:25:41 -06:00
|
|
|
cmdr |= ATMCI_CMDR_RSPTYP_48BIT;
|
atmel-mci: Driver for Atmel on-chip MMC controllers
This is a driver for the MMC controller on the AP7000 chips from
Atmel. It should in theory work on AT91 systems too with some
tweaking, but since the DMA interface is quite different, it's not
entirely clear if it's worth merging this with the at91_mci driver.
This driver has been around for a while in BSPs and kernel sources
provided by Atmel, but this particular version uses the generic DMA
Engine framework (with the slave extensions) instead of an
avr32-only DMA controller framework.
This driver can also use PIO transfers when no DMA channels are
available, and for transfers where using DMA may be difficult or
impractical for some reason (e.g. the DMA setup overhead is usually
not worth it for very short transfers, and badly aligned buffers or
lengths are difficult to handle.)
Currently, the driver only support PIO transfers. DMA support has been
split out to a separate patch to hopefully make it easier to review.
The driver has been tested using mmc-block and ext3fs on several SD,
SDHC and MMC+ cards. Reads and writes work fine, with read transfer
rates up to 3.5 MiB/s on fast cards with debugging disabled.
The driver has also been tested using the mmc_test module on the same
cards. All tests except 7, 9, 15 and 17 succeed. The first two are
unsupported by all the cards I have, so I don't know if the driver
handles this correctly. The last two fail because the hardware flags a
Data CRC Error instead of a Data Timeout error. I'm not sure how to deal
with that.
Documentation for this controller can be found in many data sheets from
Atmel, including the AT32AP7000 data sheet which can be found here:
http://www.atmel.com/dyn/products/datasheets.asp?family_id=682
Signed-off-by: Haavard Skinnemoen <haavard.skinnemoen@atmel.com>
Signed-off-by: Pierre Ossman <drzeus@drzeus.cx>
2008-06-30 10:35:03 -06:00
|
|
|
}
|
|
|
|
|
|
|
|
/*
|
|
|
|
* This should really be MAXLAT_5 for CMD2 and ACMD41, but
|
|
|
|
* it's too difficult to determine whether this is an ACMD or
|
|
|
|
* not. Better make it 64.
|
|
|
|
*/
|
2011-08-11 09:25:41 -06:00
|
|
|
cmdr |= ATMCI_CMDR_MAXLAT_64CYC;
|
atmel-mci: Driver for Atmel on-chip MMC controllers
This is a driver for the MMC controller on the AP7000 chips from
Atmel. It should in theory work on AT91 systems too with some
tweaking, but since the DMA interface is quite different, it's not
entirely clear if it's worth merging this with the at91_mci driver.
This driver has been around for a while in BSPs and kernel sources
provided by Atmel, but this particular version uses the generic DMA
Engine framework (with the slave extensions) instead of an
avr32-only DMA controller framework.
This driver can also use PIO transfers when no DMA channels are
available, and for transfers where using DMA may be difficult or
impractical for some reason (e.g. the DMA setup overhead is usually
not worth it for very short transfers, and badly aligned buffers or
lengths are difficult to handle.)
Currently, the driver only support PIO transfers. DMA support has been
split out to a separate patch to hopefully make it easier to review.
The driver has been tested using mmc-block and ext3fs on several SD,
SDHC and MMC+ cards. Reads and writes work fine, with read transfer
rates up to 3.5 MiB/s on fast cards with debugging disabled.
The driver has also been tested using the mmc_test module on the same
cards. All tests except 7, 9, 15 and 17 succeed. The first two are
unsupported by all the cards I have, so I don't know if the driver
handles this correctly. The last two fail because the hardware flags a
Data CRC Error instead of a Data Timeout error. I'm not sure how to deal
with that.
Documentation for this controller can be found in many data sheets from
Atmel, including the AT32AP7000 data sheet which can be found here:
http://www.atmel.com/dyn/products/datasheets.asp?family_id=682
Signed-off-by: Haavard Skinnemoen <haavard.skinnemoen@atmel.com>
Signed-off-by: Pierre Ossman <drzeus@drzeus.cx>
2008-06-30 10:35:03 -06:00
|
|
|
|
|
|
|
if (mmc->ios.bus_mode == MMC_BUSMODE_OPENDRAIN)
|
2011-08-11 09:25:41 -06:00
|
|
|
cmdr |= ATMCI_CMDR_OPDCMD;
|
atmel-mci: Driver for Atmel on-chip MMC controllers
This is a driver for the MMC controller on the AP7000 chips from
Atmel. It should in theory work on AT91 systems too with some
tweaking, but since the DMA interface is quite different, it's not
entirely clear if it's worth merging this with the at91_mci driver.
This driver has been around for a while in BSPs and kernel sources
provided by Atmel, but this particular version uses the generic DMA
Engine framework (with the slave extensions) instead of an
avr32-only DMA controller framework.
This driver can also use PIO transfers when no DMA channels are
available, and for transfers where using DMA may be difficult or
impractical for some reason (e.g. the DMA setup overhead is usually
not worth it for very short transfers, and badly aligned buffers or
lengths are difficult to handle.)
Currently, the driver only support PIO transfers. DMA support has been
split out to a separate patch to hopefully make it easier to review.
The driver has been tested using mmc-block and ext3fs on several SD,
SDHC and MMC+ cards. Reads and writes work fine, with read transfer
rates up to 3.5 MiB/s on fast cards with debugging disabled.
The driver has also been tested using the mmc_test module on the same
cards. All tests except 7, 9, 15 and 17 succeed. The first two are
unsupported by all the cards I have, so I don't know if the driver
handles this correctly. The last two fail because the hardware flags a
Data CRC Error instead of a Data Timeout error. I'm not sure how to deal
with that.
Documentation for this controller can be found in many data sheets from
Atmel, including the AT32AP7000 data sheet which can be found here:
http://www.atmel.com/dyn/products/datasheets.asp?family_id=682
Signed-off-by: Haavard Skinnemoen <haavard.skinnemoen@atmel.com>
Signed-off-by: Pierre Ossman <drzeus@drzeus.cx>
2008-06-30 10:35:03 -06:00
|
|
|
|
|
|
|
data = cmd->data;
|
|
|
|
if (data) {
|
2011-08-11 09:25:41 -06:00
|
|
|
cmdr |= ATMCI_CMDR_START_XFER;
|
2010-12-10 11:14:32 -07:00
|
|
|
|
|
|
|
if (cmd->opcode == SD_IO_RW_EXTENDED) {
|
2011-08-11 09:25:41 -06:00
|
|
|
cmdr |= ATMCI_CMDR_SDIO_BLOCK;
|
2010-12-10 11:14:32 -07:00
|
|
|
} else {
|
2016-02-01 05:07:26 -07:00
|
|
|
if (data->blocks > 1)
|
2011-08-11 09:25:41 -06:00
|
|
|
cmdr |= ATMCI_CMDR_MULTI_BLOCK;
|
2010-12-10 11:14:32 -07:00
|
|
|
else
|
2011-08-11 09:25:41 -06:00
|
|
|
cmdr |= ATMCI_CMDR_BLOCK;
|
2010-12-10 11:14:32 -07:00
|
|
|
}
|
atmel-mci: Driver for Atmel on-chip MMC controllers
This is a driver for the MMC controller on the AP7000 chips from
Atmel. It should in theory work on AT91 systems too with some
tweaking, but since the DMA interface is quite different, it's not
entirely clear if it's worth merging this with the at91_mci driver.
This driver has been around for a while in BSPs and kernel sources
provided by Atmel, but this particular version uses the generic DMA
Engine framework (with the slave extensions) instead of an
avr32-only DMA controller framework.
This driver can also use PIO transfers when no DMA channels are
available, and for transfers where using DMA may be difficult or
impractical for some reason (e.g. the DMA setup overhead is usually
not worth it for very short transfers, and badly aligned buffers or
lengths are difficult to handle.)
Currently, the driver only support PIO transfers. DMA support has been
split out to a separate patch to hopefully make it easier to review.
The driver has been tested using mmc-block and ext3fs on several SD,
SDHC and MMC+ cards. Reads and writes work fine, with read transfer
rates up to 3.5 MiB/s on fast cards with debugging disabled.
The driver has also been tested using the mmc_test module on the same
cards. All tests except 7, 9, 15 and 17 succeed. The first two are
unsupported by all the cards I have, so I don't know if the driver
handles this correctly. The last two fail because the hardware flags a
Data CRC Error instead of a Data Timeout error. I'm not sure how to deal
with that.
Documentation for this controller can be found in many data sheets from
Atmel, including the AT32AP7000 data sheet which can be found here:
http://www.atmel.com/dyn/products/datasheets.asp?family_id=682
Signed-off-by: Haavard Skinnemoen <haavard.skinnemoen@atmel.com>
Signed-off-by: Pierre Ossman <drzeus@drzeus.cx>
2008-06-30 10:35:03 -06:00
|
|
|
|
|
|
|
if (data->flags & MMC_DATA_READ)
|
2011-08-11 09:25:41 -06:00
|
|
|
cmdr |= ATMCI_CMDR_TRDIR_READ;
|
atmel-mci: Driver for Atmel on-chip MMC controllers
This is a driver for the MMC controller on the AP7000 chips from
Atmel. It should in theory work on AT91 systems too with some
tweaking, but since the DMA interface is quite different, it's not
entirely clear if it's worth merging this with the at91_mci driver.
This driver has been around for a while in BSPs and kernel sources
provided by Atmel, but this particular version uses the generic DMA
Engine framework (with the slave extensions) instead of an
avr32-only DMA controller framework.
This driver can also use PIO transfers when no DMA channels are
available, and for transfers where using DMA may be difficult or
impractical for some reason (e.g. the DMA setup overhead is usually
not worth it for very short transfers, and badly aligned buffers or
lengths are difficult to handle.)
Currently, the driver only support PIO transfers. DMA support has been
split out to a separate patch to hopefully make it easier to review.
The driver has been tested using mmc-block and ext3fs on several SD,
SDHC and MMC+ cards. Reads and writes work fine, with read transfer
rates up to 3.5 MiB/s on fast cards with debugging disabled.
The driver has also been tested using the mmc_test module on the same
cards. All tests except 7, 9, 15 and 17 succeed. The first two are
unsupported by all the cards I have, so I don't know if the driver
handles this correctly. The last two fail because the hardware flags a
Data CRC Error instead of a Data Timeout error. I'm not sure how to deal
with that.
Documentation for this controller can be found in many data sheets from
Atmel, including the AT32AP7000 data sheet which can be found here:
http://www.atmel.com/dyn/products/datasheets.asp?family_id=682
Signed-off-by: Haavard Skinnemoen <haavard.skinnemoen@atmel.com>
Signed-off-by: Pierre Ossman <drzeus@drzeus.cx>
2008-06-30 10:35:03 -06:00
|
|
|
}
|
|
|
|
|
|
|
|
return cmdr;
|
|
|
|
}
|
|
|
|
|
2011-08-11 09:25:45 -06:00
|
|
|
static void atmci_send_command(struct atmel_mci *host,
|
atmel-mci: support multiple mmc slots
The Atmel MCI controller can drive multiple cards through separate sets
of pins, but only one at a time. This patch adds support for
multiplexing access to the controller so that multiple card slots can be
used as if they were hooked up to separate mmc controllers.
The atmel-mci driver registers each slot as a separate mmc_host. Both
access the same common controller state, but they also have some state
on their own for card detection/write protect handling, and separate
shadows of the MR and SDCR registers.
When one of the slots receives a request from the mmc core, the common
controller state is checked. If it's idle, the request is submitted
immediately. If not, the request is added to a queue. When a request is
done, the queue is checked and if there is a queued request, it is
submitted before the completion callback is called.
This patch also includes a few cleanups and fixes, including a locking
overhaul. I had to change the locking extensively in any case, so I
might as well try to get it right. The driver no longer takes any
irq-safe locks, which may or may not improve the overall system
performance.
This patch also adds a bit of documentation of the internal data
structures.
Signed-off-by: Haavard Skinnemoen <haavard.skinnemoen@atmel.com>
2008-09-17 12:53:55 -06:00
|
|
|
struct mmc_command *cmd, u32 cmd_flags)
|
atmel-mci: Driver for Atmel on-chip MMC controllers
This is a driver for the MMC controller on the AP7000 chips from
Atmel. It should in theory work on AT91 systems too with some
tweaking, but since the DMA interface is quite different, it's not
entirely clear if it's worth merging this with the at91_mci driver.
This driver has been around for a while in BSPs and kernel sources
provided by Atmel, but this particular version uses the generic DMA
Engine framework (with the slave extensions) instead of an
avr32-only DMA controller framework.
This driver can also use PIO transfers when no DMA channels are
available, and for transfers where using DMA may be difficult or
impractical for some reason (e.g. the DMA setup overhead is usually
not worth it for very short transfers, and badly aligned buffers or
lengths are difficult to handle.)
Currently, the driver only support PIO transfers. DMA support has been
split out to a separate patch to hopefully make it easier to review.
The driver has been tested using mmc-block and ext3fs on several SD,
SDHC and MMC+ cards. Reads and writes work fine, with read transfer
rates up to 3.5 MiB/s on fast cards with debugging disabled.
The driver has also been tested using the mmc_test module on the same
cards. All tests except 7, 9, 15 and 17 succeed. The first two are
unsupported by all the cards I have, so I don't know if the driver
handles this correctly. The last two fail because the hardware flags a
Data CRC Error instead of a Data Timeout error. I'm not sure how to deal
with that.
Documentation for this controller can be found in many data sheets from
Atmel, including the AT32AP7000 data sheet which can be found here:
http://www.atmel.com/dyn/products/datasheets.asp?family_id=682
Signed-off-by: Haavard Skinnemoen <haavard.skinnemoen@atmel.com>
Signed-off-by: Pierre Ossman <drzeus@drzeus.cx>
2008-06-30 10:35:03 -06:00
|
|
|
{
|
|
|
|
WARN_ON(host->cmd);
|
|
|
|
host->cmd = cmd;
|
|
|
|
|
atmel-mci: support multiple mmc slots
The Atmel MCI controller can drive multiple cards through separate sets
of pins, but only one at a time. This patch adds support for
multiplexing access to the controller so that multiple card slots can be
used as if they were hooked up to separate mmc controllers.
The atmel-mci driver registers each slot as a separate mmc_host. Both
access the same common controller state, but they also have some state
on their own for card detection/write protect handling, and separate
shadows of the MR and SDCR registers.
When one of the slots receives a request from the mmc core, the common
controller state is checked. If it's idle, the request is submitted
immediately. If not, the request is added to a queue. When a request is
done, the queue is checked and if there is a queued request, it is
submitted before the completion callback is called.
This patch also includes a few cleanups and fixes, including a locking
overhaul. I had to change the locking extensively in any case, so I
might as well try to get it right. The driver no longer takes any
irq-safe locks, which may or may not improve the overall system
performance.
This patch also adds a bit of documentation of the internal data
structures.
Signed-off-by: Haavard Skinnemoen <haavard.skinnemoen@atmel.com>
2008-09-17 12:53:55 -06:00
|
|
|
dev_vdbg(&host->pdev->dev,
|
atmel-mci: Driver for Atmel on-chip MMC controllers
This is a driver for the MMC controller on the AP7000 chips from
Atmel. It should in theory work on AT91 systems too with some
tweaking, but since the DMA interface is quite different, it's not
entirely clear if it's worth merging this with the at91_mci driver.
This driver has been around for a while in BSPs and kernel sources
provided by Atmel, but this particular version uses the generic DMA
Engine framework (with the slave extensions) instead of an
avr32-only DMA controller framework.
This driver can also use PIO transfers when no DMA channels are
available, and for transfers where using DMA may be difficult or
impractical for some reason (e.g. the DMA setup overhead is usually
not worth it for very short transfers, and badly aligned buffers or
lengths are difficult to handle.)
Currently, the driver only support PIO transfers. DMA support has been
split out to a separate patch to hopefully make it easier to review.
The driver has been tested using mmc-block and ext3fs on several SD,
SDHC and MMC+ cards. Reads and writes work fine, with read transfer
rates up to 3.5 MiB/s on fast cards with debugging disabled.
The driver has also been tested using the mmc_test module on the same
cards. All tests except 7, 9, 15 and 17 succeed. The first two are
unsupported by all the cards I have, so I don't know if the driver
handles this correctly. The last two fail because the hardware flags a
Data CRC Error instead of a Data Timeout error. I'm not sure how to deal
with that.
Documentation for this controller can be found in many data sheets from
Atmel, including the AT32AP7000 data sheet which can be found here:
http://www.atmel.com/dyn/products/datasheets.asp?family_id=682
Signed-off-by: Haavard Skinnemoen <haavard.skinnemoen@atmel.com>
Signed-off-by: Pierre Ossman <drzeus@drzeus.cx>
2008-06-30 10:35:03 -06:00
|
|
|
"start command: ARGR=0x%08x CMDR=0x%08x\n",
|
|
|
|
cmd->arg, cmd_flags);
|
|
|
|
|
2011-08-11 09:25:42 -06:00
|
|
|
atmci_writel(host, ATMCI_ARGR, cmd->arg);
|
|
|
|
atmci_writel(host, ATMCI_CMDR, cmd_flags);
|
atmel-mci: Driver for Atmel on-chip MMC controllers
This is a driver for the MMC controller on the AP7000 chips from
Atmel. It should in theory work on AT91 systems too with some
tweaking, but since the DMA interface is quite different, it's not
entirely clear if it's worth merging this with the at91_mci driver.
This driver has been around for a while in BSPs and kernel sources
provided by Atmel, but this particular version uses the generic DMA
Engine framework (with the slave extensions) instead of an
avr32-only DMA controller framework.
This driver can also use PIO transfers when no DMA channels are
available, and for transfers where using DMA may be difficult or
impractical for some reason (e.g. the DMA setup overhead is usually
not worth it for very short transfers, and badly aligned buffers or
lengths are difficult to handle.)
Currently, the driver only support PIO transfers. DMA support has been
split out to a separate patch to hopefully make it easier to review.
The driver has been tested using mmc-block and ext3fs on several SD,
SDHC and MMC+ cards. Reads and writes work fine, with read transfer
rates up to 3.5 MiB/s on fast cards with debugging disabled.
The driver has also been tested using the mmc_test module on the same
cards. All tests except 7, 9, 15 and 17 succeed. The first two are
unsupported by all the cards I have, so I don't know if the driver
handles this correctly. The last two fail because the hardware flags a
Data CRC Error instead of a Data Timeout error. I'm not sure how to deal
with that.
Documentation for this controller can be found in many data sheets from
Atmel, including the AT32AP7000 data sheet which can be found here:
http://www.atmel.com/dyn/products/datasheets.asp?family_id=682
Signed-off-by: Haavard Skinnemoen <haavard.skinnemoen@atmel.com>
Signed-off-by: Pierre Ossman <drzeus@drzeus.cx>
2008-06-30 10:35:03 -06:00
|
|
|
}
|
|
|
|
|
2011-08-11 09:25:41 -06:00
|
|
|
static void atmci_send_stop_cmd(struct atmel_mci *host, struct mmc_data *data)
|
atmel-mci: Driver for Atmel on-chip MMC controllers
This is a driver for the MMC controller on the AP7000 chips from
Atmel. It should in theory work on AT91 systems too with some
tweaking, but since the DMA interface is quite different, it's not
entirely clear if it's worth merging this with the at91_mci driver.
This driver has been around for a while in BSPs and kernel sources
provided by Atmel, but this particular version uses the generic DMA
Engine framework (with the slave extensions) instead of an
avr32-only DMA controller framework.
This driver can also use PIO transfers when no DMA channels are
available, and for transfers where using DMA may be difficult or
impractical for some reason (e.g. the DMA setup overhead is usually
not worth it for very short transfers, and badly aligned buffers or
lengths are difficult to handle.)
Currently, the driver only support PIO transfers. DMA support has been
split out to a separate patch to hopefully make it easier to review.
The driver has been tested using mmc-block and ext3fs on several SD,
SDHC and MMC+ cards. Reads and writes work fine, with read transfer
rates up to 3.5 MiB/s on fast cards with debugging disabled.
The driver has also been tested using the mmc_test module on the same
cards. All tests except 7, 9, 15 and 17 succeed. The first two are
unsupported by all the cards I have, so I don't know if the driver
handles this correctly. The last two fail because the hardware flags a
Data CRC Error instead of a Data Timeout error. I'm not sure how to deal
with that.
Documentation for this controller can be found in many data sheets from
Atmel, including the AT32AP7000 data sheet which can be found here:
http://www.atmel.com/dyn/products/datasheets.asp?family_id=682
Signed-off-by: Haavard Skinnemoen <haavard.skinnemoen@atmel.com>
Signed-off-by: Pierre Ossman <drzeus@drzeus.cx>
2008-06-30 10:35:03 -06:00
|
|
|
{
|
2012-05-16 07:26:01 -06:00
|
|
|
dev_dbg(&host->pdev->dev, "send stop command\n");
|
2011-08-11 09:25:45 -06:00
|
|
|
atmci_send_command(host, data->stop, host->stop_cmdr);
|
2011-08-11 09:25:42 -06:00
|
|
|
atmci_writel(host, ATMCI_IER, ATMCI_CMDRDY);
|
atmel-mci: Driver for Atmel on-chip MMC controllers
This is a driver for the MMC controller on the AP7000 chips from
Atmel. It should in theory work on AT91 systems too with some
tweaking, but since the DMA interface is quite different, it's not
entirely clear if it's worth merging this with the at91_mci driver.
This driver has been around for a while in BSPs and kernel sources
provided by Atmel, but this particular version uses the generic DMA
Engine framework (with the slave extensions) instead of an
avr32-only DMA controller framework.
This driver can also use PIO transfers when no DMA channels are
available, and for transfers where using DMA may be difficult or
impractical for some reason (e.g. the DMA setup overhead is usually
not worth it for very short transfers, and badly aligned buffers or
lengths are difficult to handle.)
Currently, the driver only support PIO transfers. DMA support has been
split out to a separate patch to hopefully make it easier to review.
The driver has been tested using mmc-block and ext3fs on several SD,
SDHC and MMC+ cards. Reads and writes work fine, with read transfer
rates up to 3.5 MiB/s on fast cards with debugging disabled.
The driver has also been tested using the mmc_test module on the same
cards. All tests except 7, 9, 15 and 17 succeed. The first two are
unsupported by all the cards I have, so I don't know if the driver
handles this correctly. The last two fail because the hardware flags a
Data CRC Error instead of a Data Timeout error. I'm not sure how to deal
with that.
Documentation for this controller can be found in many data sheets from
Atmel, including the AT32AP7000 data sheet which can be found here:
http://www.atmel.com/dyn/products/datasheets.asp?family_id=682
Signed-off-by: Haavard Skinnemoen <haavard.skinnemoen@atmel.com>
Signed-off-by: Pierre Ossman <drzeus@drzeus.cx>
2008-06-30 10:35:03 -06:00
|
|
|
}
|
|
|
|
|
2011-08-11 09:25:44 -06:00
|
|
|
/*
|
|
|
|
* Configure given PDC buffer taking care of alignement issues.
|
|
|
|
* Update host->data_size and host->sg.
|
|
|
|
*/
|
|
|
|
static void atmci_pdc_set_single_buf(struct atmel_mci *host,
|
|
|
|
enum atmci_xfer_dir dir, enum atmci_pdc_buf buf_nb)
|
|
|
|
{
|
|
|
|
u32 pointer_reg, counter_reg;
|
2012-05-16 07:25:58 -06:00
|
|
|
unsigned int buf_size;
|
2011-08-11 09:25:44 -06:00
|
|
|
|
|
|
|
if (dir == XFER_RECEIVE) {
|
|
|
|
pointer_reg = ATMEL_PDC_RPR;
|
|
|
|
counter_reg = ATMEL_PDC_RCR;
|
|
|
|
} else {
|
|
|
|
pointer_reg = ATMEL_PDC_TPR;
|
|
|
|
counter_reg = ATMEL_PDC_TCR;
|
|
|
|
}
|
|
|
|
|
|
|
|
if (buf_nb == PDC_SECOND_BUF) {
|
2011-08-11 09:25:46 -06:00
|
|
|
pointer_reg += ATMEL_PDC_SCND_BUF_OFF;
|
|
|
|
counter_reg += ATMEL_PDC_SCND_BUF_OFF;
|
2011-08-11 09:25:44 -06:00
|
|
|
}
|
|
|
|
|
2012-05-16 07:25:58 -06:00
|
|
|
if (!host->caps.has_rwproof) {
|
|
|
|
buf_size = host->buf_size;
|
|
|
|
atmci_writel(host, pointer_reg, host->buf_phys_addr);
|
|
|
|
} else {
|
|
|
|
buf_size = sg_dma_len(host->sg);
|
|
|
|
atmci_writel(host, pointer_reg, sg_dma_address(host->sg));
|
|
|
|
}
|
|
|
|
|
|
|
|
if (host->data_size <= buf_size) {
|
2011-08-11 09:25:44 -06:00
|
|
|
if (host->data_size & 0x3) {
|
|
|
|
/* If size is different from modulo 4, transfer bytes */
|
|
|
|
atmci_writel(host, counter_reg, host->data_size);
|
|
|
|
atmci_writel(host, ATMCI_MR, host->mode_reg | ATMCI_MR_PDCFBYTE);
|
|
|
|
} else {
|
|
|
|
/* Else transfer 32-bits words */
|
|
|
|
atmci_writel(host, counter_reg, host->data_size / 4);
|
|
|
|
}
|
|
|
|
host->data_size = 0;
|
|
|
|
} else {
|
|
|
|
/* We assume the size of a page is 32-bits aligned */
|
2011-08-11 09:25:47 -06:00
|
|
|
atmci_writel(host, counter_reg, sg_dma_len(host->sg) / 4);
|
|
|
|
host->data_size -= sg_dma_len(host->sg);
|
2011-08-11 09:25:44 -06:00
|
|
|
if (host->data_size)
|
|
|
|
host->sg = sg_next(host->sg);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Configure PDC buffer according to the data size ie configuring one or two
|
|
|
|
* buffers. Don't use this function if you want to configure only the second
|
|
|
|
* buffer. In this case, use atmci_pdc_set_single_buf.
|
|
|
|
*/
|
|
|
|
static void atmci_pdc_set_both_buf(struct atmel_mci *host, int dir)
|
2008-07-30 12:29:03 -06:00
|
|
|
{
|
2011-08-11 09:25:44 -06:00
|
|
|
atmci_pdc_set_single_buf(host, dir, PDC_FIRST_BUF);
|
|
|
|
if (host->data_size)
|
|
|
|
atmci_pdc_set_single_buf(host, dir, PDC_SECOND_BUF);
|
|
|
|
}
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Unmap sg lists, called when transfer is finished.
|
|
|
|
*/
|
|
|
|
static void atmci_pdc_cleanup(struct atmel_mci *host)
|
|
|
|
{
|
|
|
|
struct mmc_data *data = host->data;
|
2008-07-30 12:29:03 -06:00
|
|
|
|
2010-05-11 15:06:49 -06:00
|
|
|
if (data)
|
2011-08-11 09:25:44 -06:00
|
|
|
dma_unmap_sg(&host->pdev->dev,
|
|
|
|
data->sg, data->sg_len,
|
2017-03-26 12:45:56 -06:00
|
|
|
mmc_get_dma_dir(data));
|
2008-07-30 12:29:03 -06:00
|
|
|
}
|
|
|
|
|
2011-08-11 09:25:44 -06:00
|
|
|
/*
|
|
|
|
* Disable PDC transfers. Update pending flags to EVENT_XFER_COMPLETE after
|
|
|
|
* having received ATMCI_TXBUFE or ATMCI_RXBUFF interrupt. Enable ATMCI_NOTBUSY
|
|
|
|
* interrupt needed for both transfer directions.
|
|
|
|
*/
|
|
|
|
static void atmci_pdc_complete(struct atmel_mci *host)
|
2008-07-30 12:29:03 -06:00
|
|
|
{
|
2012-05-16 07:25:58 -06:00
|
|
|
int transfer_size = host->data->blocks * host->data->blksz;
|
2012-05-16 07:26:00 -06:00
|
|
|
int i;
|
2012-05-16 07:25:58 -06:00
|
|
|
|
2011-08-11 09:25:44 -06:00
|
|
|
atmci_writel(host, ATMEL_PDC_PTCR, ATMEL_PDC_RXTDIS | ATMEL_PDC_TXTDIS);
|
2012-05-16 07:25:58 -06:00
|
|
|
|
|
|
|
if ((!host->caps.has_rwproof)
|
2012-05-16 07:26:00 -06:00
|
|
|
&& (host->data->flags & MMC_DATA_READ)) {
|
|
|
|
if (host->caps.has_bad_data_ordering)
|
|
|
|
for (i = 0; i < transfer_size; i++)
|
|
|
|
host->buffer[i] = swab32(host->buffer[i]);
|
2012-05-16 07:25:58 -06:00
|
|
|
sg_copy_from_buffer(host->data->sg, host->data->sg_len,
|
|
|
|
host->buffer, transfer_size);
|
2012-05-16 07:26:00 -06:00
|
|
|
}
|
2012-05-16 07:25:58 -06:00
|
|
|
|
2011-08-11 09:25:44 -06:00
|
|
|
atmci_pdc_cleanup(host);
|
2008-07-30 12:29:03 -06:00
|
|
|
|
2014-05-06 09:43:26 -06:00
|
|
|
dev_dbg(&host->pdev->dev, "(%s) set pending xfer complete\n", __func__);
|
|
|
|
atmci_set_pending(host, EVENT_XFER_COMPLETE);
|
|
|
|
tasklet_schedule(&host->tasklet);
|
2008-07-30 12:29:03 -06:00
|
|
|
}
|
|
|
|
|
2011-08-11 09:25:44 -06:00
|
|
|
static void atmci_dma_cleanup(struct atmel_mci *host)
|
|
|
|
{
|
|
|
|
struct mmc_data *data = host->data;
|
|
|
|
|
|
|
|
if (data)
|
|
|
|
dma_unmap_sg(host->dma.chan->device->dev,
|
|
|
|
data->sg, data->sg_len,
|
2017-03-26 12:45:56 -06:00
|
|
|
mmc_get_dma_dir(data));
|
2011-08-11 09:25:44 -06:00
|
|
|
}
|
|
|
|
|
|
|
|
/*
|
|
|
|
* This function is called by the DMA driver from tasklet context.
|
|
|
|
*/
|
2008-07-30 12:29:03 -06:00
|
|
|
static void atmci_dma_complete(void *arg)
|
|
|
|
{
|
|
|
|
struct atmel_mci *host = arg;
|
|
|
|
struct mmc_data *data = host->data;
|
|
|
|
|
|
|
|
dev_vdbg(&host->pdev->dev, "DMA complete\n");
|
|
|
|
|
2012-08-30 10:34:38 -06:00
|
|
|
if (host->caps.has_dma_conf_reg)
|
2009-12-14 19:01:31 -07:00
|
|
|
/* Disable DMA hardware handshaking on MCI */
|
2011-08-11 09:25:42 -06:00
|
|
|
atmci_writel(host, ATMCI_DMA, atmci_readl(host, ATMCI_DMA) & ~ATMCI_DMAEN);
|
2009-12-14 19:01:31 -07:00
|
|
|
|
2008-07-30 12:29:03 -06:00
|
|
|
atmci_dma_cleanup(host);
|
|
|
|
|
|
|
|
/*
|
|
|
|
* If the card was removed, data will be NULL. No point trying
|
|
|
|
* to send the stop command or waiting for NBUSY in this case.
|
|
|
|
*/
|
|
|
|
if (data) {
|
2012-05-16 07:26:01 -06:00
|
|
|
dev_dbg(&host->pdev->dev,
|
|
|
|
"(%s) set pending xfer complete\n", __func__);
|
2008-07-30 12:29:03 -06:00
|
|
|
atmci_set_pending(host, EVENT_XFER_COMPLETE);
|
|
|
|
tasklet_schedule(&host->tasklet);
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Regardless of what the documentation says, we have
|
|
|
|
* to wait for NOTBUSY even after block read
|
|
|
|
* operations.
|
|
|
|
*
|
|
|
|
* When the DMA transfer is complete, the controller
|
|
|
|
* may still be reading the CRC from the card, i.e.
|
|
|
|
* the data transfer is still in progress and we
|
|
|
|
* haven't seen all the potential error bits yet.
|
|
|
|
*
|
|
|
|
* The interrupt handler will schedule a different
|
|
|
|
* tasklet to finish things up when the data transfer
|
|
|
|
* is completely done.
|
|
|
|
*
|
|
|
|
* We may not complete the mmc request here anyway
|
|
|
|
* because the mmc layer may call back and cause us to
|
|
|
|
* violate the "don't submit new operations from the
|
|
|
|
* completion callback" rule of the dma engine
|
|
|
|
* framework.
|
|
|
|
*/
|
2011-08-11 09:25:42 -06:00
|
|
|
atmci_writel(host, ATMCI_IER, ATMCI_NOTBUSY);
|
2008-07-30 12:29:03 -06:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2011-08-11 09:25:44 -06:00
|
|
|
/*
|
|
|
|
* Returns a mask of interrupt flags to be enabled after the whole
|
|
|
|
* request has been prepared.
|
|
|
|
*/
|
|
|
|
static u32 atmci_prepare_data(struct atmel_mci *host, struct mmc_data *data)
|
|
|
|
{
|
|
|
|
u32 iflags;
|
|
|
|
|
|
|
|
data->error = -EINPROGRESS;
|
|
|
|
|
|
|
|
host->sg = data->sg;
|
2013-04-08 10:05:47 -06:00
|
|
|
host->sg_len = data->sg_len;
|
2011-08-11 09:25:44 -06:00
|
|
|
host->data = data;
|
|
|
|
host->data_chan = NULL;
|
|
|
|
|
|
|
|
iflags = ATMCI_DATA_ERROR_FLAGS;
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Errata: MMC data write operation with less than 12
|
|
|
|
* bytes is impossible.
|
|
|
|
*
|
|
|
|
* Errata: MCI Transmit Data Register (TDR) FIFO
|
|
|
|
* corruption when length is not multiple of 4.
|
|
|
|
*/
|
|
|
|
if (data->blocks * data->blksz < 12
|
|
|
|
|| (data->blocks * data->blksz) & 3)
|
|
|
|
host->need_reset = true;
|
|
|
|
|
|
|
|
host->pio_offset = 0;
|
|
|
|
if (data->flags & MMC_DATA_READ)
|
|
|
|
iflags |= ATMCI_RXRDY;
|
|
|
|
else
|
|
|
|
iflags |= ATMCI_TXRDY;
|
|
|
|
|
|
|
|
return iflags;
|
|
|
|
}
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Set interrupt flags and set block length into the MCI mode register even
|
|
|
|
* if this value is also accessible in the MCI block register. It seems to be
|
|
|
|
* necessary before the High Speed MCI version. It also map sg and configure
|
|
|
|
* PDC registers.
|
|
|
|
*/
|
|
|
|
static u32
|
|
|
|
atmci_prepare_data_pdc(struct atmel_mci *host, struct mmc_data *data)
|
|
|
|
{
|
|
|
|
u32 iflags, tmp;
|
|
|
|
unsigned int sg_len;
|
2012-05-16 07:26:00 -06:00
|
|
|
int i;
|
2011-08-11 09:25:44 -06:00
|
|
|
|
|
|
|
data->error = -EINPROGRESS;
|
|
|
|
|
|
|
|
host->data = data;
|
|
|
|
host->sg = data->sg;
|
|
|
|
iflags = ATMCI_DATA_ERROR_FLAGS;
|
|
|
|
|
|
|
|
/* Enable pdc mode */
|
|
|
|
atmci_writel(host, ATMCI_MR, host->mode_reg | ATMCI_MR_PDCMODE);
|
|
|
|
|
2017-03-26 12:45:56 -06:00
|
|
|
if (data->flags & MMC_DATA_READ)
|
2011-08-11 09:25:44 -06:00
|
|
|
iflags |= ATMCI_ENDRX | ATMCI_RXBUFF;
|
2017-03-26 12:45:56 -06:00
|
|
|
else
|
2012-05-16 07:25:59 -06:00
|
|
|
iflags |= ATMCI_ENDTX | ATMCI_TXBUFE | ATMCI_BLKE;
|
2011-08-11 09:25:44 -06:00
|
|
|
|
|
|
|
/* Set BLKLEN */
|
|
|
|
tmp = atmci_readl(host, ATMCI_MR);
|
|
|
|
tmp &= 0x0000ffff;
|
|
|
|
tmp |= ATMCI_BLKLEN(data->blksz);
|
|
|
|
atmci_writel(host, ATMCI_MR, tmp);
|
|
|
|
|
|
|
|
/* Configure PDC */
|
|
|
|
host->data_size = data->blocks * data->blksz;
|
2017-03-26 12:45:56 -06:00
|
|
|
sg_len = dma_map_sg(&host->pdev->dev, data->sg, data->sg_len,
|
|
|
|
mmc_get_dma_dir(data));
|
2012-05-16 07:25:58 -06:00
|
|
|
|
|
|
|
if ((!host->caps.has_rwproof)
|
2012-05-16 07:26:00 -06:00
|
|
|
&& (host->data->flags & MMC_DATA_WRITE)) {
|
2012-05-16 07:25:58 -06:00
|
|
|
sg_copy_to_buffer(host->data->sg, host->data->sg_len,
|
|
|
|
host->buffer, host->data_size);
|
2012-05-16 07:26:00 -06:00
|
|
|
if (host->caps.has_bad_data_ordering)
|
|
|
|
for (i = 0; i < host->data_size; i++)
|
|
|
|
host->buffer[i] = swab32(host->buffer[i]);
|
|
|
|
}
|
2012-05-16 07:25:58 -06:00
|
|
|
|
2011-08-11 09:25:44 -06:00
|
|
|
if (host->data_size)
|
2017-03-26 12:45:56 -06:00
|
|
|
atmci_pdc_set_both_buf(host, data->flags & MMC_DATA_READ ?
|
|
|
|
XFER_RECEIVE : XFER_TRANSMIT);
|
2011-08-11 09:25:44 -06:00
|
|
|
return iflags;
|
|
|
|
}
|
|
|
|
|
|
|
|
static u32
|
2009-12-14 19:01:31 -07:00
|
|
|
atmci_prepare_data_dma(struct atmel_mci *host, struct mmc_data *data)
|
2008-07-30 12:29:03 -06:00
|
|
|
{
|
|
|
|
struct dma_chan *chan;
|
|
|
|
struct dma_async_tx_descriptor *desc;
|
|
|
|
struct scatterlist *sg;
|
|
|
|
unsigned int i;
|
2011-10-13 23:15:11 -06:00
|
|
|
enum dma_transfer_direction slave_dirn;
|
2009-09-08 18:53:05 -06:00
|
|
|
unsigned int sglen;
|
2012-06-06 04:19:44 -06:00
|
|
|
u32 maxburst;
|
2011-08-11 09:25:44 -06:00
|
|
|
u32 iflags;
|
|
|
|
|
|
|
|
data->error = -EINPROGRESS;
|
|
|
|
|
|
|
|
WARN_ON(host->data);
|
|
|
|
host->sg = NULL;
|
|
|
|
host->data = data;
|
|
|
|
|
|
|
|
iflags = ATMCI_DATA_ERROR_FLAGS;
|
2008-07-30 12:29:03 -06:00
|
|
|
|
|
|
|
/*
|
|
|
|
* We don't do DMA on "complex" transfers, i.e. with
|
|
|
|
* non-word-aligned buffers or lengths. Also, we don't bother
|
|
|
|
* with all the DMA setup overhead for short transfers.
|
|
|
|
*/
|
2011-08-11 09:25:44 -06:00
|
|
|
if (data->blocks * data->blksz < ATMCI_DMA_THRESHOLD)
|
|
|
|
return atmci_prepare_data(host, data);
|
2008-07-30 12:29:03 -06:00
|
|
|
if (data->blksz & 3)
|
2011-08-11 09:25:44 -06:00
|
|
|
return atmci_prepare_data(host, data);
|
2008-07-30 12:29:03 -06:00
|
|
|
|
|
|
|
for_each_sg(data->sg, sg, data->sg_len, i) {
|
|
|
|
if (sg->offset & 3 || sg->length & 3)
|
2011-08-11 09:25:44 -06:00
|
|
|
return atmci_prepare_data(host, data);
|
2008-07-30 12:29:03 -06:00
|
|
|
}
|
|
|
|
|
|
|
|
/* If we don't have a channel, we can't do DMA */
|
|
|
|
chan = host->dma.chan;
|
2009-01-06 11:38:14 -07:00
|
|
|
if (chan)
|
2008-07-30 12:29:03 -06:00
|
|
|
host->data_chan = chan;
|
|
|
|
|
|
|
|
if (!chan)
|
|
|
|
return -ENODEV;
|
|
|
|
|
2011-10-13 23:15:11 -06:00
|
|
|
if (data->flags & MMC_DATA_READ) {
|
2012-02-01 03:42:27 -07:00
|
|
|
host->dma_conf.direction = slave_dirn = DMA_DEV_TO_MEM;
|
2015-11-23 08:27:32 -07:00
|
|
|
maxburst = atmci_convert_chksize(host,
|
|
|
|
host->dma_conf.src_maxburst);
|
2011-10-13 23:15:11 -06:00
|
|
|
} else {
|
2012-02-01 03:42:27 -07:00
|
|
|
host->dma_conf.direction = slave_dirn = DMA_MEM_TO_DEV;
|
2015-11-23 08:27:32 -07:00
|
|
|
maxburst = atmci_convert_chksize(host,
|
|
|
|
host->dma_conf.dst_maxburst);
|
2011-10-13 23:15:11 -06:00
|
|
|
}
|
2008-07-30 12:29:03 -06:00
|
|
|
|
2012-08-30 10:34:38 -06:00
|
|
|
if (host->caps.has_dma_conf_reg)
|
|
|
|
atmci_writel(host, ATMCI_DMA, ATMCI_DMA_CHKSIZE(maxburst) |
|
|
|
|
ATMCI_DMAEN);
|
2012-06-06 04:19:44 -06:00
|
|
|
|
2011-02-10 08:08:06 -07:00
|
|
|
sglen = dma_map_sg(chan->device->dev, data->sg,
|
2017-03-26 12:45:56 -06:00
|
|
|
data->sg_len, mmc_get_dma_dir(data));
|
2011-02-10 08:08:16 -07:00
|
|
|
|
2012-02-01 03:42:27 -07:00
|
|
|
dmaengine_slave_config(chan, &host->dma_conf);
|
2012-03-08 14:11:18 -07:00
|
|
|
desc = dmaengine_prep_slave_sg(chan,
|
2011-10-13 23:15:11 -06:00
|
|
|
data->sg, sglen, slave_dirn,
|
2008-07-30 12:29:03 -06:00
|
|
|
DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
|
|
|
|
if (!desc)
|
2009-09-08 18:53:05 -06:00
|
|
|
goto unmap_exit;
|
2008-07-30 12:29:03 -06:00
|
|
|
|
|
|
|
host->dma.data_desc = desc;
|
|
|
|
desc->callback = atmci_dma_complete;
|
|
|
|
desc->callback_param = host;
|
|
|
|
|
2011-08-11 09:25:44 -06:00
|
|
|
return iflags;
|
2009-09-08 18:53:05 -06:00
|
|
|
unmap_exit:
|
2017-03-26 12:45:56 -06:00
|
|
|
dma_unmap_sg(chan->device->dev, data->sg, data->sg_len,
|
|
|
|
mmc_get_dma_dir(data));
|
2009-09-08 18:53:05 -06:00
|
|
|
return -ENOMEM;
|
2008-07-30 12:29:03 -06:00
|
|
|
}
|
|
|
|
|
2011-08-11 09:25:44 -06:00
|
|
|
static void
|
|
|
|
atmci_submit_data(struct atmel_mci *host, struct mmc_data *data)
|
|
|
|
{
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Start PDC according to transfer direction.
|
|
|
|
*/
|
|
|
|
static void
|
|
|
|
atmci_submit_data_pdc(struct atmel_mci *host, struct mmc_data *data)
|
|
|
|
{
|
|
|
|
if (data->flags & MMC_DATA_READ)
|
|
|
|
atmci_writel(host, ATMEL_PDC_PTCR, ATMEL_PDC_RXTEN);
|
|
|
|
else
|
|
|
|
atmci_writel(host, ATMEL_PDC_PTCR, ATMEL_PDC_TXTEN);
|
|
|
|
}
|
|
|
|
|
|
|
|
static void
|
|
|
|
atmci_submit_data_dma(struct atmel_mci *host, struct mmc_data *data)
|
2009-12-14 19:01:31 -07:00
|
|
|
{
|
|
|
|
struct dma_chan *chan = host->data_chan;
|
|
|
|
struct dma_async_tx_descriptor *desc = host->dma.data_desc;
|
|
|
|
|
|
|
|
if (chan) {
|
2011-02-10 08:08:26 -07:00
|
|
|
dmaengine_submit(desc);
|
|
|
|
dma_async_issue_pending(chan);
|
2009-12-14 19:01:31 -07:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2011-08-11 09:25:44 -06:00
|
|
|
static void atmci_stop_transfer(struct atmel_mci *host)
|
2008-07-30 12:29:03 -06:00
|
|
|
{
|
2012-05-16 07:26:01 -06:00
|
|
|
dev_dbg(&host->pdev->dev,
|
|
|
|
"(%s) set pending xfer complete\n", __func__);
|
2008-07-30 12:29:03 -06:00
|
|
|
atmci_set_pending(host, EVENT_XFER_COMPLETE);
|
2011-08-11 09:25:42 -06:00
|
|
|
atmci_writel(host, ATMCI_IER, ATMCI_NOTBUSY);
|
2008-07-30 12:29:03 -06:00
|
|
|
}
|
|
|
|
|
atmel-mci: Driver for Atmel on-chip MMC controllers
This is a driver for the MMC controller on the AP7000 chips from
Atmel. It should in theory work on AT91 systems too with some
tweaking, but since the DMA interface is quite different, it's not
entirely clear if it's worth merging this with the at91_mci driver.
This driver has been around for a while in BSPs and kernel sources
provided by Atmel, but this particular version uses the generic DMA
Engine framework (with the slave extensions) instead of an
avr32-only DMA controller framework.
This driver can also use PIO transfers when no DMA channels are
available, and for transfers where using DMA may be difficult or
impractical for some reason (e.g. the DMA setup overhead is usually
not worth it for very short transfers, and badly aligned buffers or
lengths are difficult to handle.)
Currently, the driver only support PIO transfers. DMA support has been
split out to a separate patch to hopefully make it easier to review.
The driver has been tested using mmc-block and ext3fs on several SD,
SDHC and MMC+ cards. Reads and writes work fine, with read transfer
rates up to 3.5 MiB/s on fast cards with debugging disabled.
The driver has also been tested using the mmc_test module on the same
cards. All tests except 7, 9, 15 and 17 succeed. The first two are
unsupported by all the cards I have, so I don't know if the driver
handles this correctly. The last two fail because the hardware flags a
Data CRC Error instead of a Data Timeout error. I'm not sure how to deal
with that.
Documentation for this controller can be found in many data sheets from
Atmel, including the AT32AP7000 data sheet which can be found here:
http://www.atmel.com/dyn/products/datasheets.asp?family_id=682
Signed-off-by: Haavard Skinnemoen <haavard.skinnemoen@atmel.com>
Signed-off-by: Pierre Ossman <drzeus@drzeus.cx>
2008-06-30 10:35:03 -06:00
|
|
|
/*
|
2012-08-05 08:25:40 -06:00
|
|
|
* Stop data transfer because error(s) occurred.
|
atmel-mci: Driver for Atmel on-chip MMC controllers
This is a driver for the MMC controller on the AP7000 chips from
Atmel. It should in theory work on AT91 systems too with some
tweaking, but since the DMA interface is quite different, it's not
entirely clear if it's worth merging this with the at91_mci driver.
This driver has been around for a while in BSPs and kernel sources
provided by Atmel, but this particular version uses the generic DMA
Engine framework (with the slave extensions) instead of an
avr32-only DMA controller framework.
This driver can also use PIO transfers when no DMA channels are
available, and for transfers where using DMA may be difficult or
impractical for some reason (e.g. the DMA setup overhead is usually
not worth it for very short transfers, and badly aligned buffers or
lengths are difficult to handle.)
Currently, the driver only support PIO transfers. DMA support has been
split out to a separate patch to hopefully make it easier to review.
The driver has been tested using mmc-block and ext3fs on several SD,
SDHC and MMC+ cards. Reads and writes work fine, with read transfer
rates up to 3.5 MiB/s on fast cards with debugging disabled.
The driver has also been tested using the mmc_test module on the same
cards. All tests except 7, 9, 15 and 17 succeed. The first two are
unsupported by all the cards I have, so I don't know if the driver
handles this correctly. The last two fail because the hardware flags a
Data CRC Error instead of a Data Timeout error. I'm not sure how to deal
with that.
Documentation for this controller can be found in many data sheets from
Atmel, including the AT32AP7000 data sheet which can be found here:
http://www.atmel.com/dyn/products/datasheets.asp?family_id=682
Signed-off-by: Haavard Skinnemoen <haavard.skinnemoen@atmel.com>
Signed-off-by: Pierre Ossman <drzeus@drzeus.cx>
2008-06-30 10:35:03 -06:00
|
|
|
*/
|
2011-08-11 09:25:44 -06:00
|
|
|
static void atmci_stop_transfer_pdc(struct atmel_mci *host)
|
atmel-mci: Driver for Atmel on-chip MMC controllers
This is a driver for the MMC controller on the AP7000 chips from
Atmel. It should in theory work on AT91 systems too with some
tweaking, but since the DMA interface is quite different, it's not
entirely clear if it's worth merging this with the at91_mci driver.
This driver has been around for a while in BSPs and kernel sources
provided by Atmel, but this particular version uses the generic DMA
Engine framework (with the slave extensions) instead of an
avr32-only DMA controller framework.
This driver can also use PIO transfers when no DMA channels are
available, and for transfers where using DMA may be difficult or
impractical for some reason (e.g. the DMA setup overhead is usually
not worth it for very short transfers, and badly aligned buffers or
lengths are difficult to handle.)
Currently, the driver only support PIO transfers. DMA support has been
split out to a separate patch to hopefully make it easier to review.
The driver has been tested using mmc-block and ext3fs on several SD,
SDHC and MMC+ cards. Reads and writes work fine, with read transfer
rates up to 3.5 MiB/s on fast cards with debugging disabled.
The driver has also been tested using the mmc_test module on the same
cards. All tests except 7, 9, 15 and 17 succeed. The first two are
unsupported by all the cards I have, so I don't know if the driver
handles this correctly. The last two fail because the hardware flags a
Data CRC Error instead of a Data Timeout error. I'm not sure how to deal
with that.
Documentation for this controller can be found in many data sheets from
Atmel, including the AT32AP7000 data sheet which can be found here:
http://www.atmel.com/dyn/products/datasheets.asp?family_id=682
Signed-off-by: Haavard Skinnemoen <haavard.skinnemoen@atmel.com>
Signed-off-by: Pierre Ossman <drzeus@drzeus.cx>
2008-06-30 10:35:03 -06:00
|
|
|
{
|
2012-05-16 07:25:59 -06:00
|
|
|
atmci_writel(host, ATMEL_PDC_PTCR, ATMEL_PDC_RXTDIS | ATMEL_PDC_TXTDIS);
|
2011-08-11 09:25:44 -06:00
|
|
|
}
|
atmel-mci: support multiple mmc slots
The Atmel MCI controller can drive multiple cards through separate sets
of pins, but only one at a time. This patch adds support for
multiplexing access to the controller so that multiple card slots can be
used as if they were hooked up to separate mmc controllers.
The atmel-mci driver registers each slot as a separate mmc_host. Both
access the same common controller state, but they also have some state
on their own for card detection/write protect handling, and separate
shadows of the MR and SDCR registers.
When one of the slots receives a request from the mmc core, the common
controller state is checked. If it's idle, the request is submitted
immediately. If not, the request is added to a queue. When a request is
done, the queue is checked and if there is a queued request, it is
submitted before the completion callback is called.
This patch also includes a few cleanups and fixes, including a locking
overhaul. I had to change the locking extensively in any case, so I
might as well try to get it right. The driver no longer takes any
irq-safe locks, which may or may not improve the overall system
performance.
This patch also adds a bit of documentation of the internal data
structures.
Signed-off-by: Haavard Skinnemoen <haavard.skinnemoen@atmel.com>
2008-09-17 12:53:55 -06:00
|
|
|
|
2011-08-11 09:25:44 -06:00
|
|
|
static void atmci_stop_transfer_dma(struct atmel_mci *host)
|
|
|
|
{
|
|
|
|
struct dma_chan *chan = host->data_chan;
|
atmel-mci: support multiple mmc slots
The Atmel MCI controller can drive multiple cards through separate sets
of pins, but only one at a time. This patch adds support for
multiplexing access to the controller so that multiple card slots can be
used as if they were hooked up to separate mmc controllers.
The atmel-mci driver registers each slot as a separate mmc_host. Both
access the same common controller state, but they also have some state
on their own for card detection/write protect handling, and separate
shadows of the MR and SDCR registers.
When one of the slots receives a request from the mmc core, the common
controller state is checked. If it's idle, the request is submitted
immediately. If not, the request is added to a queue. When a request is
done, the queue is checked and if there is a queued request, it is
submitted before the completion callback is called.
This patch also includes a few cleanups and fixes, including a locking
overhaul. I had to change the locking extensively in any case, so I
might as well try to get it right. The driver no longer takes any
irq-safe locks, which may or may not improve the overall system
performance.
This patch also adds a bit of documentation of the internal data
structures.
Signed-off-by: Haavard Skinnemoen <haavard.skinnemoen@atmel.com>
2008-09-17 12:53:55 -06:00
|
|
|
|
2011-08-11 09:25:44 -06:00
|
|
|
if (chan) {
|
|
|
|
dmaengine_terminate_all(chan);
|
|
|
|
atmci_dma_cleanup(host);
|
|
|
|
} else {
|
|
|
|
/* Data transfer was stopped by the interrupt handler */
|
2012-05-16 07:26:01 -06:00
|
|
|
dev_dbg(&host->pdev->dev,
|
|
|
|
"(%s) set pending xfer complete\n", __func__);
|
2011-08-11 09:25:44 -06:00
|
|
|
atmci_set_pending(host, EVENT_XFER_COMPLETE);
|
|
|
|
atmci_writel(host, ATMCI_IER, ATMCI_NOTBUSY);
|
2008-07-30 12:29:03 -06:00
|
|
|
}
|
atmel-mci: Driver for Atmel on-chip MMC controllers
This is a driver for the MMC controller on the AP7000 chips from
Atmel. It should in theory work on AT91 systems too with some
tweaking, but since the DMA interface is quite different, it's not
entirely clear if it's worth merging this with the at91_mci driver.
This driver has been around for a while in BSPs and kernel sources
provided by Atmel, but this particular version uses the generic DMA
Engine framework (with the slave extensions) instead of an
avr32-only DMA controller framework.
This driver can also use PIO transfers when no DMA channels are
available, and for transfers where using DMA may be difficult or
impractical for some reason (e.g. the DMA setup overhead is usually
not worth it for very short transfers, and badly aligned buffers or
lengths are difficult to handle.)
Currently, the driver only support PIO transfers. DMA support has been
split out to a separate patch to hopefully make it easier to review.
The driver has been tested using mmc-block and ext3fs on several SD,
SDHC and MMC+ cards. Reads and writes work fine, with read transfer
rates up to 3.5 MiB/s on fast cards with debugging disabled.
The driver has also been tested using the mmc_test module on the same
cards. All tests except 7, 9, 15 and 17 succeed. The first two are
unsupported by all the cards I have, so I don't know if the driver
handles this correctly. The last two fail because the hardware flags a
Data CRC Error instead of a Data Timeout error. I'm not sure how to deal
with that.
Documentation for this controller can be found in many data sheets from
Atmel, including the AT32AP7000 data sheet which can be found here:
http://www.atmel.com/dyn/products/datasheets.asp?family_id=682
Signed-off-by: Haavard Skinnemoen <haavard.skinnemoen@atmel.com>
Signed-off-by: Pierre Ossman <drzeus@drzeus.cx>
2008-06-30 10:35:03 -06:00
|
|
|
}
|
|
|
|
|
2011-08-11 09:25:44 -06:00
|
|
|
/*
|
|
|
|
* Start a request: prepare data if needed, prepare the command and activate
|
|
|
|
* interrupts.
|
|
|
|
*/
|
atmel-mci: support multiple mmc slots
The Atmel MCI controller can drive multiple cards through separate sets
of pins, but only one at a time. This patch adds support for
multiplexing access to the controller so that multiple card slots can be
used as if they were hooked up to separate mmc controllers.
The atmel-mci driver registers each slot as a separate mmc_host. Both
access the same common controller state, but they also have some state
on their own for card detection/write protect handling, and separate
shadows of the MR and SDCR registers.
When one of the slots receives a request from the mmc core, the common
controller state is checked. If it's idle, the request is submitted
immediately. If not, the request is added to a queue. When a request is
done, the queue is checked and if there is a queued request, it is
submitted before the completion callback is called.
This patch also includes a few cleanups and fixes, including a locking
overhaul. I had to change the locking extensively in any case, so I
might as well try to get it right. The driver no longer takes any
irq-safe locks, which may or may not improve the overall system
performance.
This patch also adds a bit of documentation of the internal data
structures.
Signed-off-by: Haavard Skinnemoen <haavard.skinnemoen@atmel.com>
2008-09-17 12:53:55 -06:00
|
|
|
static void atmci_start_request(struct atmel_mci *host,
|
|
|
|
struct atmel_mci_slot *slot)
|
atmel-mci: Driver for Atmel on-chip MMC controllers
This is a driver for the MMC controller on the AP7000 chips from
Atmel. It should in theory work on AT91 systems too with some
tweaking, but since the DMA interface is quite different, it's not
entirely clear if it's worth merging this with the at91_mci driver.
This driver has been around for a while in BSPs and kernel sources
provided by Atmel, but this particular version uses the generic DMA
Engine framework (with the slave extensions) instead of an
avr32-only DMA controller framework.
This driver can also use PIO transfers when no DMA channels are
available, and for transfers where using DMA may be difficult or
impractical for some reason (e.g. the DMA setup overhead is usually
not worth it for very short transfers, and badly aligned buffers or
lengths are difficult to handle.)
Currently, the driver only support PIO transfers. DMA support has been
split out to a separate patch to hopefully make it easier to review.
The driver has been tested using mmc-block and ext3fs on several SD,
SDHC and MMC+ cards. Reads and writes work fine, with read transfer
rates up to 3.5 MiB/s on fast cards with debugging disabled.
The driver has also been tested using the mmc_test module on the same
cards. All tests except 7, 9, 15 and 17 succeed. The first two are
unsupported by all the cards I have, so I don't know if the driver
handles this correctly. The last two fail because the hardware flags a
Data CRC Error instead of a Data Timeout error. I'm not sure how to deal
with that.
Documentation for this controller can be found in many data sheets from
Atmel, including the AT32AP7000 data sheet which can be found here:
http://www.atmel.com/dyn/products/datasheets.asp?family_id=682
Signed-off-by: Haavard Skinnemoen <haavard.skinnemoen@atmel.com>
Signed-off-by: Pierre Ossman <drzeus@drzeus.cx>
2008-06-30 10:35:03 -06:00
|
|
|
{
|
atmel-mci: support multiple mmc slots
The Atmel MCI controller can drive multiple cards through separate sets
of pins, but only one at a time. This patch adds support for
multiplexing access to the controller so that multiple card slots can be
used as if they were hooked up to separate mmc controllers.
The atmel-mci driver registers each slot as a separate mmc_host. Both
access the same common controller state, but they also have some state
on their own for card detection/write protect handling, and separate
shadows of the MR and SDCR registers.
When one of the slots receives a request from the mmc core, the common
controller state is checked. If it's idle, the request is submitted
immediately. If not, the request is added to a queue. When a request is
done, the queue is checked and if there is a queued request, it is
submitted before the completion callback is called.
This patch also includes a few cleanups and fixes, including a locking
overhaul. I had to change the locking extensively in any case, so I
might as well try to get it right. The driver no longer takes any
irq-safe locks, which may or may not improve the overall system
performance.
This patch also adds a bit of documentation of the internal data
structures.
Signed-off-by: Haavard Skinnemoen <haavard.skinnemoen@atmel.com>
2008-09-17 12:53:55 -06:00
|
|
|
struct mmc_request *mrq;
|
atmel-mci: Driver for Atmel on-chip MMC controllers
This is a driver for the MMC controller on the AP7000 chips from
Atmel. It should in theory work on AT91 systems too with some
tweaking, but since the DMA interface is quite different, it's not
entirely clear if it's worth merging this with the at91_mci driver.
This driver has been around for a while in BSPs and kernel sources
provided by Atmel, but this particular version uses the generic DMA
Engine framework (with the slave extensions) instead of an
avr32-only DMA controller framework.
This driver can also use PIO transfers when no DMA channels are
available, and for transfers where using DMA may be difficult or
impractical for some reason (e.g. the DMA setup overhead is usually
not worth it for very short transfers, and badly aligned buffers or
lengths are difficult to handle.)
Currently, the driver only support PIO transfers. DMA support has been
split out to a separate patch to hopefully make it easier to review.
The driver has been tested using mmc-block and ext3fs on several SD,
SDHC and MMC+ cards. Reads and writes work fine, with read transfer
rates up to 3.5 MiB/s on fast cards with debugging disabled.
The driver has also been tested using the mmc_test module on the same
cards. All tests except 7, 9, 15 and 17 succeed. The first two are
unsupported by all the cards I have, so I don't know if the driver
handles this correctly. The last two fail because the hardware flags a
Data CRC Error instead of a Data Timeout error. I'm not sure how to deal
with that.
Documentation for this controller can be found in many data sheets from
Atmel, including the AT32AP7000 data sheet which can be found here:
http://www.atmel.com/dyn/products/datasheets.asp?family_id=682
Signed-off-by: Haavard Skinnemoen <haavard.skinnemoen@atmel.com>
Signed-off-by: Pierre Ossman <drzeus@drzeus.cx>
2008-06-30 10:35:03 -06:00
|
|
|
struct mmc_command *cmd;
|
atmel-mci: support multiple mmc slots
The Atmel MCI controller can drive multiple cards through separate sets
of pins, but only one at a time. This patch adds support for
multiplexing access to the controller so that multiple card slots can be
used as if they were hooked up to separate mmc controllers.
The atmel-mci driver registers each slot as a separate mmc_host. Both
access the same common controller state, but they also have some state
on their own for card detection/write protect handling, and separate
shadows of the MR and SDCR registers.
When one of the slots receives a request from the mmc core, the common
controller state is checked. If it's idle, the request is submitted
immediately. If not, the request is added to a queue. When a request is
done, the queue is checked and if there is a queued request, it is
submitted before the completion callback is called.
This patch also includes a few cleanups and fixes, including a locking
overhaul. I had to change the locking extensively in any case, so I
might as well try to get it right. The driver no longer takes any
irq-safe locks, which may or may not improve the overall system
performance.
This patch also adds a bit of documentation of the internal data
structures.
Signed-off-by: Haavard Skinnemoen <haavard.skinnemoen@atmel.com>
2008-09-17 12:53:55 -06:00
|
|
|
struct mmc_data *data;
|
atmel-mci: Driver for Atmel on-chip MMC controllers
This is a driver for the MMC controller on the AP7000 chips from
Atmel. It should in theory work on AT91 systems too with some
tweaking, but since the DMA interface is quite different, it's not
entirely clear if it's worth merging this with the at91_mci driver.
This driver has been around for a while in BSPs and kernel sources
provided by Atmel, but this particular version uses the generic DMA
Engine framework (with the slave extensions) instead of an
avr32-only DMA controller framework.
This driver can also use PIO transfers when no DMA channels are
available, and for transfers where using DMA may be difficult or
impractical for some reason (e.g. the DMA setup overhead is usually
not worth it for very short transfers, and badly aligned buffers or
lengths are difficult to handle.)
Currently, the driver only support PIO transfers. DMA support has been
split out to a separate patch to hopefully make it easier to review.
The driver has been tested using mmc-block and ext3fs on several SD,
SDHC and MMC+ cards. Reads and writes work fine, with read transfer
rates up to 3.5 MiB/s on fast cards with debugging disabled.
The driver has also been tested using the mmc_test module on the same
cards. All tests except 7, 9, 15 and 17 succeed. The first two are
unsupported by all the cards I have, so I don't know if the driver
handles this correctly. The last two fail because the hardware flags a
Data CRC Error instead of a Data Timeout error. I'm not sure how to deal
with that.
Documentation for this controller can be found in many data sheets from
Atmel, including the AT32AP7000 data sheet which can be found here:
http://www.atmel.com/dyn/products/datasheets.asp?family_id=682
Signed-off-by: Haavard Skinnemoen <haavard.skinnemoen@atmel.com>
Signed-off-by: Pierre Ossman <drzeus@drzeus.cx>
2008-06-30 10:35:03 -06:00
|
|
|
u32 iflags;
|
atmel-mci: support multiple mmc slots
The Atmel MCI controller can drive multiple cards through separate sets
of pins, but only one at a time. This patch adds support for
multiplexing access to the controller so that multiple card slots can be
used as if they were hooked up to separate mmc controllers.
The atmel-mci driver registers each slot as a separate mmc_host. Both
access the same common controller state, but they also have some state
on their own for card detection/write protect handling, and separate
shadows of the MR and SDCR registers.
When one of the slots receives a request from the mmc core, the common
controller state is checked. If it's idle, the request is submitted
immediately. If not, the request is added to a queue. When a request is
done, the queue is checked and if there is a queued request, it is
submitted before the completion callback is called.
This patch also includes a few cleanups and fixes, including a locking
overhaul. I had to change the locking extensively in any case, so I
might as well try to get it right. The driver no longer takes any
irq-safe locks, which may or may not improve the overall system
performance.
This patch also adds a bit of documentation of the internal data
structures.
Signed-off-by: Haavard Skinnemoen <haavard.skinnemoen@atmel.com>
2008-09-17 12:53:55 -06:00
|
|
|
u32 cmdflags;
|
atmel-mci: Driver for Atmel on-chip MMC controllers
This is a driver for the MMC controller on the AP7000 chips from
Atmel. It should in theory work on AT91 systems too with some
tweaking, but since the DMA interface is quite different, it's not
entirely clear if it's worth merging this with the at91_mci driver.
This driver has been around for a while in BSPs and kernel sources
provided by Atmel, but this particular version uses the generic DMA
Engine framework (with the slave extensions) instead of an
avr32-only DMA controller framework.
This driver can also use PIO transfers when no DMA channels are
available, and for transfers where using DMA may be difficult or
impractical for some reason (e.g. the DMA setup overhead is usually
not worth it for very short transfers, and badly aligned buffers or
lengths are difficult to handle.)
Currently, the driver only support PIO transfers. DMA support has been
split out to a separate patch to hopefully make it easier to review.
The driver has been tested using mmc-block and ext3fs on several SD,
SDHC and MMC+ cards. Reads and writes work fine, with read transfer
rates up to 3.5 MiB/s on fast cards with debugging disabled.
The driver has also been tested using the mmc_test module on the same
cards. All tests except 7, 9, 15 and 17 succeed. The first two are
unsupported by all the cards I have, so I don't know if the driver
handles this correctly. The last two fail because the hardware flags a
Data CRC Error instead of a Data Timeout error. I'm not sure how to deal
with that.
Documentation for this controller can be found in many data sheets from
Atmel, including the AT32AP7000 data sheet which can be found here:
http://www.atmel.com/dyn/products/datasheets.asp?family_id=682
Signed-off-by: Haavard Skinnemoen <haavard.skinnemoen@atmel.com>
Signed-off-by: Pierre Ossman <drzeus@drzeus.cx>
2008-06-30 10:35:03 -06:00
|
|
|
|
atmel-mci: support multiple mmc slots
The Atmel MCI controller can drive multiple cards through separate sets
of pins, but only one at a time. This patch adds support for
multiplexing access to the controller so that multiple card slots can be
used as if they were hooked up to separate mmc controllers.
The atmel-mci driver registers each slot as a separate mmc_host. Both
access the same common controller state, but they also have some state
on their own for card detection/write protect handling, and separate
shadows of the MR and SDCR registers.
When one of the slots receives a request from the mmc core, the common
controller state is checked. If it's idle, the request is submitted
immediately. If not, the request is added to a queue. When a request is
done, the queue is checked and if there is a queued request, it is
submitted before the completion callback is called.
This patch also includes a few cleanups and fixes, including a locking
overhaul. I had to change the locking extensively in any case, so I
might as well try to get it right. The driver no longer takes any
irq-safe locks, which may or may not improve the overall system
performance.
This patch also adds a bit of documentation of the internal data
structures.
Signed-off-by: Haavard Skinnemoen <haavard.skinnemoen@atmel.com>
2008-09-17 12:53:55 -06:00
|
|
|
mrq = slot->mrq;
|
|
|
|
host->cur_slot = slot;
|
atmel-mci: Driver for Atmel on-chip MMC controllers
This is a driver for the MMC controller on the AP7000 chips from
Atmel. It should in theory work on AT91 systems too with some
tweaking, but since the DMA interface is quite different, it's not
entirely clear if it's worth merging this with the at91_mci driver.
This driver has been around for a while in BSPs and kernel sources
provided by Atmel, but this particular version uses the generic DMA
Engine framework (with the slave extensions) instead of an
avr32-only DMA controller framework.
This driver can also use PIO transfers when no DMA channels are
available, and for transfers where using DMA may be difficult or
impractical for some reason (e.g. the DMA setup overhead is usually
not worth it for very short transfers, and badly aligned buffers or
lengths are difficult to handle.)
Currently, the driver only support PIO transfers. DMA support has been
split out to a separate patch to hopefully make it easier to review.
The driver has been tested using mmc-block and ext3fs on several SD,
SDHC and MMC+ cards. Reads and writes work fine, with read transfer
rates up to 3.5 MiB/s on fast cards with debugging disabled.
The driver has also been tested using the mmc_test module on the same
cards. All tests except 7, 9, 15 and 17 succeed. The first two are
unsupported by all the cards I have, so I don't know if the driver
handles this correctly. The last two fail because the hardware flags a
Data CRC Error instead of a Data Timeout error. I'm not sure how to deal
with that.
Documentation for this controller can be found in many data sheets from
Atmel, including the AT32AP7000 data sheet which can be found here:
http://www.atmel.com/dyn/products/datasheets.asp?family_id=682
Signed-off-by: Haavard Skinnemoen <haavard.skinnemoen@atmel.com>
Signed-off-by: Pierre Ossman <drzeus@drzeus.cx>
2008-06-30 10:35:03 -06:00
|
|
|
host->mrq = mrq;
|
atmel-mci: support multiple mmc slots
The Atmel MCI controller can drive multiple cards through separate sets
of pins, but only one at a time. This patch adds support for
multiplexing access to the controller so that multiple card slots can be
used as if they were hooked up to separate mmc controllers.
The atmel-mci driver registers each slot as a separate mmc_host. Both
access the same common controller state, but they also have some state
on their own for card detection/write protect handling, and separate
shadows of the MR and SDCR registers.
When one of the slots receives a request from the mmc core, the common
controller state is checked. If it's idle, the request is submitted
immediately. If not, the request is added to a queue. When a request is
done, the queue is checked and if there is a queued request, it is
submitted before the completion callback is called.
This patch also includes a few cleanups and fixes, including a locking
overhaul. I had to change the locking extensively in any case, so I
might as well try to get it right. The driver no longer takes any
irq-safe locks, which may or may not improve the overall system
performance.
This patch also adds a bit of documentation of the internal data
structures.
Signed-off-by: Haavard Skinnemoen <haavard.skinnemoen@atmel.com>
2008-09-17 12:53:55 -06:00
|
|
|
|
atmel-mci: Driver for Atmel on-chip MMC controllers
This is a driver for the MMC controller on the AP7000 chips from
Atmel. It should in theory work on AT91 systems too with some
tweaking, but since the DMA interface is quite different, it's not
entirely clear if it's worth merging this with the at91_mci driver.
This driver has been around for a while in BSPs and kernel sources
provided by Atmel, but this particular version uses the generic DMA
Engine framework (with the slave extensions) instead of an
avr32-only DMA controller framework.
This driver can also use PIO transfers when no DMA channels are
available, and for transfers where using DMA may be difficult or
impractical for some reason (e.g. the DMA setup overhead is usually
not worth it for very short transfers, and badly aligned buffers or
lengths are difficult to handle.)
Currently, the driver only support PIO transfers. DMA support has been
split out to a separate patch to hopefully make it easier to review.
The driver has been tested using mmc-block and ext3fs on several SD,
SDHC and MMC+ cards. Reads and writes work fine, with read transfer
rates up to 3.5 MiB/s on fast cards with debugging disabled.
The driver has also been tested using the mmc_test module on the same
cards. All tests except 7, 9, 15 and 17 succeed. The first two are
unsupported by all the cards I have, so I don't know if the driver
handles this correctly. The last two fail because the hardware flags a
Data CRC Error instead of a Data Timeout error. I'm not sure how to deal
with that.
Documentation for this controller can be found in many data sheets from
Atmel, including the AT32AP7000 data sheet which can be found here:
http://www.atmel.com/dyn/products/datasheets.asp?family_id=682
Signed-off-by: Haavard Skinnemoen <haavard.skinnemoen@atmel.com>
Signed-off-by: Pierre Ossman <drzeus@drzeus.cx>
2008-06-30 10:35:03 -06:00
|
|
|
host->pending_events = 0;
|
|
|
|
host->completed_events = 0;
|
2012-05-16 07:25:59 -06:00
|
|
|
host->cmd_status = 0;
|
2008-10-05 07:16:59 -06:00
|
|
|
host->data_status = 0;
|
atmel-mci: Driver for Atmel on-chip MMC controllers
This is a driver for the MMC controller on the AP7000 chips from
Atmel. It should in theory work on AT91 systems too with some
tweaking, but since the DMA interface is quite different, it's not
entirely clear if it's worth merging this with the at91_mci driver.
This driver has been around for a while in BSPs and kernel sources
provided by Atmel, but this particular version uses the generic DMA
Engine framework (with the slave extensions) instead of an
avr32-only DMA controller framework.
This driver can also use PIO transfers when no DMA channels are
available, and for transfers where using DMA may be difficult or
impractical for some reason (e.g. the DMA setup overhead is usually
not worth it for very short transfers, and badly aligned buffers or
lengths are difficult to handle.)
Currently, the driver only support PIO transfers. DMA support has been
split out to a separate patch to hopefully make it easier to review.
The driver has been tested using mmc-block and ext3fs on several SD,
SDHC and MMC+ cards. Reads and writes work fine, with read transfer
rates up to 3.5 MiB/s on fast cards with debugging disabled.
The driver has also been tested using the mmc_test module on the same
cards. All tests except 7, 9, 15 and 17 succeed. The first two are
unsupported by all the cards I have, so I don't know if the driver
handles this correctly. The last two fail because the hardware flags a
Data CRC Error instead of a Data Timeout error. I'm not sure how to deal
with that.
Documentation for this controller can be found in many data sheets from
Atmel, including the AT32AP7000 data sheet which can be found here:
http://www.atmel.com/dyn/products/datasheets.asp?family_id=682
Signed-off-by: Haavard Skinnemoen <haavard.skinnemoen@atmel.com>
Signed-off-by: Pierre Ossman <drzeus@drzeus.cx>
2008-06-30 10:35:03 -06:00
|
|
|
|
2012-05-16 07:26:01 -06:00
|
|
|
dev_dbg(&host->pdev->dev, "start request: cmd %u\n", mrq->cmd->opcode);
|
|
|
|
|
2012-05-16 07:26:00 -06:00
|
|
|
if (host->need_reset || host->caps.need_reset_after_xfer) {
|
2012-02-09 03:55:29 -07:00
|
|
|
iflags = atmci_readl(host, ATMCI_IMR);
|
|
|
|
iflags &= (ATMCI_SDIOIRQA | ATMCI_SDIOIRQB);
|
2011-08-11 09:25:42 -06:00
|
|
|
atmci_writel(host, ATMCI_CR, ATMCI_CR_SWRST);
|
|
|
|
atmci_writel(host, ATMCI_CR, ATMCI_CR_MCIEN);
|
|
|
|
atmci_writel(host, ATMCI_MR, host->mode_reg);
|
2011-08-11 09:25:44 -06:00
|
|
|
if (host->caps.has_cfg_reg)
|
2011-08-11 09:25:42 -06:00
|
|
|
atmci_writel(host, ATMCI_CFG, host->cfg_reg);
|
2012-02-09 03:55:29 -07:00
|
|
|
atmci_writel(host, ATMCI_IER, iflags);
|
atmel-mci: support multiple mmc slots
The Atmel MCI controller can drive multiple cards through separate sets
of pins, but only one at a time. This patch adds support for
multiplexing access to the controller so that multiple card slots can be
used as if they were hooked up to separate mmc controllers.
The atmel-mci driver registers each slot as a separate mmc_host. Both
access the same common controller state, but they also have some state
on their own for card detection/write protect handling, and separate
shadows of the MR and SDCR registers.
When one of the slots receives a request from the mmc core, the common
controller state is checked. If it's idle, the request is submitted
immediately. If not, the request is added to a queue. When a request is
done, the queue is checked and if there is a queued request, it is
submitted before the completion callback is called.
This patch also includes a few cleanups and fixes, including a locking
overhaul. I had to change the locking extensively in any case, so I
might as well try to get it right. The driver no longer takes any
irq-safe locks, which may or may not improve the overall system
performance.
This patch also adds a bit of documentation of the internal data
structures.
Signed-off-by: Haavard Skinnemoen <haavard.skinnemoen@atmel.com>
2008-09-17 12:53:55 -06:00
|
|
|
host->need_reset = false;
|
|
|
|
}
|
2011-08-11 09:25:42 -06:00
|
|
|
atmci_writel(host, ATMCI_SDCR, slot->sdc_reg);
|
atmel-mci: support multiple mmc slots
The Atmel MCI controller can drive multiple cards through separate sets
of pins, but only one at a time. This patch adds support for
multiplexing access to the controller so that multiple card slots can be
used as if they were hooked up to separate mmc controllers.
The atmel-mci driver registers each slot as a separate mmc_host. Both
access the same common controller state, but they also have some state
on their own for card detection/write protect handling, and separate
shadows of the MR and SDCR registers.
When one of the slots receives a request from the mmc core, the common
controller state is checked. If it's idle, the request is submitted
immediately. If not, the request is added to a queue. When a request is
done, the queue is checked and if there is a queued request, it is
submitted before the completion callback is called.
This patch also includes a few cleanups and fixes, including a locking
overhaul. I had to change the locking extensively in any case, so I
might as well try to get it right. The driver no longer takes any
irq-safe locks, which may or may not improve the overall system
performance.
This patch also adds a bit of documentation of the internal data
structures.
Signed-off-by: Haavard Skinnemoen <haavard.skinnemoen@atmel.com>
2008-09-17 12:53:55 -06:00
|
|
|
|
2011-08-11 09:25:42 -06:00
|
|
|
iflags = atmci_readl(host, ATMCI_IMR);
|
2011-08-11 09:25:41 -06:00
|
|
|
if (iflags & ~(ATMCI_SDIOIRQA | ATMCI_SDIOIRQB))
|
2012-05-16 07:25:59 -06:00
|
|
|
dev_dbg(&slot->mmc->class_dev, "WARNING: IMR=0x%08x\n",
|
atmel-mci: support multiple mmc slots
The Atmel MCI controller can drive multiple cards through separate sets
of pins, but only one at a time. This patch adds support for
multiplexing access to the controller so that multiple card slots can be
used as if they were hooked up to separate mmc controllers.
The atmel-mci driver registers each slot as a separate mmc_host. Both
access the same common controller state, but they also have some state
on their own for card detection/write protect handling, and separate
shadows of the MR and SDCR registers.
When one of the slots receives a request from the mmc core, the common
controller state is checked. If it's idle, the request is submitted
immediately. If not, the request is added to a queue. When a request is
done, the queue is checked and if there is a queued request, it is
submitted before the completion callback is called.
This patch also includes a few cleanups and fixes, including a locking
overhaul. I had to change the locking extensively in any case, so I
might as well try to get it right. The driver no longer takes any
irq-safe locks, which may or may not improve the overall system
performance.
This patch also adds a bit of documentation of the internal data
structures.
Signed-off-by: Haavard Skinnemoen <haavard.skinnemoen@atmel.com>
2008-09-17 12:53:55 -06:00
|
|
|
iflags);
|
|
|
|
|
|
|
|
if (unlikely(test_and_clear_bit(ATMCI_CARD_NEED_INIT, &slot->flags))) {
|
|
|
|
/* Send init sequence (74 clock cycles) */
|
2011-08-11 09:25:42 -06:00
|
|
|
atmci_writel(host, ATMCI_CMDR, ATMCI_CMDR_SPCMD_INIT);
|
|
|
|
while (!(atmci_readl(host, ATMCI_SR) & ATMCI_CMDRDY))
|
atmel-mci: support multiple mmc slots
The Atmel MCI controller can drive multiple cards through separate sets
of pins, but only one at a time. This patch adds support for
multiplexing access to the controller so that multiple card slots can be
used as if they were hooked up to separate mmc controllers.
The atmel-mci driver registers each slot as a separate mmc_host. Both
access the same common controller state, but they also have some state
on their own for card detection/write protect handling, and separate
shadows of the MR and SDCR registers.
When one of the slots receives a request from the mmc core, the common
controller state is checked. If it's idle, the request is submitted
immediately. If not, the request is added to a queue. When a request is
done, the queue is checked and if there is a queued request, it is
submitted before the completion callback is called.
This patch also includes a few cleanups and fixes, including a locking
overhaul. I had to change the locking extensively in any case, so I
might as well try to get it right. The driver no longer takes any
irq-safe locks, which may or may not improve the overall system
performance.
This patch also adds a bit of documentation of the internal data
structures.
Signed-off-by: Haavard Skinnemoen <haavard.skinnemoen@atmel.com>
2008-09-17 12:53:55 -06:00
|
|
|
cpu_relax();
|
|
|
|
}
|
2009-12-14 19:01:31 -07:00
|
|
|
iflags = 0;
|
atmel-mci: Driver for Atmel on-chip MMC controllers
This is a driver for the MMC controller on the AP7000 chips from
Atmel. It should in theory work on AT91 systems too with some
tweaking, but since the DMA interface is quite different, it's not
entirely clear if it's worth merging this with the at91_mci driver.
This driver has been around for a while in BSPs and kernel sources
provided by Atmel, but this particular version uses the generic DMA
Engine framework (with the slave extensions) instead of an
avr32-only DMA controller framework.
This driver can also use PIO transfers when no DMA channels are
available, and for transfers where using DMA may be difficult or
impractical for some reason (e.g. the DMA setup overhead is usually
not worth it for very short transfers, and badly aligned buffers or
lengths are difficult to handle.)
Currently, the driver only support PIO transfers. DMA support has been
split out to a separate patch to hopefully make it easier to review.
The driver has been tested using mmc-block and ext3fs on several SD,
SDHC and MMC+ cards. Reads and writes work fine, with read transfer
rates up to 3.5 MiB/s on fast cards with debugging disabled.
The driver has also been tested using the mmc_test module on the same
cards. All tests except 7, 9, 15 and 17 succeed. The first two are
unsupported by all the cards I have, so I don't know if the driver
handles this correctly. The last two fail because the hardware flags a
Data CRC Error instead of a Data Timeout error. I'm not sure how to deal
with that.
Documentation for this controller can be found in many data sheets from
Atmel, including the AT32AP7000 data sheet which can be found here:
http://www.atmel.com/dyn/products/datasheets.asp?family_id=682
Signed-off-by: Haavard Skinnemoen <haavard.skinnemoen@atmel.com>
Signed-off-by: Pierre Ossman <drzeus@drzeus.cx>
2008-06-30 10:35:03 -06:00
|
|
|
data = mrq->data;
|
|
|
|
if (data) {
|
atmel-mci: support multiple mmc slots
The Atmel MCI controller can drive multiple cards through separate sets
of pins, but only one at a time. This patch adds support for
multiplexing access to the controller so that multiple card slots can be
used as if they were hooked up to separate mmc controllers.
The atmel-mci driver registers each slot as a separate mmc_host. Both
access the same common controller state, but they also have some state
on their own for card detection/write protect handling, and separate
shadows of the MR and SDCR registers.
When one of the slots receives a request from the mmc core, the common
controller state is checked. If it's idle, the request is submitted
immediately. If not, the request is added to a queue. When a request is
done, the queue is checked and if there is a queued request, it is
submitted before the completion callback is called.
This patch also includes a few cleanups and fixes, including a locking
overhaul. I had to change the locking extensively in any case, so I
might as well try to get it right. The driver no longer takes any
irq-safe locks, which may or may not improve the overall system
performance.
This patch also adds a bit of documentation of the internal data
structures.
Signed-off-by: Haavard Skinnemoen <haavard.skinnemoen@atmel.com>
2008-09-17 12:53:55 -06:00
|
|
|
atmci_set_timeout(host, slot, data);
|
2008-10-03 06:46:17 -06:00
|
|
|
|
|
|
|
/* Must set block count/size before sending command */
|
2011-08-11 09:25:42 -06:00
|
|
|
atmci_writel(host, ATMCI_BLKR, ATMCI_BCNT(data->blocks)
|
2011-08-11 09:25:41 -06:00
|
|
|
| ATMCI_BLKLEN(data->blksz));
|
atmel-mci: support multiple mmc slots
The Atmel MCI controller can drive multiple cards through separate sets
of pins, but only one at a time. This patch adds support for
multiplexing access to the controller so that multiple card slots can be
used as if they were hooked up to separate mmc controllers.
The atmel-mci driver registers each slot as a separate mmc_host. Both
access the same common controller state, but they also have some state
on their own for card detection/write protect handling, and separate
shadows of the MR and SDCR registers.
When one of the slots receives a request from the mmc core, the common
controller state is checked. If it's idle, the request is submitted
immediately. If not, the request is added to a queue. When a request is
done, the queue is checked and if there is a queued request, it is
submitted before the completion callback is called.
This patch also includes a few cleanups and fixes, including a locking
overhaul. I had to change the locking extensively in any case, so I
might as well try to get it right. The driver no longer takes any
irq-safe locks, which may or may not improve the overall system
performance.
This patch also adds a bit of documentation of the internal data
structures.
Signed-off-by: Haavard Skinnemoen <haavard.skinnemoen@atmel.com>
2008-09-17 12:53:55 -06:00
|
|
|
dev_vdbg(&slot->mmc->class_dev, "BLKR=0x%08x\n",
|
2011-08-11 09:25:41 -06:00
|
|
|
ATMCI_BCNT(data->blocks) | ATMCI_BLKLEN(data->blksz));
|
2009-12-14 19:01:31 -07:00
|
|
|
|
2011-08-11 09:25:44 -06:00
|
|
|
iflags |= host->prepare_data(host, data);
|
atmel-mci: Driver for Atmel on-chip MMC controllers
This is a driver for the MMC controller on the AP7000 chips from
Atmel. It should in theory work on AT91 systems too with some
tweaking, but since the DMA interface is quite different, it's not
entirely clear if it's worth merging this with the at91_mci driver.
This driver has been around for a while in BSPs and kernel sources
provided by Atmel, but this particular version uses the generic DMA
Engine framework (with the slave extensions) instead of an
avr32-only DMA controller framework.
This driver can also use PIO transfers when no DMA channels are
available, and for transfers where using DMA may be difficult or
impractical for some reason (e.g. the DMA setup overhead is usually
not worth it for very short transfers, and badly aligned buffers or
lengths are difficult to handle.)
Currently, the driver only support PIO transfers. DMA support has been
split out to a separate patch to hopefully make it easier to review.
The driver has been tested using mmc-block and ext3fs on several SD,
SDHC and MMC+ cards. Reads and writes work fine, with read transfer
rates up to 3.5 MiB/s on fast cards with debugging disabled.
The driver has also been tested using the mmc_test module on the same
cards. All tests except 7, 9, 15 and 17 succeed. The first two are
unsupported by all the cards I have, so I don't know if the driver
handles this correctly. The last two fail because the hardware flags a
Data CRC Error instead of a Data Timeout error. I'm not sure how to deal
with that.
Documentation for this controller can be found in many data sheets from
Atmel, including the AT32AP7000 data sheet which can be found here:
http://www.atmel.com/dyn/products/datasheets.asp?family_id=682
Signed-off-by: Haavard Skinnemoen <haavard.skinnemoen@atmel.com>
Signed-off-by: Pierre Ossman <drzeus@drzeus.cx>
2008-06-30 10:35:03 -06:00
|
|
|
}
|
|
|
|
|
2011-08-11 09:25:41 -06:00
|
|
|
iflags |= ATMCI_CMDRDY;
|
atmel-mci: Driver for Atmel on-chip MMC controllers
This is a driver for the MMC controller on the AP7000 chips from
Atmel. It should in theory work on AT91 systems too with some
tweaking, but since the DMA interface is quite different, it's not
entirely clear if it's worth merging this with the at91_mci driver.
This driver has been around for a while in BSPs and kernel sources
provided by Atmel, but this particular version uses the generic DMA
Engine framework (with the slave extensions) instead of an
avr32-only DMA controller framework.
This driver can also use PIO transfers when no DMA channels are
available, and for transfers where using DMA may be difficult or
impractical for some reason (e.g. the DMA setup overhead is usually
not worth it for very short transfers, and badly aligned buffers or
lengths are difficult to handle.)
Currently, the driver only support PIO transfers. DMA support has been
split out to a separate patch to hopefully make it easier to review.
The driver has been tested using mmc-block and ext3fs on several SD,
SDHC and MMC+ cards. Reads and writes work fine, with read transfer
rates up to 3.5 MiB/s on fast cards with debugging disabled.
The driver has also been tested using the mmc_test module on the same
cards. All tests except 7, 9, 15 and 17 succeed. The first two are
unsupported by all the cards I have, so I don't know if the driver
handles this correctly. The last two fail because the hardware flags a
Data CRC Error instead of a Data Timeout error. I'm not sure how to deal
with that.
Documentation for this controller can be found in many data sheets from
Atmel, including the AT32AP7000 data sheet which can be found here:
http://www.atmel.com/dyn/products/datasheets.asp?family_id=682
Signed-off-by: Haavard Skinnemoen <haavard.skinnemoen@atmel.com>
Signed-off-by: Pierre Ossman <drzeus@drzeus.cx>
2008-06-30 10:35:03 -06:00
|
|
|
cmd = mrq->cmd;
|
atmel-mci: support multiple mmc slots
The Atmel MCI controller can drive multiple cards through separate sets
of pins, but only one at a time. This patch adds support for
multiplexing access to the controller so that multiple card slots can be
used as if they were hooked up to separate mmc controllers.
The atmel-mci driver registers each slot as a separate mmc_host. Both
access the same common controller state, but they also have some state
on their own for card detection/write protect handling, and separate
shadows of the MR and SDCR registers.
When one of the slots receives a request from the mmc core, the common
controller state is checked. If it's idle, the request is submitted
immediately. If not, the request is added to a queue. When a request is
done, the queue is checked and if there is a queued request, it is
submitted before the completion callback is called.
This patch also includes a few cleanups and fixes, including a locking
overhaul. I had to change the locking extensively in any case, so I
might as well try to get it right. The driver no longer takes any
irq-safe locks, which may or may not improve the overall system
performance.
This patch also adds a bit of documentation of the internal data
structures.
Signed-off-by: Haavard Skinnemoen <haavard.skinnemoen@atmel.com>
2008-09-17 12:53:55 -06:00
|
|
|
cmdflags = atmci_prepare_command(slot->mmc, cmd);
|
2013-11-20 08:01:11 -07:00
|
|
|
|
|
|
|
/*
|
|
|
|
* DMA transfer should be started before sending the command to avoid
|
|
|
|
* unexpected errors especially for read operations in SDIO mode.
|
|
|
|
* Unfortunately, in PDC mode, command has to be sent before starting
|
|
|
|
* the transfer.
|
|
|
|
*/
|
|
|
|
if (host->submit_data != &atmci_submit_data_dma)
|
|
|
|
atmci_send_command(host, cmd, cmdflags);
|
atmel-mci: Driver for Atmel on-chip MMC controllers
This is a driver for the MMC controller on the AP7000 chips from
Atmel. It should in theory work on AT91 systems too with some
tweaking, but since the DMA interface is quite different, it's not
entirely clear if it's worth merging this with the at91_mci driver.
This driver has been around for a while in BSPs and kernel sources
provided by Atmel, but this particular version uses the generic DMA
Engine framework (with the slave extensions) instead of an
avr32-only DMA controller framework.
This driver can also use PIO transfers when no DMA channels are
available, and for transfers where using DMA may be difficult or
impractical for some reason (e.g. the DMA setup overhead is usually
not worth it for very short transfers, and badly aligned buffers or
lengths are difficult to handle.)
Currently, the driver only support PIO transfers. DMA support has been
split out to a separate patch to hopefully make it easier to review.
The driver has been tested using mmc-block and ext3fs on several SD,
SDHC and MMC+ cards. Reads and writes work fine, with read transfer
rates up to 3.5 MiB/s on fast cards with debugging disabled.
The driver has also been tested using the mmc_test module on the same
cards. All tests except 7, 9, 15 and 17 succeed. The first two are
unsupported by all the cards I have, so I don't know if the driver
handles this correctly. The last two fail because the hardware flags a
Data CRC Error instead of a Data Timeout error. I'm not sure how to deal
with that.
Documentation for this controller can be found in many data sheets from
Atmel, including the AT32AP7000 data sheet which can be found here:
http://www.atmel.com/dyn/products/datasheets.asp?family_id=682
Signed-off-by: Haavard Skinnemoen <haavard.skinnemoen@atmel.com>
Signed-off-by: Pierre Ossman <drzeus@drzeus.cx>
2008-06-30 10:35:03 -06:00
|
|
|
|
|
|
|
if (data)
|
2011-08-11 09:25:44 -06:00
|
|
|
host->submit_data(host, data);
|
atmel-mci: Driver for Atmel on-chip MMC controllers
This is a driver for the MMC controller on the AP7000 chips from
Atmel. It should in theory work on AT91 systems too with some
tweaking, but since the DMA interface is quite different, it's not
entirely clear if it's worth merging this with the at91_mci driver.
This driver has been around for a while in BSPs and kernel sources
provided by Atmel, but this particular version uses the generic DMA
Engine framework (with the slave extensions) instead of an
avr32-only DMA controller framework.
This driver can also use PIO transfers when no DMA channels are
available, and for transfers where using DMA may be difficult or
impractical for some reason (e.g. the DMA setup overhead is usually
not worth it for very short transfers, and badly aligned buffers or
lengths are difficult to handle.)
Currently, the driver only support PIO transfers. DMA support has been
split out to a separate patch to hopefully make it easier to review.
The driver has been tested using mmc-block and ext3fs on several SD,
SDHC and MMC+ cards. Reads and writes work fine, with read transfer
rates up to 3.5 MiB/s on fast cards with debugging disabled.
The driver has also been tested using the mmc_test module on the same
cards. All tests except 7, 9, 15 and 17 succeed. The first two are
unsupported by all the cards I have, so I don't know if the driver
handles this correctly. The last two fail because the hardware flags a
Data CRC Error instead of a Data Timeout error. I'm not sure how to deal
with that.
Documentation for this controller can be found in many data sheets from
Atmel, including the AT32AP7000 data sheet which can be found here:
http://www.atmel.com/dyn/products/datasheets.asp?family_id=682
Signed-off-by: Haavard Skinnemoen <haavard.skinnemoen@atmel.com>
Signed-off-by: Pierre Ossman <drzeus@drzeus.cx>
2008-06-30 10:35:03 -06:00
|
|
|
|
2013-11-20 08:01:11 -07:00
|
|
|
if (host->submit_data == &atmci_submit_data_dma)
|
|
|
|
atmci_send_command(host, cmd, cmdflags);
|
|
|
|
|
atmel-mci: Driver for Atmel on-chip MMC controllers
This is a driver for the MMC controller on the AP7000 chips from
Atmel. It should in theory work on AT91 systems too with some
tweaking, but since the DMA interface is quite different, it's not
entirely clear if it's worth merging this with the at91_mci driver.
This driver has been around for a while in BSPs and kernel sources
provided by Atmel, but this particular version uses the generic DMA
Engine framework (with the slave extensions) instead of an
avr32-only DMA controller framework.
This driver can also use PIO transfers when no DMA channels are
available, and for transfers where using DMA may be difficult or
impractical for some reason (e.g. the DMA setup overhead is usually
not worth it for very short transfers, and badly aligned buffers or
lengths are difficult to handle.)
Currently, the driver only support PIO transfers. DMA support has been
split out to a separate patch to hopefully make it easier to review.
The driver has been tested using mmc-block and ext3fs on several SD,
SDHC and MMC+ cards. Reads and writes work fine, with read transfer
rates up to 3.5 MiB/s on fast cards with debugging disabled.
The driver has also been tested using the mmc_test module on the same
cards. All tests except 7, 9, 15 and 17 succeed. The first two are
unsupported by all the cards I have, so I don't know if the driver
handles this correctly. The last two fail because the hardware flags a
Data CRC Error instead of a Data Timeout error. I'm not sure how to deal
with that.
Documentation for this controller can be found in many data sheets from
Atmel, including the AT32AP7000 data sheet which can be found here:
http://www.atmel.com/dyn/products/datasheets.asp?family_id=682
Signed-off-by: Haavard Skinnemoen <haavard.skinnemoen@atmel.com>
Signed-off-by: Pierre Ossman <drzeus@drzeus.cx>
2008-06-30 10:35:03 -06:00
|
|
|
if (mrq->stop) {
|
atmel-mci: support multiple mmc slots
The Atmel MCI controller can drive multiple cards through separate sets
of pins, but only one at a time. This patch adds support for
multiplexing access to the controller so that multiple card slots can be
used as if they were hooked up to separate mmc controllers.
The atmel-mci driver registers each slot as a separate mmc_host. Both
access the same common controller state, but they also have some state
on their own for card detection/write protect handling, and separate
shadows of the MR and SDCR registers.
When one of the slots receives a request from the mmc core, the common
controller state is checked. If it's idle, the request is submitted
immediately. If not, the request is added to a queue. When a request is
done, the queue is checked and if there is a queued request, it is
submitted before the completion callback is called.
This patch also includes a few cleanups and fixes, including a locking
overhaul. I had to change the locking extensively in any case, so I
might as well try to get it right. The driver no longer takes any
irq-safe locks, which may or may not improve the overall system
performance.
This patch also adds a bit of documentation of the internal data
structures.
Signed-off-by: Haavard Skinnemoen <haavard.skinnemoen@atmel.com>
2008-09-17 12:53:55 -06:00
|
|
|
host->stop_cmdr = atmci_prepare_command(slot->mmc, mrq->stop);
|
2011-08-11 09:25:41 -06:00
|
|
|
host->stop_cmdr |= ATMCI_CMDR_STOP_XFER;
|
atmel-mci: Driver for Atmel on-chip MMC controllers
This is a driver for the MMC controller on the AP7000 chips from
Atmel. It should in theory work on AT91 systems too with some
tweaking, but since the DMA interface is quite different, it's not
entirely clear if it's worth merging this with the at91_mci driver.
This driver has been around for a while in BSPs and kernel sources
provided by Atmel, but this particular version uses the generic DMA
Engine framework (with the slave extensions) instead of an
avr32-only DMA controller framework.
This driver can also use PIO transfers when no DMA channels are
available, and for transfers where using DMA may be difficult or
impractical for some reason (e.g. the DMA setup overhead is usually
not worth it for very short transfers, and badly aligned buffers or
lengths are difficult to handle.)
Currently, the driver only support PIO transfers. DMA support has been
split out to a separate patch to hopefully make it easier to review.
The driver has been tested using mmc-block and ext3fs on several SD,
SDHC and MMC+ cards. Reads and writes work fine, with read transfer
rates up to 3.5 MiB/s on fast cards with debugging disabled.
The driver has also been tested using the mmc_test module on the same
cards. All tests except 7, 9, 15 and 17 succeed. The first two are
unsupported by all the cards I have, so I don't know if the driver
handles this correctly. The last two fail because the hardware flags a
Data CRC Error instead of a Data Timeout error. I'm not sure how to deal
with that.
Documentation for this controller can be found in many data sheets from
Atmel, including the AT32AP7000 data sheet which can be found here:
http://www.atmel.com/dyn/products/datasheets.asp?family_id=682
Signed-off-by: Haavard Skinnemoen <haavard.skinnemoen@atmel.com>
Signed-off-by: Pierre Ossman <drzeus@drzeus.cx>
2008-06-30 10:35:03 -06:00
|
|
|
if (!(data->flags & MMC_DATA_WRITE))
|
2011-08-11 09:25:41 -06:00
|
|
|
host->stop_cmdr |= ATMCI_CMDR_TRDIR_READ;
|
2016-02-01 05:07:26 -07:00
|
|
|
host->stop_cmdr |= ATMCI_CMDR_MULTI_BLOCK;
|
atmel-mci: Driver for Atmel on-chip MMC controllers
This is a driver for the MMC controller on the AP7000 chips from
Atmel. It should in theory work on AT91 systems too with some
tweaking, but since the DMA interface is quite different, it's not
entirely clear if it's worth merging this with the at91_mci driver.
This driver has been around for a while in BSPs and kernel sources
provided by Atmel, but this particular version uses the generic DMA
Engine framework (with the slave extensions) instead of an
avr32-only DMA controller framework.
This driver can also use PIO transfers when no DMA channels are
available, and for transfers where using DMA may be difficult or
impractical for some reason (e.g. the DMA setup overhead is usually
not worth it for very short transfers, and badly aligned buffers or
lengths are difficult to handle.)
Currently, the driver only support PIO transfers. DMA support has been
split out to a separate patch to hopefully make it easier to review.
The driver has been tested using mmc-block and ext3fs on several SD,
SDHC and MMC+ cards. Reads and writes work fine, with read transfer
rates up to 3.5 MiB/s on fast cards with debugging disabled.
The driver has also been tested using the mmc_test module on the same
cards. All tests except 7, 9, 15 and 17 succeed. The first two are
unsupported by all the cards I have, so I don't know if the driver
handles this correctly. The last two fail because the hardware flags a
Data CRC Error instead of a Data Timeout error. I'm not sure how to deal
with that.
Documentation for this controller can be found in many data sheets from
Atmel, including the AT32AP7000 data sheet which can be found here:
http://www.atmel.com/dyn/products/datasheets.asp?family_id=682
Signed-off-by: Haavard Skinnemoen <haavard.skinnemoen@atmel.com>
Signed-off-by: Pierre Ossman <drzeus@drzeus.cx>
2008-06-30 10:35:03 -06:00
|
|
|
}
|
|
|
|
|
|
|
|
/*
|
|
|
|
* We could have enabled interrupts earlier, but I suspect
|
|
|
|
* that would open up a nice can of interesting race
|
|
|
|
* conditions (e.g. command and data complete, but stop not
|
|
|
|
* prepared yet.)
|
|
|
|
*/
|
2011-08-11 09:25:42 -06:00
|
|
|
atmci_writel(host, ATMCI_IER, iflags);
|
2012-05-16 07:26:00 -06:00
|
|
|
|
|
|
|
mod_timer(&host->timer, jiffies + msecs_to_jiffies(2000));
|
atmel-mci: support multiple mmc slots
The Atmel MCI controller can drive multiple cards through separate sets
of pins, but only one at a time. This patch adds support for
multiplexing access to the controller so that multiple card slots can be
used as if they were hooked up to separate mmc controllers.
The atmel-mci driver registers each slot as a separate mmc_host. Both
access the same common controller state, but they also have some state
on their own for card detection/write protect handling, and separate
shadows of the MR and SDCR registers.
When one of the slots receives a request from the mmc core, the common
controller state is checked. If it's idle, the request is submitted
immediately. If not, the request is added to a queue. When a request is
done, the queue is checked and if there is a queued request, it is
submitted before the completion callback is called.
This patch also includes a few cleanups and fixes, including a locking
overhaul. I had to change the locking extensively in any case, so I
might as well try to get it right. The driver no longer takes any
irq-safe locks, which may or may not improve the overall system
performance.
This patch also adds a bit of documentation of the internal data
structures.
Signed-off-by: Haavard Skinnemoen <haavard.skinnemoen@atmel.com>
2008-09-17 12:53:55 -06:00
|
|
|
}
|
atmel-mci: Driver for Atmel on-chip MMC controllers
This is a driver for the MMC controller on the AP7000 chips from
Atmel. It should in theory work on AT91 systems too with some
tweaking, but since the DMA interface is quite different, it's not
entirely clear if it's worth merging this with the at91_mci driver.
This driver has been around for a while in BSPs and kernel sources
provided by Atmel, but this particular version uses the generic DMA
Engine framework (with the slave extensions) instead of an
avr32-only DMA controller framework.
This driver can also use PIO transfers when no DMA channels are
available, and for transfers where using DMA may be difficult or
impractical for some reason (e.g. the DMA setup overhead is usually
not worth it for very short transfers, and badly aligned buffers or
lengths are difficult to handle.)
Currently, the driver only support PIO transfers. DMA support has been
split out to a separate patch to hopefully make it easier to review.
The driver has been tested using mmc-block and ext3fs on several SD,
SDHC and MMC+ cards. Reads and writes work fine, with read transfer
rates up to 3.5 MiB/s on fast cards with debugging disabled.
The driver has also been tested using the mmc_test module on the same
cards. All tests except 7, 9, 15 and 17 succeed. The first two are
unsupported by all the cards I have, so I don't know if the driver
handles this correctly. The last two fail because the hardware flags a
Data CRC Error instead of a Data Timeout error. I'm not sure how to deal
with that.
Documentation for this controller can be found in many data sheets from
Atmel, including the AT32AP7000 data sheet which can be found here:
http://www.atmel.com/dyn/products/datasheets.asp?family_id=682
Signed-off-by: Haavard Skinnemoen <haavard.skinnemoen@atmel.com>
Signed-off-by: Pierre Ossman <drzeus@drzeus.cx>
2008-06-30 10:35:03 -06:00
|
|
|
|
atmel-mci: support multiple mmc slots
The Atmel MCI controller can drive multiple cards through separate sets
of pins, but only one at a time. This patch adds support for
multiplexing access to the controller so that multiple card slots can be
used as if they were hooked up to separate mmc controllers.
The atmel-mci driver registers each slot as a separate mmc_host. Both
access the same common controller state, but they also have some state
on their own for card detection/write protect handling, and separate
shadows of the MR and SDCR registers.
When one of the slots receives a request from the mmc core, the common
controller state is checked. If it's idle, the request is submitted
immediately. If not, the request is added to a queue. When a request is
done, the queue is checked and if there is a queued request, it is
submitted before the completion callback is called.
This patch also includes a few cleanups and fixes, including a locking
overhaul. I had to change the locking extensively in any case, so I
might as well try to get it right. The driver no longer takes any
irq-safe locks, which may or may not improve the overall system
performance.
This patch also adds a bit of documentation of the internal data
structures.
Signed-off-by: Haavard Skinnemoen <haavard.skinnemoen@atmel.com>
2008-09-17 12:53:55 -06:00
|
|
|
static void atmci_queue_request(struct atmel_mci *host,
|
|
|
|
struct atmel_mci_slot *slot, struct mmc_request *mrq)
|
|
|
|
{
|
|
|
|
dev_vdbg(&slot->mmc->class_dev, "queue request: state=%d\n",
|
|
|
|
host->state);
|
|
|
|
|
|
|
|
spin_lock_bh(&host->lock);
|
|
|
|
slot->mrq = mrq;
|
|
|
|
if (host->state == STATE_IDLE) {
|
|
|
|
host->state = STATE_SENDING_CMD;
|
|
|
|
atmci_start_request(host, slot);
|
|
|
|
} else {
|
2012-05-16 07:26:01 -06:00
|
|
|
dev_dbg(&host->pdev->dev, "queue request\n");
|
atmel-mci: support multiple mmc slots
The Atmel MCI controller can drive multiple cards through separate sets
of pins, but only one at a time. This patch adds support for
multiplexing access to the controller so that multiple card slots can be
used as if they were hooked up to separate mmc controllers.
The atmel-mci driver registers each slot as a separate mmc_host. Both
access the same common controller state, but they also have some state
on their own for card detection/write protect handling, and separate
shadows of the MR and SDCR registers.
When one of the slots receives a request from the mmc core, the common
controller state is checked. If it's idle, the request is submitted
immediately. If not, the request is added to a queue. When a request is
done, the queue is checked and if there is a queued request, it is
submitted before the completion callback is called.
This patch also includes a few cleanups and fixes, including a locking
overhaul. I had to change the locking extensively in any case, so I
might as well try to get it right. The driver no longer takes any
irq-safe locks, which may or may not improve the overall system
performance.
This patch also adds a bit of documentation of the internal data
structures.
Signed-off-by: Haavard Skinnemoen <haavard.skinnemoen@atmel.com>
2008-09-17 12:53:55 -06:00
|
|
|
list_add_tail(&slot->queue_node, &host->queue);
|
|
|
|
}
|
|
|
|
spin_unlock_bh(&host->lock);
|
|
|
|
}
|
atmel-mci: Driver for Atmel on-chip MMC controllers
This is a driver for the MMC controller on the AP7000 chips from
Atmel. It should in theory work on AT91 systems too with some
tweaking, but since the DMA interface is quite different, it's not
entirely clear if it's worth merging this with the at91_mci driver.
This driver has been around for a while in BSPs and kernel sources
provided by Atmel, but this particular version uses the generic DMA
Engine framework (with the slave extensions) instead of an
avr32-only DMA controller framework.
This driver can also use PIO transfers when no DMA channels are
available, and for transfers where using DMA may be difficult or
impractical for some reason (e.g. the DMA setup overhead is usually
not worth it for very short transfers, and badly aligned buffers or
lengths are difficult to handle.)
Currently, the driver only support PIO transfers. DMA support has been
split out to a separate patch to hopefully make it easier to review.
The driver has been tested using mmc-block and ext3fs on several SD,
SDHC and MMC+ cards. Reads and writes work fine, with read transfer
rates up to 3.5 MiB/s on fast cards with debugging disabled.
The driver has also been tested using the mmc_test module on the same
cards. All tests except 7, 9, 15 and 17 succeed. The first two are
unsupported by all the cards I have, so I don't know if the driver
handles this correctly. The last two fail because the hardware flags a
Data CRC Error instead of a Data Timeout error. I'm not sure how to deal
with that.
Documentation for this controller can be found in many data sheets from
Atmel, including the AT32AP7000 data sheet which can be found here:
http://www.atmel.com/dyn/products/datasheets.asp?family_id=682
Signed-off-by: Haavard Skinnemoen <haavard.skinnemoen@atmel.com>
Signed-off-by: Pierre Ossman <drzeus@drzeus.cx>
2008-06-30 10:35:03 -06:00
|
|
|
|
atmel-mci: support multiple mmc slots
The Atmel MCI controller can drive multiple cards through separate sets
of pins, but only one at a time. This patch adds support for
multiplexing access to the controller so that multiple card slots can be
used as if they were hooked up to separate mmc controllers.
The atmel-mci driver registers each slot as a separate mmc_host. Both
access the same common controller state, but they also have some state
on their own for card detection/write protect handling, and separate
shadows of the MR and SDCR registers.
When one of the slots receives a request from the mmc core, the common
controller state is checked. If it's idle, the request is submitted
immediately. If not, the request is added to a queue. When a request is
done, the queue is checked and if there is a queued request, it is
submitted before the completion callback is called.
This patch also includes a few cleanups and fixes, including a locking
overhaul. I had to change the locking extensively in any case, so I
might as well try to get it right. The driver no longer takes any
irq-safe locks, which may or may not improve the overall system
performance.
This patch also adds a bit of documentation of the internal data
structures.
Signed-off-by: Haavard Skinnemoen <haavard.skinnemoen@atmel.com>
2008-09-17 12:53:55 -06:00
|
|
|
static void atmci_request(struct mmc_host *mmc, struct mmc_request *mrq)
|
|
|
|
{
|
|
|
|
struct atmel_mci_slot *slot = mmc_priv(mmc);
|
|
|
|
struct atmel_mci *host = slot->host;
|
|
|
|
struct mmc_data *data;
|
|
|
|
|
|
|
|
WARN_ON(slot->mrq);
|
2012-05-16 07:26:01 -06:00
|
|
|
dev_dbg(&host->pdev->dev, "MRQ: cmd %u\n", mrq->cmd->opcode);
|
atmel-mci: support multiple mmc slots
The Atmel MCI controller can drive multiple cards through separate sets
of pins, but only one at a time. This patch adds support for
multiplexing access to the controller so that multiple card slots can be
used as if they were hooked up to separate mmc controllers.
The atmel-mci driver registers each slot as a separate mmc_host. Both
access the same common controller state, but they also have some state
on their own for card detection/write protect handling, and separate
shadows of the MR and SDCR registers.
When one of the slots receives a request from the mmc core, the common
controller state is checked. If it's idle, the request is submitted
immediately. If not, the request is added to a queue. When a request is
done, the queue is checked and if there is a queued request, it is
submitted before the completion callback is called.
This patch also includes a few cleanups and fixes, including a locking
overhaul. I had to change the locking extensively in any case, so I
might as well try to get it right. The driver no longer takes any
irq-safe locks, which may or may not improve the overall system
performance.
This patch also adds a bit of documentation of the internal data
structures.
Signed-off-by: Haavard Skinnemoen <haavard.skinnemoen@atmel.com>
2008-09-17 12:53:55 -06:00
|
|
|
|
|
|
|
/*
|
|
|
|
* We may "know" the card is gone even though there's still an
|
|
|
|
* electrical connection. If so, we really need to communicate
|
|
|
|
* this to the MMC core since there won't be any more
|
|
|
|
* interrupts as the card is completely removed. Otherwise,
|
|
|
|
* the MMC core might believe the card is still there even
|
|
|
|
* though the card was just removed very slowly.
|
|
|
|
*/
|
|
|
|
if (!test_bit(ATMCI_CARD_PRESENT, &slot->flags)) {
|
|
|
|
mrq->cmd->error = -ENOMEDIUM;
|
|
|
|
mmc_request_done(mmc, mrq);
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* We don't support multiple blocks of weird lengths. */
|
|
|
|
data = mrq->data;
|
|
|
|
if (data && data->blocks > 1 && data->blksz & 3) {
|
|
|
|
mrq->cmd->error = -EINVAL;
|
|
|
|
mmc_request_done(mmc, mrq);
|
|
|
|
}
|
|
|
|
|
|
|
|
atmci_queue_request(host, slot, mrq);
|
atmel-mci: Driver for Atmel on-chip MMC controllers
This is a driver for the MMC controller on the AP7000 chips from
Atmel. It should in theory work on AT91 systems too with some
tweaking, but since the DMA interface is quite different, it's not
entirely clear if it's worth merging this with the at91_mci driver.
This driver has been around for a while in BSPs and kernel sources
provided by Atmel, but this particular version uses the generic DMA
Engine framework (with the slave extensions) instead of an
avr32-only DMA controller framework.
This driver can also use PIO transfers when no DMA channels are
available, and for transfers where using DMA may be difficult or
impractical for some reason (e.g. the DMA setup overhead is usually
not worth it for very short transfers, and badly aligned buffers or
lengths are difficult to handle.)
Currently, the driver only support PIO transfers. DMA support has been
split out to a separate patch to hopefully make it easier to review.
The driver has been tested using mmc-block and ext3fs on several SD,
SDHC and MMC+ cards. Reads and writes work fine, with read transfer
rates up to 3.5 MiB/s on fast cards with debugging disabled.
The driver has also been tested using the mmc_test module on the same
cards. All tests except 7, 9, 15 and 17 succeed. The first two are
unsupported by all the cards I have, so I don't know if the driver
handles this correctly. The last two fail because the hardware flags a
Data CRC Error instead of a Data Timeout error. I'm not sure how to deal
with that.
Documentation for this controller can be found in many data sheets from
Atmel, including the AT32AP7000 data sheet which can be found here:
http://www.atmel.com/dyn/products/datasheets.asp?family_id=682
Signed-off-by: Haavard Skinnemoen <haavard.skinnemoen@atmel.com>
Signed-off-by: Pierre Ossman <drzeus@drzeus.cx>
2008-06-30 10:35:03 -06:00
|
|
|
}
|
|
|
|
|
|
|
|
static void atmci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
|
|
|
|
{
|
atmel-mci: support multiple mmc slots
The Atmel MCI controller can drive multiple cards through separate sets
of pins, but only one at a time. This patch adds support for
multiplexing access to the controller so that multiple card slots can be
used as if they were hooked up to separate mmc controllers.
The atmel-mci driver registers each slot as a separate mmc_host. Both
access the same common controller state, but they also have some state
on their own for card detection/write protect handling, and separate
shadows of the MR and SDCR registers.
When one of the slots receives a request from the mmc core, the common
controller state is checked. If it's idle, the request is submitted
immediately. If not, the request is added to a queue. When a request is
done, the queue is checked and if there is a queued request, it is
submitted before the completion callback is called.
This patch also includes a few cleanups and fixes, including a locking
overhaul. I had to change the locking extensively in any case, so I
might as well try to get it right. The driver no longer takes any
irq-safe locks, which may or may not improve the overall system
performance.
This patch also adds a bit of documentation of the internal data
structures.
Signed-off-by: Haavard Skinnemoen <haavard.skinnemoen@atmel.com>
2008-09-17 12:53:55 -06:00
|
|
|
struct atmel_mci_slot *slot = mmc_priv(mmc);
|
|
|
|
struct atmel_mci *host = slot->host;
|
|
|
|
unsigned int i;
|
2014-10-29 22:00:41 -06:00
|
|
|
|
2011-08-11 09:25:41 -06:00
|
|
|
slot->sdc_reg &= ~ATMCI_SDCBUS_MASK;
|
2008-10-03 09:48:16 -06:00
|
|
|
switch (ios->bus_width) {
|
|
|
|
case MMC_BUS_WIDTH_1:
|
2011-08-11 09:25:41 -06:00
|
|
|
slot->sdc_reg |= ATMCI_SDCBUS_1BIT;
|
2008-10-03 09:48:16 -06:00
|
|
|
break;
|
|
|
|
case MMC_BUS_WIDTH_4:
|
2011-08-11 09:25:41 -06:00
|
|
|
slot->sdc_reg |= ATMCI_SDCBUS_4BIT;
|
2008-10-03 09:48:16 -06:00
|
|
|
break;
|
|
|
|
}
|
|
|
|
|
atmel-mci: Driver for Atmel on-chip MMC controllers
This is a driver for the MMC controller on the AP7000 chips from
Atmel. It should in theory work on AT91 systems too with some
tweaking, but since the DMA interface is quite different, it's not
entirely clear if it's worth merging this with the at91_mci driver.
This driver has been around for a while in BSPs and kernel sources
provided by Atmel, but this particular version uses the generic DMA
Engine framework (with the slave extensions) instead of an
avr32-only DMA controller framework.
This driver can also use PIO transfers when no DMA channels are
available, and for transfers where using DMA may be difficult or
impractical for some reason (e.g. the DMA setup overhead is usually
not worth it for very short transfers, and badly aligned buffers or
lengths are difficult to handle.)
Currently, the driver only support PIO transfers. DMA support has been
split out to a separate patch to hopefully make it easier to review.
The driver has been tested using mmc-block and ext3fs on several SD,
SDHC and MMC+ cards. Reads and writes work fine, with read transfer
rates up to 3.5 MiB/s on fast cards with debugging disabled.
The driver has also been tested using the mmc_test module on the same
cards. All tests except 7, 9, 15 and 17 succeed. The first two are
unsupported by all the cards I have, so I don't know if the driver
handles this correctly. The last two fail because the hardware flags a
Data CRC Error instead of a Data Timeout error. I'm not sure how to deal
with that.
Documentation for this controller can be found in many data sheets from
Atmel, including the AT32AP7000 data sheet which can be found here:
http://www.atmel.com/dyn/products/datasheets.asp?family_id=682
Signed-off-by: Haavard Skinnemoen <haavard.skinnemoen@atmel.com>
Signed-off-by: Pierre Ossman <drzeus@drzeus.cx>
2008-06-30 10:35:03 -06:00
|
|
|
if (ios->clock) {
|
atmel-mci: support multiple mmc slots
The Atmel MCI controller can drive multiple cards through separate sets
of pins, but only one at a time. This patch adds support for
multiplexing access to the controller so that multiple card slots can be
used as if they were hooked up to separate mmc controllers.
The atmel-mci driver registers each slot as a separate mmc_host. Both
access the same common controller state, but they also have some state
on their own for card detection/write protect handling, and separate
shadows of the MR and SDCR registers.
When one of the slots receives a request from the mmc core, the common
controller state is checked. If it's idle, the request is submitted
immediately. If not, the request is added to a queue. When a request is
done, the queue is checked and if there is a queued request, it is
submitted before the completion callback is called.
This patch also includes a few cleanups and fixes, including a locking
overhaul. I had to change the locking extensively in any case, so I
might as well try to get it right. The driver no longer takes any
irq-safe locks, which may or may not improve the overall system
performance.
This patch also adds a bit of documentation of the internal data
structures.
Signed-off-by: Haavard Skinnemoen <haavard.skinnemoen@atmel.com>
2008-09-17 12:53:55 -06:00
|
|
|
unsigned int clock_min = ~0U;
|
2015-05-06 07:16:46 -06:00
|
|
|
int clkdiv;
|
atmel-mci: Driver for Atmel on-chip MMC controllers
This is a driver for the MMC controller on the AP7000 chips from
Atmel. It should in theory work on AT91 systems too with some
tweaking, but since the DMA interface is quite different, it's not
entirely clear if it's worth merging this with the at91_mci driver.
This driver has been around for a while in BSPs and kernel sources
provided by Atmel, but this particular version uses the generic DMA
Engine framework (with the slave extensions) instead of an
avr32-only DMA controller framework.
This driver can also use PIO transfers when no DMA channels are
available, and for transfers where using DMA may be difficult or
impractical for some reason (e.g. the DMA setup overhead is usually
not worth it for very short transfers, and badly aligned buffers or
lengths are difficult to handle.)
Currently, the driver only support PIO transfers. DMA support has been
split out to a separate patch to hopefully make it easier to review.
The driver has been tested using mmc-block and ext3fs on several SD,
SDHC and MMC+ cards. Reads and writes work fine, with read transfer
rates up to 3.5 MiB/s on fast cards with debugging disabled.
The driver has also been tested using the mmc_test module on the same
cards. All tests except 7, 9, 15 and 17 succeed. The first two are
unsupported by all the cards I have, so I don't know if the driver
handles this correctly. The last two fail because the hardware flags a
Data CRC Error instead of a Data Timeout error. I'm not sure how to deal
with that.
Documentation for this controller can be found in many data sheets from
Atmel, including the AT32AP7000 data sheet which can be found here:
http://www.atmel.com/dyn/products/datasheets.asp?family_id=682
Signed-off-by: Haavard Skinnemoen <haavard.skinnemoen@atmel.com>
Signed-off-by: Pierre Ossman <drzeus@drzeus.cx>
2008-06-30 10:35:03 -06:00
|
|
|
|
atmel-mci: support multiple mmc slots
The Atmel MCI controller can drive multiple cards through separate sets
of pins, but only one at a time. This patch adds support for
multiplexing access to the controller so that multiple card slots can be
used as if they were hooked up to separate mmc controllers.
The atmel-mci driver registers each slot as a separate mmc_host. Both
access the same common controller state, but they also have some state
on their own for card detection/write protect handling, and separate
shadows of the MR and SDCR registers.
When one of the slots receives a request from the mmc core, the common
controller state is checked. If it's idle, the request is submitted
immediately. If not, the request is added to a queue. When a request is
done, the queue is checked and if there is a queued request, it is
submitted before the completion callback is called.
This patch also includes a few cleanups and fixes, including a locking
overhaul. I had to change the locking extensively in any case, so I
might as well try to get it right. The driver no longer takes any
irq-safe locks, which may or may not improve the overall system
performance.
This patch also adds a bit of documentation of the internal data
structures.
Signed-off-by: Haavard Skinnemoen <haavard.skinnemoen@atmel.com>
2008-09-17 12:53:55 -06:00
|
|
|
spin_lock_bh(&host->lock);
|
|
|
|
if (!host->mode_reg) {
|
2011-08-11 09:25:42 -06:00
|
|
|
atmci_writel(host, ATMCI_CR, ATMCI_CR_SWRST);
|
|
|
|
atmci_writel(host, ATMCI_CR, ATMCI_CR_MCIEN);
|
2011-08-11 09:25:44 -06:00
|
|
|
if (host->caps.has_cfg_reg)
|
2011-08-11 09:25:42 -06:00
|
|
|
atmci_writel(host, ATMCI_CFG, host->cfg_reg);
|
atmel-mci: support multiple mmc slots
The Atmel MCI controller can drive multiple cards through separate sets
of pins, but only one at a time. This patch adds support for
multiplexing access to the controller so that multiple card slots can be
used as if they were hooked up to separate mmc controllers.
The atmel-mci driver registers each slot as a separate mmc_host. Both
access the same common controller state, but they also have some state
on their own for card detection/write protect handling, and separate
shadows of the MR and SDCR registers.
When one of the slots receives a request from the mmc core, the common
controller state is checked. If it's idle, the request is submitted
immediately. If not, the request is added to a queue. When a request is
done, the queue is checked and if there is a queued request, it is
submitted before the completion callback is called.
This patch also includes a few cleanups and fixes, including a locking
overhaul. I had to change the locking extensively in any case, so I
might as well try to get it right. The driver no longer takes any
irq-safe locks, which may or may not improve the overall system
performance.
This patch also adds a bit of documentation of the internal data
structures.
Signed-off-by: Haavard Skinnemoen <haavard.skinnemoen@atmel.com>
2008-09-17 12:53:55 -06:00
|
|
|
}
|
2008-10-03 09:48:16 -06:00
|
|
|
|
atmel-mci: support multiple mmc slots
The Atmel MCI controller can drive multiple cards through separate sets
of pins, but only one at a time. This patch adds support for
multiplexing access to the controller so that multiple card slots can be
used as if they were hooked up to separate mmc controllers.
The atmel-mci driver registers each slot as a separate mmc_host. Both
access the same common controller state, but they also have some state
on their own for card detection/write protect handling, and separate
shadows of the MR and SDCR registers.
When one of the slots receives a request from the mmc core, the common
controller state is checked. If it's idle, the request is submitted
immediately. If not, the request is added to a queue. When a request is
done, the queue is checked and if there is a queued request, it is
submitted before the completion callback is called.
This patch also includes a few cleanups and fixes, including a locking
overhaul. I had to change the locking extensively in any case, so I
might as well try to get it right. The driver no longer takes any
irq-safe locks, which may or may not improve the overall system
performance.
This patch also adds a bit of documentation of the internal data
structures.
Signed-off-by: Haavard Skinnemoen <haavard.skinnemoen@atmel.com>
2008-09-17 12:53:55 -06:00
|
|
|
/*
|
|
|
|
* Use mirror of ios->clock to prevent race with mmc
|
|
|
|
* core ios update when finding the minimum.
|
|
|
|
*/
|
|
|
|
slot->clock = ios->clock;
|
2011-08-11 09:25:41 -06:00
|
|
|
for (i = 0; i < ATMCI_MAX_NR_SLOTS; i++) {
|
atmel-mci: support multiple mmc slots
The Atmel MCI controller can drive multiple cards through separate sets
of pins, but only one at a time. This patch adds support for
multiplexing access to the controller so that multiple card slots can be
used as if they were hooked up to separate mmc controllers.
The atmel-mci driver registers each slot as a separate mmc_host. Both
access the same common controller state, but they also have some state
on their own for card detection/write protect handling, and separate
shadows of the MR and SDCR registers.
When one of the slots receives a request from the mmc core, the common
controller state is checked. If it's idle, the request is submitted
immediately. If not, the request is added to a queue. When a request is
done, the queue is checked and if there is a queued request, it is
submitted before the completion callback is called.
This patch also includes a few cleanups and fixes, including a locking
overhaul. I had to change the locking extensively in any case, so I
might as well try to get it right. The driver no longer takes any
irq-safe locks, which may or may not improve the overall system
performance.
This patch also adds a bit of documentation of the internal data
structures.
Signed-off-by: Haavard Skinnemoen <haavard.skinnemoen@atmel.com>
2008-09-17 12:53:55 -06:00
|
|
|
if (host->slot[i] && host->slot[i]->clock
|
|
|
|
&& host->slot[i]->clock < clock_min)
|
|
|
|
clock_min = host->slot[i]->clock;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* Calculate clock divider */
|
2012-03-21 09:41:23 -06:00
|
|
|
if (host->caps.has_odd_clk_div) {
|
|
|
|
clkdiv = DIV_ROUND_UP(host->bus_hz, clock_min) - 2;
|
2015-05-06 07:16:46 -06:00
|
|
|
if (clkdiv < 0) {
|
|
|
|
dev_warn(&mmc->class_dev,
|
|
|
|
"clock %u too fast; using %lu\n",
|
|
|
|
clock_min, host->bus_hz / 2);
|
|
|
|
clkdiv = 0;
|
|
|
|
} else if (clkdiv > 511) {
|
2012-03-21 09:41:23 -06:00
|
|
|
dev_warn(&mmc->class_dev,
|
|
|
|
"clock %u too slow; using %lu\n",
|
|
|
|
clock_min, host->bus_hz / (511 + 2));
|
|
|
|
clkdiv = 511;
|
|
|
|
}
|
|
|
|
host->mode_reg = ATMCI_MR_CLKDIV(clkdiv >> 1)
|
|
|
|
| ATMCI_MR_CLKODD(clkdiv & 1);
|
|
|
|
} else {
|
|
|
|
clkdiv = DIV_ROUND_UP(host->bus_hz, 2 * clock_min) - 1;
|
|
|
|
if (clkdiv > 255) {
|
|
|
|
dev_warn(&mmc->class_dev,
|
|
|
|
"clock %u too slow; using %lu\n",
|
|
|
|
clock_min, host->bus_hz / (2 * 256));
|
|
|
|
clkdiv = 255;
|
|
|
|
}
|
|
|
|
host->mode_reg = ATMCI_MR_CLKDIV(clkdiv);
|
atmel-mci: Driver for Atmel on-chip MMC controllers
This is a driver for the MMC controller on the AP7000 chips from
Atmel. It should in theory work on AT91 systems too with some
tweaking, but since the DMA interface is quite different, it's not
entirely clear if it's worth merging this with the at91_mci driver.
This driver has been around for a while in BSPs and kernel sources
provided by Atmel, but this particular version uses the generic DMA
Engine framework (with the slave extensions) instead of an
avr32-only DMA controller framework.
This driver can also use PIO transfers when no DMA channels are
available, and for transfers where using DMA may be difficult or
impractical for some reason (e.g. the DMA setup overhead is usually
not worth it for very short transfers, and badly aligned buffers or
lengths are difficult to handle.)
Currently, the driver only support PIO transfers. DMA support has been
split out to a separate patch to hopefully make it easier to review.
The driver has been tested using mmc-block and ext3fs on several SD,
SDHC and MMC+ cards. Reads and writes work fine, with read transfer
rates up to 3.5 MiB/s on fast cards with debugging disabled.
The driver has also been tested using the mmc_test module on the same
cards. All tests except 7, 9, 15 and 17 succeed. The first two are
unsupported by all the cards I have, so I don't know if the driver
handles this correctly. The last two fail because the hardware flags a
Data CRC Error instead of a Data Timeout error. I'm not sure how to deal
with that.
Documentation for this controller can be found in many data sheets from
Atmel, including the AT32AP7000 data sheet which can be found here:
http://www.atmel.com/dyn/products/datasheets.asp?family_id=682
Signed-off-by: Haavard Skinnemoen <haavard.skinnemoen@atmel.com>
Signed-off-by: Pierre Ossman <drzeus@drzeus.cx>
2008-06-30 10:35:03 -06:00
|
|
|
}
|
|
|
|
|
atmel-mci: support multiple mmc slots
The Atmel MCI controller can drive multiple cards through separate sets
of pins, but only one at a time. This patch adds support for
multiplexing access to the controller so that multiple card slots can be
used as if they were hooked up to separate mmc controllers.
The atmel-mci driver registers each slot as a separate mmc_host. Both
access the same common controller state, but they also have some state
on their own for card detection/write protect handling, and separate
shadows of the MR and SDCR registers.
When one of the slots receives a request from the mmc core, the common
controller state is checked. If it's idle, the request is submitted
immediately. If not, the request is added to a queue. When a request is
done, the queue is checked and if there is a queued request, it is
submitted before the completion callback is called.
This patch also includes a few cleanups and fixes, including a locking
overhaul. I had to change the locking extensively in any case, so I
might as well try to get it right. The driver no longer takes any
irq-safe locks, which may or may not improve the overall system
performance.
This patch also adds a bit of documentation of the internal data
structures.
Signed-off-by: Haavard Skinnemoen <haavard.skinnemoen@atmel.com>
2008-09-17 12:53:55 -06:00
|
|
|
/*
|
|
|
|
* WRPROOF and RDPROOF prevent overruns/underruns by
|
|
|
|
* stopping the clock when the FIFO is full/empty.
|
|
|
|
* This state is not expected to last for long.
|
|
|
|
*/
|
2011-08-11 09:25:44 -06:00
|
|
|
if (host->caps.has_rwproof)
|
2011-08-11 09:25:41 -06:00
|
|
|
host->mode_reg |= (ATMCI_MR_WRPROOF | ATMCI_MR_RDPROOF);
|
atmel-mci: Driver for Atmel on-chip MMC controllers
This is a driver for the MMC controller on the AP7000 chips from
Atmel. It should in theory work on AT91 systems too with some
tweaking, but since the DMA interface is quite different, it's not
entirely clear if it's worth merging this with the at91_mci driver.
This driver has been around for a while in BSPs and kernel sources
provided by Atmel, but this particular version uses the generic DMA
Engine framework (with the slave extensions) instead of an
avr32-only DMA controller framework.
This driver can also use PIO transfers when no DMA channels are
available, and for transfers where using DMA may be difficult or
impractical for some reason (e.g. the DMA setup overhead is usually
not worth it for very short transfers, and badly aligned buffers or
lengths are difficult to handle.)
Currently, the driver only support PIO transfers. DMA support has been
split out to a separate patch to hopefully make it easier to review.
The driver has been tested using mmc-block and ext3fs on several SD,
SDHC and MMC+ cards. Reads and writes work fine, with read transfer
rates up to 3.5 MiB/s on fast cards with debugging disabled.
The driver has also been tested using the mmc_test module on the same
cards. All tests except 7, 9, 15 and 17 succeed. The first two are
unsupported by all the cards I have, so I don't know if the driver
handles this correctly. The last two fail because the hardware flags a
Data CRC Error instead of a Data Timeout error. I'm not sure how to deal
with that.
Documentation for this controller can be found in many data sheets from
Atmel, including the AT32AP7000 data sheet which can be found here:
http://www.atmel.com/dyn/products/datasheets.asp?family_id=682
Signed-off-by: Haavard Skinnemoen <haavard.skinnemoen@atmel.com>
Signed-off-by: Pierre Ossman <drzeus@drzeus.cx>
2008-06-30 10:35:03 -06:00
|
|
|
|
2011-08-11 09:25:44 -06:00
|
|
|
if (host->caps.has_cfg_reg) {
|
2010-05-26 15:41:59 -06:00
|
|
|
/* setup High Speed mode in relation with card capacity */
|
|
|
|
if (ios->timing == MMC_TIMING_SD_HS)
|
2011-08-11 09:25:41 -06:00
|
|
|
host->cfg_reg |= ATMCI_CFG_HSMODE;
|
2010-05-26 15:41:59 -06:00
|
|
|
else
|
2011-08-11 09:25:41 -06:00
|
|
|
host->cfg_reg &= ~ATMCI_CFG_HSMODE;
|
2010-05-26 15:41:59 -06:00
|
|
|
}
|
|
|
|
|
|
|
|
if (list_empty(&host->queue)) {
|
2011-08-11 09:25:42 -06:00
|
|
|
atmci_writel(host, ATMCI_MR, host->mode_reg);
|
2011-08-11 09:25:44 -06:00
|
|
|
if (host->caps.has_cfg_reg)
|
2011-08-11 09:25:42 -06:00
|
|
|
atmci_writel(host, ATMCI_CFG, host->cfg_reg);
|
2010-05-26 15:41:59 -06:00
|
|
|
} else {
|
atmel-mci: support multiple mmc slots
The Atmel MCI controller can drive multiple cards through separate sets
of pins, but only one at a time. This patch adds support for
multiplexing access to the controller so that multiple card slots can be
used as if they were hooked up to separate mmc controllers.
The atmel-mci driver registers each slot as a separate mmc_host. Both
access the same common controller state, but they also have some state
on their own for card detection/write protect handling, and separate
shadows of the MR and SDCR registers.
When one of the slots receives a request from the mmc core, the common
controller state is checked. If it's idle, the request is submitted
immediately. If not, the request is added to a queue. When a request is
done, the queue is checked and if there is a queued request, it is
submitted before the completion callback is called.
This patch also includes a few cleanups and fixes, including a locking
overhaul. I had to change the locking extensively in any case, so I
might as well try to get it right. The driver no longer takes any
irq-safe locks, which may or may not improve the overall system
performance.
This patch also adds a bit of documentation of the internal data
structures.
Signed-off-by: Haavard Skinnemoen <haavard.skinnemoen@atmel.com>
2008-09-17 12:53:55 -06:00
|
|
|
host->need_clock_update = true;
|
2010-05-26 15:41:59 -06:00
|
|
|
}
|
atmel-mci: support multiple mmc slots
The Atmel MCI controller can drive multiple cards through separate sets
of pins, but only one at a time. This patch adds support for
multiplexing access to the controller so that multiple card slots can be
used as if they were hooked up to separate mmc controllers.
The atmel-mci driver registers each slot as a separate mmc_host. Both
access the same common controller state, but they also have some state
on their own for card detection/write protect handling, and separate
shadows of the MR and SDCR registers.
When one of the slots receives a request from the mmc core, the common
controller state is checked. If it's idle, the request is submitted
immediately. If not, the request is added to a queue. When a request is
done, the queue is checked and if there is a queued request, it is
submitted before the completion callback is called.
This patch also includes a few cleanups and fixes, including a locking
overhaul. I had to change the locking extensively in any case, so I
might as well try to get it right. The driver no longer takes any
irq-safe locks, which may or may not improve the overall system
performance.
This patch also adds a bit of documentation of the internal data
structures.
Signed-off-by: Haavard Skinnemoen <haavard.skinnemoen@atmel.com>
2008-09-17 12:53:55 -06:00
|
|
|
|
|
|
|
spin_unlock_bh(&host->lock);
|
2008-10-03 09:48:16 -06:00
|
|
|
} else {
|
atmel-mci: support multiple mmc slots
The Atmel MCI controller can drive multiple cards through separate sets
of pins, but only one at a time. This patch adds support for
multiplexing access to the controller so that multiple card slots can be
used as if they were hooked up to separate mmc controllers.
The atmel-mci driver registers each slot as a separate mmc_host. Both
access the same common controller state, but they also have some state
on their own for card detection/write protect handling, and separate
shadows of the MR and SDCR registers.
When one of the slots receives a request from the mmc core, the common
controller state is checked. If it's idle, the request is submitted
immediately. If not, the request is added to a queue. When a request is
done, the queue is checked and if there is a queued request, it is
submitted before the completion callback is called.
This patch also includes a few cleanups and fixes, including a locking
overhaul. I had to change the locking extensively in any case, so I
might as well try to get it right. The driver no longer takes any
irq-safe locks, which may or may not improve the overall system
performance.
This patch also adds a bit of documentation of the internal data
structures.
Signed-off-by: Haavard Skinnemoen <haavard.skinnemoen@atmel.com>
2008-09-17 12:53:55 -06:00
|
|
|
bool any_slot_active = false;
|
|
|
|
|
|
|
|
spin_lock_bh(&host->lock);
|
|
|
|
slot->clock = 0;
|
2011-08-11 09:25:41 -06:00
|
|
|
for (i = 0; i < ATMCI_MAX_NR_SLOTS; i++) {
|
atmel-mci: support multiple mmc slots
The Atmel MCI controller can drive multiple cards through separate sets
of pins, but only one at a time. This patch adds support for
multiplexing access to the controller so that multiple card slots can be
used as if they were hooked up to separate mmc controllers.
The atmel-mci driver registers each slot as a separate mmc_host. Both
access the same common controller state, but they also have some state
on their own for card detection/write protect handling, and separate
shadows of the MR and SDCR registers.
When one of the slots receives a request from the mmc core, the common
controller state is checked. If it's idle, the request is submitted
immediately. If not, the request is added to a queue. When a request is
done, the queue is checked and if there is a queued request, it is
submitted before the completion callback is called.
This patch also includes a few cleanups and fixes, including a locking
overhaul. I had to change the locking extensively in any case, so I
might as well try to get it right. The driver no longer takes any
irq-safe locks, which may or may not improve the overall system
performance.
This patch also adds a bit of documentation of the internal data
structures.
Signed-off-by: Haavard Skinnemoen <haavard.skinnemoen@atmel.com>
2008-09-17 12:53:55 -06:00
|
|
|
if (host->slot[i] && host->slot[i]->clock) {
|
|
|
|
any_slot_active = true;
|
|
|
|
break;
|
|
|
|
}
|
2008-10-03 09:48:16 -06:00
|
|
|
}
|
atmel-mci: support multiple mmc slots
The Atmel MCI controller can drive multiple cards through separate sets
of pins, but only one at a time. This patch adds support for
multiplexing access to the controller so that multiple card slots can be
used as if they were hooked up to separate mmc controllers.
The atmel-mci driver registers each slot as a separate mmc_host. Both
access the same common controller state, but they also have some state
on their own for card detection/write protect handling, and separate
shadows of the MR and SDCR registers.
When one of the slots receives a request from the mmc core, the common
controller state is checked. If it's idle, the request is submitted
immediately. If not, the request is added to a queue. When a request is
done, the queue is checked and if there is a queued request, it is
submitted before the completion callback is called.
This patch also includes a few cleanups and fixes, including a locking
overhaul. I had to change the locking extensively in any case, so I
might as well try to get it right. The driver no longer takes any
irq-safe locks, which may or may not improve the overall system
performance.
This patch also adds a bit of documentation of the internal data
structures.
Signed-off-by: Haavard Skinnemoen <haavard.skinnemoen@atmel.com>
2008-09-17 12:53:55 -06:00
|
|
|
if (!any_slot_active) {
|
2011-08-11 09:25:42 -06:00
|
|
|
atmci_writel(host, ATMCI_CR, ATMCI_CR_MCIDIS);
|
atmel-mci: support multiple mmc slots
The Atmel MCI controller can drive multiple cards through separate sets
of pins, but only one at a time. This patch adds support for
multiplexing access to the controller so that multiple card slots can be
used as if they were hooked up to separate mmc controllers.
The atmel-mci driver registers each slot as a separate mmc_host. Both
access the same common controller state, but they also have some state
on their own for card detection/write protect handling, and separate
shadows of the MR and SDCR registers.
When one of the slots receives a request from the mmc core, the common
controller state is checked. If it's idle, the request is submitted
immediately. If not, the request is added to a queue. When a request is
done, the queue is checked and if there is a queued request, it is
submitted before the completion callback is called.
This patch also includes a few cleanups and fixes, including a locking
overhaul. I had to change the locking extensively in any case, so I
might as well try to get it right. The driver no longer takes any
irq-safe locks, which may or may not improve the overall system
performance.
This patch also adds a bit of documentation of the internal data
structures.
Signed-off-by: Haavard Skinnemoen <haavard.skinnemoen@atmel.com>
2008-09-17 12:53:55 -06:00
|
|
|
if (host->mode_reg) {
|
2011-08-11 09:25:42 -06:00
|
|
|
atmci_readl(host, ATMCI_MR);
|
atmel-mci: support multiple mmc slots
The Atmel MCI controller can drive multiple cards through separate sets
of pins, but only one at a time. This patch adds support for
multiplexing access to the controller so that multiple card slots can be
used as if they were hooked up to separate mmc controllers.
The atmel-mci driver registers each slot as a separate mmc_host. Both
access the same common controller state, but they also have some state
on their own for card detection/write protect handling, and separate
shadows of the MR and SDCR registers.
When one of the slots receives a request from the mmc core, the common
controller state is checked. If it's idle, the request is submitted
immediately. If not, the request is added to a queue. When a request is
done, the queue is checked and if there is a queued request, it is
submitted before the completion callback is called.
This patch also includes a few cleanups and fixes, including a locking
overhaul. I had to change the locking extensively in any case, so I
might as well try to get it right. The driver no longer takes any
irq-safe locks, which may or may not improve the overall system
performance.
This patch also adds a bit of documentation of the internal data
structures.
Signed-off-by: Haavard Skinnemoen <haavard.skinnemoen@atmel.com>
2008-09-17 12:53:55 -06:00
|
|
|
}
|
|
|
|
host->mode_reg = 0;
|
|
|
|
}
|
|
|
|
spin_unlock_bh(&host->lock);
|
atmel-mci: Driver for Atmel on-chip MMC controllers
This is a driver for the MMC controller on the AP7000 chips from
Atmel. It should in theory work on AT91 systems too with some
tweaking, but since the DMA interface is quite different, it's not
entirely clear if it's worth merging this with the at91_mci driver.
This driver has been around for a while in BSPs and kernel sources
provided by Atmel, but this particular version uses the generic DMA
Engine framework (with the slave extensions) instead of an
avr32-only DMA controller framework.
This driver can also use PIO transfers when no DMA channels are
available, and for transfers where using DMA may be difficult or
impractical for some reason (e.g. the DMA setup overhead is usually
not worth it for very short transfers, and badly aligned buffers or
lengths are difficult to handle.)
Currently, the driver only support PIO transfers. DMA support has been
split out to a separate patch to hopefully make it easier to review.
The driver has been tested using mmc-block and ext3fs on several SD,
SDHC and MMC+ cards. Reads and writes work fine, with read transfer
rates up to 3.5 MiB/s on fast cards with debugging disabled.
The driver has also been tested using the mmc_test module on the same
cards. All tests except 7, 9, 15 and 17 succeed. The first two are
unsupported by all the cards I have, so I don't know if the driver
handles this correctly. The last two fail because the hardware flags a
Data CRC Error instead of a Data Timeout error. I'm not sure how to deal
with that.
Documentation for this controller can be found in many data sheets from
Atmel, including the AT32AP7000 data sheet which can be found here:
http://www.atmel.com/dyn/products/datasheets.asp?family_id=682
Signed-off-by: Haavard Skinnemoen <haavard.skinnemoen@atmel.com>
Signed-off-by: Pierre Ossman <drzeus@drzeus.cx>
2008-06-30 10:35:03 -06:00
|
|
|
}
|
|
|
|
|
|
|
|
switch (ios->power_mode) {
|
2013-10-17 04:46:48 -06:00
|
|
|
case MMC_POWER_OFF:
|
|
|
|
if (!IS_ERR(mmc->supply.vmmc))
|
|
|
|
mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, 0);
|
|
|
|
break;
|
atmel-mci: support multiple mmc slots
The Atmel MCI controller can drive multiple cards through separate sets
of pins, but only one at a time. This patch adds support for
multiplexing access to the controller so that multiple card slots can be
used as if they were hooked up to separate mmc controllers.
The atmel-mci driver registers each slot as a separate mmc_host. Both
access the same common controller state, but they also have some state
on their own for card detection/write protect handling, and separate
shadows of the MR and SDCR registers.
When one of the slots receives a request from the mmc core, the common
controller state is checked. If it's idle, the request is submitted
immediately. If not, the request is added to a queue. When a request is
done, the queue is checked and if there is a queued request, it is
submitted before the completion callback is called.
This patch also includes a few cleanups and fixes, including a locking
overhaul. I had to change the locking extensively in any case, so I
might as well try to get it right. The driver no longer takes any
irq-safe locks, which may or may not improve the overall system
performance.
This patch also adds a bit of documentation of the internal data
structures.
Signed-off-by: Haavard Skinnemoen <haavard.skinnemoen@atmel.com>
2008-09-17 12:53:55 -06:00
|
|
|
case MMC_POWER_UP:
|
|
|
|
set_bit(ATMCI_CARD_NEED_INIT, &slot->flags);
|
2013-10-17 04:46:48 -06:00
|
|
|
if (!IS_ERR(mmc->supply.vmmc))
|
|
|
|
mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, ios->vdd);
|
atmel-mci: support multiple mmc slots
The Atmel MCI controller can drive multiple cards through separate sets
of pins, but only one at a time. This patch adds support for
multiplexing access to the controller so that multiple card slots can be
used as if they were hooked up to separate mmc controllers.
The atmel-mci driver registers each slot as a separate mmc_host. Both
access the same common controller state, but they also have some state
on their own for card detection/write protect handling, and separate
shadows of the MR and SDCR registers.
When one of the slots receives a request from the mmc core, the common
controller state is checked. If it's idle, the request is submitted
immediately. If not, the request is added to a queue. When a request is
done, the queue is checked and if there is a queued request, it is
submitted before the completion callback is called.
This patch also includes a few cleanups and fixes, including a locking
overhaul. I had to change the locking extensively in any case, so I
might as well try to get it right. The driver no longer takes any
irq-safe locks, which may or may not improve the overall system
performance.
This patch also adds a bit of documentation of the internal data
structures.
Signed-off-by: Haavard Skinnemoen <haavard.skinnemoen@atmel.com>
2008-09-17 12:53:55 -06:00
|
|
|
break;
|
atmel-mci: Driver for Atmel on-chip MMC controllers
This is a driver for the MMC controller on the AP7000 chips from
Atmel. It should in theory work on AT91 systems too with some
tweaking, but since the DMA interface is quite different, it's not
entirely clear if it's worth merging this with the at91_mci driver.
This driver has been around for a while in BSPs and kernel sources
provided by Atmel, but this particular version uses the generic DMA
Engine framework (with the slave extensions) instead of an
avr32-only DMA controller framework.
This driver can also use PIO transfers when no DMA channels are
available, and for transfers where using DMA may be difficult or
impractical for some reason (e.g. the DMA setup overhead is usually
not worth it for very short transfers, and badly aligned buffers or
lengths are difficult to handle.)
Currently, the driver only support PIO transfers. DMA support has been
split out to a separate patch to hopefully make it easier to review.
The driver has been tested using mmc-block and ext3fs on several SD,
SDHC and MMC+ cards. Reads and writes work fine, with read transfer
rates up to 3.5 MiB/s on fast cards with debugging disabled.
The driver has also been tested using the mmc_test module on the same
cards. All tests except 7, 9, 15 and 17 succeed. The first two are
unsupported by all the cards I have, so I don't know if the driver
handles this correctly. The last two fail because the hardware flags a
Data CRC Error instead of a Data Timeout error. I'm not sure how to deal
with that.
Documentation for this controller can be found in many data sheets from
Atmel, including the AT32AP7000 data sheet which can be found here:
http://www.atmel.com/dyn/products/datasheets.asp?family_id=682
Signed-off-by: Haavard Skinnemoen <haavard.skinnemoen@atmel.com>
Signed-off-by: Pierre Ossman <drzeus@drzeus.cx>
2008-06-30 10:35:03 -06:00
|
|
|
default:
|
|
|
|
/*
|
|
|
|
* TODO: None of the currently available AVR32-based
|
|
|
|
* boards allow MMC power to be turned off. Implement
|
|
|
|
* power control when this can be tested properly.
|
atmel-mci: support multiple mmc slots
The Atmel MCI controller can drive multiple cards through separate sets
of pins, but only one at a time. This patch adds support for
multiplexing access to the controller so that multiple card slots can be
used as if they were hooked up to separate mmc controllers.
The atmel-mci driver registers each slot as a separate mmc_host. Both
access the same common controller state, but they also have some state
on their own for card detection/write protect handling, and separate
shadows of the MR and SDCR registers.
When one of the slots receives a request from the mmc core, the common
controller state is checked. If it's idle, the request is submitted
immediately. If not, the request is added to a queue. When a request is
done, the queue is checked and if there is a queued request, it is
submitted before the completion callback is called.
This patch also includes a few cleanups and fixes, including a locking
overhaul. I had to change the locking extensively in any case, so I
might as well try to get it right. The driver no longer takes any
irq-safe locks, which may or may not improve the overall system
performance.
This patch also adds a bit of documentation of the internal data
structures.
Signed-off-by: Haavard Skinnemoen <haavard.skinnemoen@atmel.com>
2008-09-17 12:53:55 -06:00
|
|
|
*
|
|
|
|
* We also need to hook this into the clock management
|
|
|
|
* somehow so that newly inserted cards aren't
|
|
|
|
* subjected to a fast clock before we have a chance
|
|
|
|
* to figure out what the maximum rate is. Currently,
|
|
|
|
* there's no way to avoid this, and there never will
|
|
|
|
* be for boards that don't support power control.
|
atmel-mci: Driver for Atmel on-chip MMC controllers
This is a driver for the MMC controller on the AP7000 chips from
Atmel. It should in theory work on AT91 systems too with some
tweaking, but since the DMA interface is quite different, it's not
entirely clear if it's worth merging this with the at91_mci driver.
This driver has been around for a while in BSPs and kernel sources
provided by Atmel, but this particular version uses the generic DMA
Engine framework (with the slave extensions) instead of an
avr32-only DMA controller framework.
This driver can also use PIO transfers when no DMA channels are
available, and for transfers where using DMA may be difficult or
impractical for some reason (e.g. the DMA setup overhead is usually
not worth it for very short transfers, and badly aligned buffers or
lengths are difficult to handle.)
Currently, the driver only support PIO transfers. DMA support has been
split out to a separate patch to hopefully make it easier to review.
The driver has been tested using mmc-block and ext3fs on several SD,
SDHC and MMC+ cards. Reads and writes work fine, with read transfer
rates up to 3.5 MiB/s on fast cards with debugging disabled.
The driver has also been tested using the mmc_test module on the same
cards. All tests except 7, 9, 15 and 17 succeed. The first two are
unsupported by all the cards I have, so I don't know if the driver
handles this correctly. The last two fail because the hardware flags a
Data CRC Error instead of a Data Timeout error. I'm not sure how to deal
with that.
Documentation for this controller can be found in many data sheets from
Atmel, including the AT32AP7000 data sheet which can be found here:
http://www.atmel.com/dyn/products/datasheets.asp?family_id=682
Signed-off-by: Haavard Skinnemoen <haavard.skinnemoen@atmel.com>
Signed-off-by: Pierre Ossman <drzeus@drzeus.cx>
2008-06-30 10:35:03 -06:00
|
|
|
*/
|
|
|
|
break;
|
|
|
|
}
|
2014-10-29 22:00:41 -06:00
|
|
|
|
atmel-mci: Driver for Atmel on-chip MMC controllers
This is a driver for the MMC controller on the AP7000 chips from
Atmel. It should in theory work on AT91 systems too with some
tweaking, but since the DMA interface is quite different, it's not
entirely clear if it's worth merging this with the at91_mci driver.
This driver has been around for a while in BSPs and kernel sources
provided by Atmel, but this particular version uses the generic DMA
Engine framework (with the slave extensions) instead of an
avr32-only DMA controller framework.
This driver can also use PIO transfers when no DMA channels are
available, and for transfers where using DMA may be difficult or
impractical for some reason (e.g. the DMA setup overhead is usually
not worth it for very short transfers, and badly aligned buffers or
lengths are difficult to handle.)
Currently, the driver only support PIO transfers. DMA support has been
split out to a separate patch to hopefully make it easier to review.
The driver has been tested using mmc-block and ext3fs on several SD,
SDHC and MMC+ cards. Reads and writes work fine, with read transfer
rates up to 3.5 MiB/s on fast cards with debugging disabled.
The driver has also been tested using the mmc_test module on the same
cards. All tests except 7, 9, 15 and 17 succeed. The first two are
unsupported by all the cards I have, so I don't know if the driver
handles this correctly. The last two fail because the hardware flags a
Data CRC Error instead of a Data Timeout error. I'm not sure how to deal
with that.
Documentation for this controller can be found in many data sheets from
Atmel, including the AT32AP7000 data sheet which can be found here:
http://www.atmel.com/dyn/products/datasheets.asp?family_id=682
Signed-off-by: Haavard Skinnemoen <haavard.skinnemoen@atmel.com>
Signed-off-by: Pierre Ossman <drzeus@drzeus.cx>
2008-06-30 10:35:03 -06:00
|
|
|
}
|
|
|
|
|
|
|
|
static int atmci_get_ro(struct mmc_host *mmc)
|
|
|
|
{
|
atmel-mci: support multiple mmc slots
The Atmel MCI controller can drive multiple cards through separate sets
of pins, but only one at a time. This patch adds support for
multiplexing access to the controller so that multiple card slots can be
used as if they were hooked up to separate mmc controllers.
The atmel-mci driver registers each slot as a separate mmc_host. Both
access the same common controller state, but they also have some state
on their own for card detection/write protect handling, and separate
shadows of the MR and SDCR registers.
When one of the slots receives a request from the mmc core, the common
controller state is checked. If it's idle, the request is submitted
immediately. If not, the request is added to a queue. When a request is
done, the queue is checked and if there is a queued request, it is
submitted before the completion callback is called.
This patch also includes a few cleanups and fixes, including a locking
overhaul. I had to change the locking extensively in any case, so I
might as well try to get it right. The driver no longer takes any
irq-safe locks, which may or may not improve the overall system
performance.
This patch also adds a bit of documentation of the internal data
structures.
Signed-off-by: Haavard Skinnemoen <haavard.skinnemoen@atmel.com>
2008-09-17 12:53:55 -06:00
|
|
|
int read_only = -ENOSYS;
|
|
|
|
struct atmel_mci_slot *slot = mmc_priv(mmc);
|
atmel-mci: Driver for Atmel on-chip MMC controllers
This is a driver for the MMC controller on the AP7000 chips from
Atmel. It should in theory work on AT91 systems too with some
tweaking, but since the DMA interface is quite different, it's not
entirely clear if it's worth merging this with the at91_mci driver.
This driver has been around for a while in BSPs and kernel sources
provided by Atmel, but this particular version uses the generic DMA
Engine framework (with the slave extensions) instead of an
avr32-only DMA controller framework.
This driver can also use PIO transfers when no DMA channels are
available, and for transfers where using DMA may be difficult or
impractical for some reason (e.g. the DMA setup overhead is usually
not worth it for very short transfers, and badly aligned buffers or
lengths are difficult to handle.)
Currently, the driver only support PIO transfers. DMA support has been
split out to a separate patch to hopefully make it easier to review.
The driver has been tested using mmc-block and ext3fs on several SD,
SDHC and MMC+ cards. Reads and writes work fine, with read transfer
rates up to 3.5 MiB/s on fast cards with debugging disabled.
The driver has also been tested using the mmc_test module on the same
cards. All tests except 7, 9, 15 and 17 succeed. The first two are
unsupported by all the cards I have, so I don't know if the driver
handles this correctly. The last two fail because the hardware flags a
Data CRC Error instead of a Data Timeout error. I'm not sure how to deal
with that.
Documentation for this controller can be found in many data sheets from
Atmel, including the AT32AP7000 data sheet which can be found here:
http://www.atmel.com/dyn/products/datasheets.asp?family_id=682
Signed-off-by: Haavard Skinnemoen <haavard.skinnemoen@atmel.com>
Signed-off-by: Pierre Ossman <drzeus@drzeus.cx>
2008-06-30 10:35:03 -06:00
|
|
|
|
atmel-mci: support multiple mmc slots
The Atmel MCI controller can drive multiple cards through separate sets
of pins, but only one at a time. This patch adds support for
multiplexing access to the controller so that multiple card slots can be
used as if they were hooked up to separate mmc controllers.
The atmel-mci driver registers each slot as a separate mmc_host. Both
access the same common controller state, but they also have some state
on their own for card detection/write protect handling, and separate
shadows of the MR and SDCR registers.
When one of the slots receives a request from the mmc core, the common
controller state is checked. If it's idle, the request is submitted
immediately. If not, the request is added to a queue. When a request is
done, the queue is checked and if there is a queued request, it is
submitted before the completion callback is called.
This patch also includes a few cleanups and fixes, including a locking
overhaul. I had to change the locking extensively in any case, so I
might as well try to get it right. The driver no longer takes any
irq-safe locks, which may or may not improve the overall system
performance.
This patch also adds a bit of documentation of the internal data
structures.
Signed-off-by: Haavard Skinnemoen <haavard.skinnemoen@atmel.com>
2008-09-17 12:53:55 -06:00
|
|
|
if (gpio_is_valid(slot->wp_pin)) {
|
|
|
|
read_only = gpio_get_value(slot->wp_pin);
|
atmel-mci: Driver for Atmel on-chip MMC controllers
This is a driver for the MMC controller on the AP7000 chips from
Atmel. It should in theory work on AT91 systems too with some
tweaking, but since the DMA interface is quite different, it's not
entirely clear if it's worth merging this with the at91_mci driver.
This driver has been around for a while in BSPs and kernel sources
provided by Atmel, but this particular version uses the generic DMA
Engine framework (with the slave extensions) instead of an
avr32-only DMA controller framework.
This driver can also use PIO transfers when no DMA channels are
available, and for transfers where using DMA may be difficult or
impractical for some reason (e.g. the DMA setup overhead is usually
not worth it for very short transfers, and badly aligned buffers or
lengths are difficult to handle.)
Currently, the driver only support PIO transfers. DMA support has been
split out to a separate patch to hopefully make it easier to review.
The driver has been tested using mmc-block and ext3fs on several SD,
SDHC and MMC+ cards. Reads and writes work fine, with read transfer
rates up to 3.5 MiB/s on fast cards with debugging disabled.
The driver has also been tested using the mmc_test module on the same
cards. All tests except 7, 9, 15 and 17 succeed. The first two are
unsupported by all the cards I have, so I don't know if the driver
handles this correctly. The last two fail because the hardware flags a
Data CRC Error instead of a Data Timeout error. I'm not sure how to deal
with that.
Documentation for this controller can be found in many data sheets from
Atmel, including the AT32AP7000 data sheet which can be found here:
http://www.atmel.com/dyn/products/datasheets.asp?family_id=682
Signed-off-by: Haavard Skinnemoen <haavard.skinnemoen@atmel.com>
Signed-off-by: Pierre Ossman <drzeus@drzeus.cx>
2008-06-30 10:35:03 -06:00
|
|
|
dev_dbg(&mmc->class_dev, "card is %s\n",
|
|
|
|
read_only ? "read-only" : "read-write");
|
|
|
|
}
|
|
|
|
|
|
|
|
return read_only;
|
|
|
|
}
|
|
|
|
|
atmel-mci: support multiple mmc slots
The Atmel MCI controller can drive multiple cards through separate sets
of pins, but only one at a time. This patch adds support for
multiplexing access to the controller so that multiple card slots can be
used as if they were hooked up to separate mmc controllers.
The atmel-mci driver registers each slot as a separate mmc_host. Both
access the same common controller state, but they also have some state
on their own for card detection/write protect handling, and separate
shadows of the MR and SDCR registers.
When one of the slots receives a request from the mmc core, the common
controller state is checked. If it's idle, the request is submitted
immediately. If not, the request is added to a queue. When a request is
done, the queue is checked and if there is a queued request, it is
submitted before the completion callback is called.
This patch also includes a few cleanups and fixes, including a locking
overhaul. I had to change the locking extensively in any case, so I
might as well try to get it right. The driver no longer takes any
irq-safe locks, which may or may not improve the overall system
performance.
This patch also adds a bit of documentation of the internal data
structures.
Signed-off-by: Haavard Skinnemoen <haavard.skinnemoen@atmel.com>
2008-09-17 12:53:55 -06:00
|
|
|
static int atmci_get_cd(struct mmc_host *mmc)
|
|
|
|
{
|
|
|
|
int present = -ENOSYS;
|
|
|
|
struct atmel_mci_slot *slot = mmc_priv(mmc);
|
|
|
|
|
|
|
|
if (gpio_is_valid(slot->detect_pin)) {
|
2009-03-31 03:16:48 -06:00
|
|
|
present = !(gpio_get_value(slot->detect_pin) ^
|
|
|
|
slot->detect_is_active_high);
|
atmel-mci: support multiple mmc slots
The Atmel MCI controller can drive multiple cards through separate sets
of pins, but only one at a time. This patch adds support for
multiplexing access to the controller so that multiple card slots can be
used as if they were hooked up to separate mmc controllers.
The atmel-mci driver registers each slot as a separate mmc_host. Both
access the same common controller state, but they also have some state
on their own for card detection/write protect handling, and separate
shadows of the MR and SDCR registers.
When one of the slots receives a request from the mmc core, the common
controller state is checked. If it's idle, the request is submitted
immediately. If not, the request is added to a queue. When a request is
done, the queue is checked and if there is a queued request, it is
submitted before the completion callback is called.
This patch also includes a few cleanups and fixes, including a locking
overhaul. I had to change the locking extensively in any case, so I
might as well try to get it right. The driver no longer takes any
irq-safe locks, which may or may not improve the overall system
performance.
This patch also adds a bit of documentation of the internal data
structures.
Signed-off-by: Haavard Skinnemoen <haavard.skinnemoen@atmel.com>
2008-09-17 12:53:55 -06:00
|
|
|
dev_dbg(&mmc->class_dev, "card is %spresent\n",
|
|
|
|
present ? "" : "not ");
|
|
|
|
}
|
|
|
|
|
|
|
|
return present;
|
|
|
|
}
|
|
|
|
|
2010-05-26 15:42:01 -06:00
|
|
|
static void atmci_enable_sdio_irq(struct mmc_host *mmc, int enable)
|
|
|
|
{
|
|
|
|
struct atmel_mci_slot *slot = mmc_priv(mmc);
|
|
|
|
struct atmel_mci *host = slot->host;
|
|
|
|
|
|
|
|
if (enable)
|
2011-08-11 09:25:42 -06:00
|
|
|
atmci_writel(host, ATMCI_IER, slot->sdio_irq);
|
2010-05-26 15:42:01 -06:00
|
|
|
else
|
2011-08-11 09:25:42 -06:00
|
|
|
atmci_writel(host, ATMCI_IDR, slot->sdio_irq);
|
2010-05-26 15:42:01 -06:00
|
|
|
}
|
|
|
|
|
atmel-mci: support multiple mmc slots
The Atmel MCI controller can drive multiple cards through separate sets
of pins, but only one at a time. This patch adds support for
multiplexing access to the controller so that multiple card slots can be
used as if they were hooked up to separate mmc controllers.
The atmel-mci driver registers each slot as a separate mmc_host. Both
access the same common controller state, but they also have some state
on their own for card detection/write protect handling, and separate
shadows of the MR and SDCR registers.
When one of the slots receives a request from the mmc core, the common
controller state is checked. If it's idle, the request is submitted
immediately. If not, the request is added to a queue. When a request is
done, the queue is checked and if there is a queued request, it is
submitted before the completion callback is called.
This patch also includes a few cleanups and fixes, including a locking
overhaul. I had to change the locking extensively in any case, so I
might as well try to get it right. The driver no longer takes any
irq-safe locks, which may or may not improve the overall system
performance.
This patch also adds a bit of documentation of the internal data
structures.
Signed-off-by: Haavard Skinnemoen <haavard.skinnemoen@atmel.com>
2008-09-17 12:53:55 -06:00
|
|
|
static const struct mmc_host_ops atmci_ops = {
|
atmel-mci: Driver for Atmel on-chip MMC controllers
This is a driver for the MMC controller on the AP7000 chips from
Atmel. It should in theory work on AT91 systems too with some
tweaking, but since the DMA interface is quite different, it's not
entirely clear if it's worth merging this with the at91_mci driver.
This driver has been around for a while in BSPs and kernel sources
provided by Atmel, but this particular version uses the generic DMA
Engine framework (with the slave extensions) instead of an
avr32-only DMA controller framework.
This driver can also use PIO transfers when no DMA channels are
available, and for transfers where using DMA may be difficult or
impractical for some reason (e.g. the DMA setup overhead is usually
not worth it for very short transfers, and badly aligned buffers or
lengths are difficult to handle.)
Currently, the driver only support PIO transfers. DMA support has been
split out to a separate patch to hopefully make it easier to review.
The driver has been tested using mmc-block and ext3fs on several SD,
SDHC and MMC+ cards. Reads and writes work fine, with read transfer
rates up to 3.5 MiB/s on fast cards with debugging disabled.
The driver has also been tested using the mmc_test module on the same
cards. All tests except 7, 9, 15 and 17 succeed. The first two are
unsupported by all the cards I have, so I don't know if the driver
handles this correctly. The last two fail because the hardware flags a
Data CRC Error instead of a Data Timeout error. I'm not sure how to deal
with that.
Documentation for this controller can be found in many data sheets from
Atmel, including the AT32AP7000 data sheet which can be found here:
http://www.atmel.com/dyn/products/datasheets.asp?family_id=682
Signed-off-by: Haavard Skinnemoen <haavard.skinnemoen@atmel.com>
Signed-off-by: Pierre Ossman <drzeus@drzeus.cx>
2008-06-30 10:35:03 -06:00
|
|
|
.request = atmci_request,
|
|
|
|
.set_ios = atmci_set_ios,
|
|
|
|
.get_ro = atmci_get_ro,
|
atmel-mci: support multiple mmc slots
The Atmel MCI controller can drive multiple cards through separate sets
of pins, but only one at a time. This patch adds support for
multiplexing access to the controller so that multiple card slots can be
used as if they were hooked up to separate mmc controllers.
The atmel-mci driver registers each slot as a separate mmc_host. Both
access the same common controller state, but they also have some state
on their own for card detection/write protect handling, and separate
shadows of the MR and SDCR registers.
When one of the slots receives a request from the mmc core, the common
controller state is checked. If it's idle, the request is submitted
immediately. If not, the request is added to a queue. When a request is
done, the queue is checked and if there is a queued request, it is
submitted before the completion callback is called.
This patch also includes a few cleanups and fixes, including a locking
overhaul. I had to change the locking extensively in any case, so I
might as well try to get it right. The driver no longer takes any
irq-safe locks, which may or may not improve the overall system
performance.
This patch also adds a bit of documentation of the internal data
structures.
Signed-off-by: Haavard Skinnemoen <haavard.skinnemoen@atmel.com>
2008-09-17 12:53:55 -06:00
|
|
|
.get_cd = atmci_get_cd,
|
2010-05-26 15:42:01 -06:00
|
|
|
.enable_sdio_irq = atmci_enable_sdio_irq,
|
atmel-mci: Driver for Atmel on-chip MMC controllers
This is a driver for the MMC controller on the AP7000 chips from
Atmel. It should in theory work on AT91 systems too with some
tweaking, but since the DMA interface is quite different, it's not
entirely clear if it's worth merging this with the at91_mci driver.
This driver has been around for a while in BSPs and kernel sources
provided by Atmel, but this particular version uses the generic DMA
Engine framework (with the slave extensions) instead of an
avr32-only DMA controller framework.
This driver can also use PIO transfers when no DMA channels are
available, and for transfers where using DMA may be difficult or
impractical for some reason (e.g. the DMA setup overhead is usually
not worth it for very short transfers, and badly aligned buffers or
lengths are difficult to handle.)
Currently, the driver only support PIO transfers. DMA support has been
split out to a separate patch to hopefully make it easier to review.
The driver has been tested using mmc-block and ext3fs on several SD,
SDHC and MMC+ cards. Reads and writes work fine, with read transfer
rates up to 3.5 MiB/s on fast cards with debugging disabled.
The driver has also been tested using the mmc_test module on the same
cards. All tests except 7, 9, 15 and 17 succeed. The first two are
unsupported by all the cards I have, so I don't know if the driver
handles this correctly. The last two fail because the hardware flags a
Data CRC Error instead of a Data Timeout error. I'm not sure how to deal
with that.
Documentation for this controller can be found in many data sheets from
Atmel, including the AT32AP7000 data sheet which can be found here:
http://www.atmel.com/dyn/products/datasheets.asp?family_id=682
Signed-off-by: Haavard Skinnemoen <haavard.skinnemoen@atmel.com>
Signed-off-by: Pierre Ossman <drzeus@drzeus.cx>
2008-06-30 10:35:03 -06:00
|
|
|
};
|
|
|
|
|
atmel-mci: support multiple mmc slots
The Atmel MCI controller can drive multiple cards through separate sets
of pins, but only one at a time. This patch adds support for
multiplexing access to the controller so that multiple card slots can be
used as if they were hooked up to separate mmc controllers.
The atmel-mci driver registers each slot as a separate mmc_host. Both
access the same common controller state, but they also have some state
on their own for card detection/write protect handling, and separate
shadows of the MR and SDCR registers.
When one of the slots receives a request from the mmc core, the common
controller state is checked. If it's idle, the request is submitted
immediately. If not, the request is added to a queue. When a request is
done, the queue is checked and if there is a queued request, it is
submitted before the completion callback is called.
This patch also includes a few cleanups and fixes, including a locking
overhaul. I had to change the locking extensively in any case, so I
might as well try to get it right. The driver no longer takes any
irq-safe locks, which may or may not improve the overall system
performance.
This patch also adds a bit of documentation of the internal data
structures.
Signed-off-by: Haavard Skinnemoen <haavard.skinnemoen@atmel.com>
2008-09-17 12:53:55 -06:00
|
|
|
/* Called with host->lock held */
|
|
|
|
static void atmci_request_end(struct atmel_mci *host, struct mmc_request *mrq)
|
|
|
|
__releases(&host->lock)
|
|
|
|
__acquires(&host->lock)
|
|
|
|
{
|
|
|
|
struct atmel_mci_slot *slot = NULL;
|
|
|
|
struct mmc_host *prev_mmc = host->cur_slot->mmc;
|
|
|
|
|
|
|
|
WARN_ON(host->cmd || host->data);
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Update the MMC clock rate if necessary. This may be
|
|
|
|
* necessary if set_ios() is called when a different slot is
|
2011-03-30 19:57:33 -06:00
|
|
|
* busy transferring data.
|
atmel-mci: support multiple mmc slots
The Atmel MCI controller can drive multiple cards through separate sets
of pins, but only one at a time. This patch adds support for
multiplexing access to the controller so that multiple card slots can be
used as if they were hooked up to separate mmc controllers.
The atmel-mci driver registers each slot as a separate mmc_host. Both
access the same common controller state, but they also have some state
on their own for card detection/write protect handling, and separate
shadows of the MR and SDCR registers.
When one of the slots receives a request from the mmc core, the common
controller state is checked. If it's idle, the request is submitted
immediately. If not, the request is added to a queue. When a request is
done, the queue is checked and if there is a queued request, it is
submitted before the completion callback is called.
This patch also includes a few cleanups and fixes, including a locking
overhaul. I had to change the locking extensively in any case, so I
might as well try to get it right. The driver no longer takes any
irq-safe locks, which may or may not improve the overall system
performance.
This patch also adds a bit of documentation of the internal data
structures.
Signed-off-by: Haavard Skinnemoen <haavard.skinnemoen@atmel.com>
2008-09-17 12:53:55 -06:00
|
|
|
*/
|
2010-05-26 15:41:59 -06:00
|
|
|
if (host->need_clock_update) {
|
2011-08-11 09:25:42 -06:00
|
|
|
atmci_writel(host, ATMCI_MR, host->mode_reg);
|
2011-08-11 09:25:44 -06:00
|
|
|
if (host->caps.has_cfg_reg)
|
2011-08-11 09:25:42 -06:00
|
|
|
atmci_writel(host, ATMCI_CFG, host->cfg_reg);
|
2010-05-26 15:41:59 -06:00
|
|
|
}
|
atmel-mci: support multiple mmc slots
The Atmel MCI controller can drive multiple cards through separate sets
of pins, but only one at a time. This patch adds support for
multiplexing access to the controller so that multiple card slots can be
used as if they were hooked up to separate mmc controllers.
The atmel-mci driver registers each slot as a separate mmc_host. Both
access the same common controller state, but they also have some state
on their own for card detection/write protect handling, and separate
shadows of the MR and SDCR registers.
When one of the slots receives a request from the mmc core, the common
controller state is checked. If it's idle, the request is submitted
immediately. If not, the request is added to a queue. When a request is
done, the queue is checked and if there is a queued request, it is
submitted before the completion callback is called.
This patch also includes a few cleanups and fixes, including a locking
overhaul. I had to change the locking extensively in any case, so I
might as well try to get it right. The driver no longer takes any
irq-safe locks, which may or may not improve the overall system
performance.
This patch also adds a bit of documentation of the internal data
structures.
Signed-off-by: Haavard Skinnemoen <haavard.skinnemoen@atmel.com>
2008-09-17 12:53:55 -06:00
|
|
|
|
|
|
|
host->cur_slot->mrq = NULL;
|
|
|
|
host->mrq = NULL;
|
|
|
|
if (!list_empty(&host->queue)) {
|
|
|
|
slot = list_entry(host->queue.next,
|
|
|
|
struct atmel_mci_slot, queue_node);
|
|
|
|
list_del(&slot->queue_node);
|
|
|
|
dev_vdbg(&host->pdev->dev, "list not empty: %s is next\n",
|
|
|
|
mmc_hostname(slot->mmc));
|
|
|
|
host->state = STATE_SENDING_CMD;
|
|
|
|
atmci_start_request(host, slot);
|
|
|
|
} else {
|
|
|
|
dev_vdbg(&host->pdev->dev, "list empty\n");
|
|
|
|
host->state = STATE_IDLE;
|
|
|
|
}
|
|
|
|
|
2012-05-16 07:26:00 -06:00
|
|
|
del_timer(&host->timer);
|
|
|
|
|
atmel-mci: support multiple mmc slots
The Atmel MCI controller can drive multiple cards through separate sets
of pins, but only one at a time. This patch adds support for
multiplexing access to the controller so that multiple card slots can be
used as if they were hooked up to separate mmc controllers.
The atmel-mci driver registers each slot as a separate mmc_host. Both
access the same common controller state, but they also have some state
on their own for card detection/write protect handling, and separate
shadows of the MR and SDCR registers.
When one of the slots receives a request from the mmc core, the common
controller state is checked. If it's idle, the request is submitted
immediately. If not, the request is added to a queue. When a request is
done, the queue is checked and if there is a queued request, it is
submitted before the completion callback is called.
This patch also includes a few cleanups and fixes, including a locking
overhaul. I had to change the locking extensively in any case, so I
might as well try to get it right. The driver no longer takes any
irq-safe locks, which may or may not improve the overall system
performance.
This patch also adds a bit of documentation of the internal data
structures.
Signed-off-by: Haavard Skinnemoen <haavard.skinnemoen@atmel.com>
2008-09-17 12:53:55 -06:00
|
|
|
spin_unlock(&host->lock);
|
|
|
|
mmc_request_done(prev_mmc, mrq);
|
|
|
|
spin_lock(&host->lock);
|
|
|
|
}
|
|
|
|
|
atmel-mci: Driver for Atmel on-chip MMC controllers
This is a driver for the MMC controller on the AP7000 chips from
Atmel. It should in theory work on AT91 systems too with some
tweaking, but since the DMA interface is quite different, it's not
entirely clear if it's worth merging this with the at91_mci driver.
This driver has been around for a while in BSPs and kernel sources
provided by Atmel, but this particular version uses the generic DMA
Engine framework (with the slave extensions) instead of an
avr32-only DMA controller framework.
This driver can also use PIO transfers when no DMA channels are
available, and for transfers where using DMA may be difficult or
impractical for some reason (e.g. the DMA setup overhead is usually
not worth it for very short transfers, and badly aligned buffers or
lengths are difficult to handle.)
Currently, the driver only support PIO transfers. DMA support has been
split out to a separate patch to hopefully make it easier to review.
The driver has been tested using mmc-block and ext3fs on several SD,
SDHC and MMC+ cards. Reads and writes work fine, with read transfer
rates up to 3.5 MiB/s on fast cards with debugging disabled.
The driver has also been tested using the mmc_test module on the same
cards. All tests except 7, 9, 15 and 17 succeed. The first two are
unsupported by all the cards I have, so I don't know if the driver
handles this correctly. The last two fail because the hardware flags a
Data CRC Error instead of a Data Timeout error. I'm not sure how to deal
with that.
Documentation for this controller can be found in many data sheets from
Atmel, including the AT32AP7000 data sheet which can be found here:
http://www.atmel.com/dyn/products/datasheets.asp?family_id=682
Signed-off-by: Haavard Skinnemoen <haavard.skinnemoen@atmel.com>
Signed-off-by: Pierre Ossman <drzeus@drzeus.cx>
2008-06-30 10:35:03 -06:00
|
|
|
static void atmci_command_complete(struct atmel_mci *host,
|
2008-07-31 06:49:16 -06:00
|
|
|
struct mmc_command *cmd)
|
atmel-mci: Driver for Atmel on-chip MMC controllers
This is a driver for the MMC controller on the AP7000 chips from
Atmel. It should in theory work on AT91 systems too with some
tweaking, but since the DMA interface is quite different, it's not
entirely clear if it's worth merging this with the at91_mci driver.
This driver has been around for a while in BSPs and kernel sources
provided by Atmel, but this particular version uses the generic DMA
Engine framework (with the slave extensions) instead of an
avr32-only DMA controller framework.
This driver can also use PIO transfers when no DMA channels are
available, and for transfers where using DMA may be difficult or
impractical for some reason (e.g. the DMA setup overhead is usually
not worth it for very short transfers, and badly aligned buffers or
lengths are difficult to handle.)
Currently, the driver only support PIO transfers. DMA support has been
split out to a separate patch to hopefully make it easier to review.
The driver has been tested using mmc-block and ext3fs on several SD,
SDHC and MMC+ cards. Reads and writes work fine, with read transfer
rates up to 3.5 MiB/s on fast cards with debugging disabled.
The driver has also been tested using the mmc_test module on the same
cards. All tests except 7, 9, 15 and 17 succeed. The first two are
unsupported by all the cards I have, so I don't know if the driver
handles this correctly. The last two fail because the hardware flags a
Data CRC Error instead of a Data Timeout error. I'm not sure how to deal
with that.
Documentation for this controller can be found in many data sheets from
Atmel, including the AT32AP7000 data sheet which can be found here:
http://www.atmel.com/dyn/products/datasheets.asp?family_id=682
Signed-off-by: Haavard Skinnemoen <haavard.skinnemoen@atmel.com>
Signed-off-by: Pierre Ossman <drzeus@drzeus.cx>
2008-06-30 10:35:03 -06:00
|
|
|
{
|
2008-07-31 06:49:16 -06:00
|
|
|
u32 status = host->cmd_status;
|
|
|
|
|
atmel-mci: Driver for Atmel on-chip MMC controllers
This is a driver for the MMC controller on the AP7000 chips from
Atmel. It should in theory work on AT91 systems too with some
tweaking, but since the DMA interface is quite different, it's not
entirely clear if it's worth merging this with the at91_mci driver.
This driver has been around for a while in BSPs and kernel sources
provided by Atmel, but this particular version uses the generic DMA
Engine framework (with the slave extensions) instead of an
avr32-only DMA controller framework.
This driver can also use PIO transfers when no DMA channels are
available, and for transfers where using DMA may be difficult or
impractical for some reason (e.g. the DMA setup overhead is usually
not worth it for very short transfers, and badly aligned buffers or
lengths are difficult to handle.)
Currently, the driver only support PIO transfers. DMA support has been
split out to a separate patch to hopefully make it easier to review.
The driver has been tested using mmc-block and ext3fs on several SD,
SDHC and MMC+ cards. Reads and writes work fine, with read transfer
rates up to 3.5 MiB/s on fast cards with debugging disabled.
The driver has also been tested using the mmc_test module on the same
cards. All tests except 7, 9, 15 and 17 succeed. The first two are
unsupported by all the cards I have, so I don't know if the driver
handles this correctly. The last two fail because the hardware flags a
Data CRC Error instead of a Data Timeout error. I'm not sure how to deal
with that.
Documentation for this controller can be found in many data sheets from
Atmel, including the AT32AP7000 data sheet which can be found here:
http://www.atmel.com/dyn/products/datasheets.asp?family_id=682
Signed-off-by: Haavard Skinnemoen <haavard.skinnemoen@atmel.com>
Signed-off-by: Pierre Ossman <drzeus@drzeus.cx>
2008-06-30 10:35:03 -06:00
|
|
|
/* Read the response from the card (up to 16 bytes) */
|
2011-08-11 09:25:42 -06:00
|
|
|
cmd->resp[0] = atmci_readl(host, ATMCI_RSPR);
|
|
|
|
cmd->resp[1] = atmci_readl(host, ATMCI_RSPR);
|
|
|
|
cmd->resp[2] = atmci_readl(host, ATMCI_RSPR);
|
|
|
|
cmd->resp[3] = atmci_readl(host, ATMCI_RSPR);
|
atmel-mci: Driver for Atmel on-chip MMC controllers
This is a driver for the MMC controller on the AP7000 chips from
Atmel. It should in theory work on AT91 systems too with some
tweaking, but since the DMA interface is quite different, it's not
entirely clear if it's worth merging this with the at91_mci driver.
This driver has been around for a while in BSPs and kernel sources
provided by Atmel, but this particular version uses the generic DMA
Engine framework (with the slave extensions) instead of an
avr32-only DMA controller framework.
This driver can also use PIO transfers when no DMA channels are
available, and for transfers where using DMA may be difficult or
impractical for some reason (e.g. the DMA setup overhead is usually
not worth it for very short transfers, and badly aligned buffers or
lengths are difficult to handle.)
Currently, the driver only support PIO transfers. DMA support has been
split out to a separate patch to hopefully make it easier to review.
The driver has been tested using mmc-block and ext3fs on several SD,
SDHC and MMC+ cards. Reads and writes work fine, with read transfer
rates up to 3.5 MiB/s on fast cards with debugging disabled.
The driver has also been tested using the mmc_test module on the same
cards. All tests except 7, 9, 15 and 17 succeed. The first two are
unsupported by all the cards I have, so I don't know if the driver
handles this correctly. The last two fail because the hardware flags a
Data CRC Error instead of a Data Timeout error. I'm not sure how to deal
with that.
Documentation for this controller can be found in many data sheets from
Atmel, including the AT32AP7000 data sheet which can be found here:
http://www.atmel.com/dyn/products/datasheets.asp?family_id=682
Signed-off-by: Haavard Skinnemoen <haavard.skinnemoen@atmel.com>
Signed-off-by: Pierre Ossman <drzeus@drzeus.cx>
2008-06-30 10:35:03 -06:00
|
|
|
|
2011-08-11 09:25:41 -06:00
|
|
|
if (status & ATMCI_RTOE)
|
atmel-mci: Driver for Atmel on-chip MMC controllers
This is a driver for the MMC controller on the AP7000 chips from
Atmel. It should in theory work on AT91 systems too with some
tweaking, but since the DMA interface is quite different, it's not
entirely clear if it's worth merging this with the at91_mci driver.
This driver has been around for a while in BSPs and kernel sources
provided by Atmel, but this particular version uses the generic DMA
Engine framework (with the slave extensions) instead of an
avr32-only DMA controller framework.
This driver can also use PIO transfers when no DMA channels are
available, and for transfers where using DMA may be difficult or
impractical for some reason (e.g. the DMA setup overhead is usually
not worth it for very short transfers, and badly aligned buffers or
lengths are difficult to handle.)
Currently, the driver only support PIO transfers. DMA support has been
split out to a separate patch to hopefully make it easier to review.
The driver has been tested using mmc-block and ext3fs on several SD,
SDHC and MMC+ cards. Reads and writes work fine, with read transfer
rates up to 3.5 MiB/s on fast cards with debugging disabled.
The driver has also been tested using the mmc_test module on the same
cards. All tests except 7, 9, 15 and 17 succeed. The first two are
unsupported by all the cards I have, so I don't know if the driver
handles this correctly. The last two fail because the hardware flags a
Data CRC Error instead of a Data Timeout error. I'm not sure how to deal
with that.
Documentation for this controller can be found in many data sheets from
Atmel, including the AT32AP7000 data sheet which can be found here:
http://www.atmel.com/dyn/products/datasheets.asp?family_id=682
Signed-off-by: Haavard Skinnemoen <haavard.skinnemoen@atmel.com>
Signed-off-by: Pierre Ossman <drzeus@drzeus.cx>
2008-06-30 10:35:03 -06:00
|
|
|
cmd->error = -ETIMEDOUT;
|
2011-08-11 09:25:41 -06:00
|
|
|
else if ((cmd->flags & MMC_RSP_CRC) && (status & ATMCI_RCRCE))
|
atmel-mci: Driver for Atmel on-chip MMC controllers
This is a driver for the MMC controller on the AP7000 chips from
Atmel. It should in theory work on AT91 systems too with some
tweaking, but since the DMA interface is quite different, it's not
entirely clear if it's worth merging this with the at91_mci driver.
This driver has been around for a while in BSPs and kernel sources
provided by Atmel, but this particular version uses the generic DMA
Engine framework (with the slave extensions) instead of an
avr32-only DMA controller framework.
This driver can also use PIO transfers when no DMA channels are
available, and for transfers where using DMA may be difficult or
impractical for some reason (e.g. the DMA setup overhead is usually
not worth it for very short transfers, and badly aligned buffers or
lengths are difficult to handle.)
Currently, the driver only support PIO transfers. DMA support has been
split out to a separate patch to hopefully make it easier to review.
The driver has been tested using mmc-block and ext3fs on several SD,
SDHC and MMC+ cards. Reads and writes work fine, with read transfer
rates up to 3.5 MiB/s on fast cards with debugging disabled.
The driver has also been tested using the mmc_test module on the same
cards. All tests except 7, 9, 15 and 17 succeed. The first two are
unsupported by all the cards I have, so I don't know if the driver
handles this correctly. The last two fail because the hardware flags a
Data CRC Error instead of a Data Timeout error. I'm not sure how to deal
with that.
Documentation for this controller can be found in many data sheets from
Atmel, including the AT32AP7000 data sheet which can be found here:
http://www.atmel.com/dyn/products/datasheets.asp?family_id=682
Signed-off-by: Haavard Skinnemoen <haavard.skinnemoen@atmel.com>
Signed-off-by: Pierre Ossman <drzeus@drzeus.cx>
2008-06-30 10:35:03 -06:00
|
|
|
cmd->error = -EILSEQ;
|
2011-08-11 09:25:41 -06:00
|
|
|
else if (status & (ATMCI_RINDE | ATMCI_RDIRE | ATMCI_RENDE))
|
atmel-mci: Driver for Atmel on-chip MMC controllers
This is a driver for the MMC controller on the AP7000 chips from
Atmel. It should in theory work on AT91 systems too with some
tweaking, but since the DMA interface is quite different, it's not
entirely clear if it's worth merging this with the at91_mci driver.
This driver has been around for a while in BSPs and kernel sources
provided by Atmel, but this particular version uses the generic DMA
Engine framework (with the slave extensions) instead of an
avr32-only DMA controller framework.
This driver can also use PIO transfers when no DMA channels are
available, and for transfers where using DMA may be difficult or
impractical for some reason (e.g. the DMA setup overhead is usually
not worth it for very short transfers, and badly aligned buffers or
lengths are difficult to handle.)
Currently, the driver only support PIO transfers. DMA support has been
split out to a separate patch to hopefully make it easier to review.
The driver has been tested using mmc-block and ext3fs on several SD,
SDHC and MMC+ cards. Reads and writes work fine, with read transfer
rates up to 3.5 MiB/s on fast cards with debugging disabled.
The driver has also been tested using the mmc_test module on the same
cards. All tests except 7, 9, 15 and 17 succeed. The first two are
unsupported by all the cards I have, so I don't know if the driver
handles this correctly. The last two fail because the hardware flags a
Data CRC Error instead of a Data Timeout error. I'm not sure how to deal
with that.
Documentation for this controller can be found in many data sheets from
Atmel, including the AT32AP7000 data sheet which can be found here:
http://www.atmel.com/dyn/products/datasheets.asp?family_id=682
Signed-off-by: Haavard Skinnemoen <haavard.skinnemoen@atmel.com>
Signed-off-by: Pierre Ossman <drzeus@drzeus.cx>
2008-06-30 10:35:03 -06:00
|
|
|
cmd->error = -EIO;
|
2012-05-16 07:26:00 -06:00
|
|
|
else if (host->mrq->data && (host->mrq->data->blksz & 3)) {
|
|
|
|
if (host->caps.need_blksz_mul_4) {
|
|
|
|
cmd->error = -EINVAL;
|
|
|
|
host->need_reset = 1;
|
|
|
|
}
|
|
|
|
} else
|
atmel-mci: Driver for Atmel on-chip MMC controllers
This is a driver for the MMC controller on the AP7000 chips from
Atmel. It should in theory work on AT91 systems too with some
tweaking, but since the DMA interface is quite different, it's not
entirely clear if it's worth merging this with the at91_mci driver.
This driver has been around for a while in BSPs and kernel sources
provided by Atmel, but this particular version uses the generic DMA
Engine framework (with the slave extensions) instead of an
avr32-only DMA controller framework.
This driver can also use PIO transfers when no DMA channels are
available, and for transfers where using DMA may be difficult or
impractical for some reason (e.g. the DMA setup overhead is usually
not worth it for very short transfers, and badly aligned buffers or
lengths are difficult to handle.)
Currently, the driver only support PIO transfers. DMA support has been
split out to a separate patch to hopefully make it easier to review.
The driver has been tested using mmc-block and ext3fs on several SD,
SDHC and MMC+ cards. Reads and writes work fine, with read transfer
rates up to 3.5 MiB/s on fast cards with debugging disabled.
The driver has also been tested using the mmc_test module on the same
cards. All tests except 7, 9, 15 and 17 succeed. The first two are
unsupported by all the cards I have, so I don't know if the driver
handles this correctly. The last two fail because the hardware flags a
Data CRC Error instead of a Data Timeout error. I'm not sure how to deal
with that.
Documentation for this controller can be found in many data sheets from
Atmel, including the AT32AP7000 data sheet which can be found here:
http://www.atmel.com/dyn/products/datasheets.asp?family_id=682
Signed-off-by: Haavard Skinnemoen <haavard.skinnemoen@atmel.com>
Signed-off-by: Pierre Ossman <drzeus@drzeus.cx>
2008-06-30 10:35:03 -06:00
|
|
|
cmd->error = 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static void atmci_detect_change(unsigned long data)
|
|
|
|
{
|
atmel-mci: support multiple mmc slots
The Atmel MCI controller can drive multiple cards through separate sets
of pins, but only one at a time. This patch adds support for
multiplexing access to the controller so that multiple card slots can be
used as if they were hooked up to separate mmc controllers.
The atmel-mci driver registers each slot as a separate mmc_host. Both
access the same common controller state, but they also have some state
on their own for card detection/write protect handling, and separate
shadows of the MR and SDCR registers.
When one of the slots receives a request from the mmc core, the common
controller state is checked. If it's idle, the request is submitted
immediately. If not, the request is added to a queue. When a request is
done, the queue is checked and if there is a queued request, it is
submitted before the completion callback is called.
This patch also includes a few cleanups and fixes, including a locking
overhaul. I had to change the locking extensively in any case, so I
might as well try to get it right. The driver no longer takes any
irq-safe locks, which may or may not improve the overall system
performance.
This patch also adds a bit of documentation of the internal data
structures.
Signed-off-by: Haavard Skinnemoen <haavard.skinnemoen@atmel.com>
2008-09-17 12:53:55 -06:00
|
|
|
struct atmel_mci_slot *slot = (struct atmel_mci_slot *)data;
|
|
|
|
bool present;
|
|
|
|
bool present_old;
|
atmel-mci: Driver for Atmel on-chip MMC controllers
This is a driver for the MMC controller on the AP7000 chips from
Atmel. It should in theory work on AT91 systems too with some
tweaking, but since the DMA interface is quite different, it's not
entirely clear if it's worth merging this with the at91_mci driver.
This driver has been around for a while in BSPs and kernel sources
provided by Atmel, but this particular version uses the generic DMA
Engine framework (with the slave extensions) instead of an
avr32-only DMA controller framework.
This driver can also use PIO transfers when no DMA channels are
available, and for transfers where using DMA may be difficult or
impractical for some reason (e.g. the DMA setup overhead is usually
not worth it for very short transfers, and badly aligned buffers or
lengths are difficult to handle.)
Currently, the driver only support PIO transfers. DMA support has been
split out to a separate patch to hopefully make it easier to review.
The driver has been tested using mmc-block and ext3fs on several SD,
SDHC and MMC+ cards. Reads and writes work fine, with read transfer
rates up to 3.5 MiB/s on fast cards with debugging disabled.
The driver has also been tested using the mmc_test module on the same
cards. All tests except 7, 9, 15 and 17 succeed. The first two are
unsupported by all the cards I have, so I don't know if the driver
handles this correctly. The last two fail because the hardware flags a
Data CRC Error instead of a Data Timeout error. I'm not sure how to deal
with that.
Documentation for this controller can be found in many data sheets from
Atmel, including the AT32AP7000 data sheet which can be found here:
http://www.atmel.com/dyn/products/datasheets.asp?family_id=682
Signed-off-by: Haavard Skinnemoen <haavard.skinnemoen@atmel.com>
Signed-off-by: Pierre Ossman <drzeus@drzeus.cx>
2008-06-30 10:35:03 -06:00
|
|
|
|
|
|
|
/*
|
atmel-mci: support multiple mmc slots
The Atmel MCI controller can drive multiple cards through separate sets
of pins, but only one at a time. This patch adds support for
multiplexing access to the controller so that multiple card slots can be
used as if they were hooked up to separate mmc controllers.
The atmel-mci driver registers each slot as a separate mmc_host. Both
access the same common controller state, but they also have some state
on their own for card detection/write protect handling, and separate
shadows of the MR and SDCR registers.
When one of the slots receives a request from the mmc core, the common
controller state is checked. If it's idle, the request is submitted
immediately. If not, the request is added to a queue. When a request is
done, the queue is checked and if there is a queued request, it is
submitted before the completion callback is called.
This patch also includes a few cleanups and fixes, including a locking
overhaul. I had to change the locking extensively in any case, so I
might as well try to get it right. The driver no longer takes any
irq-safe locks, which may or may not improve the overall system
performance.
This patch also adds a bit of documentation of the internal data
structures.
Signed-off-by: Haavard Skinnemoen <haavard.skinnemoen@atmel.com>
2008-09-17 12:53:55 -06:00
|
|
|
* atmci_cleanup_slot() sets the ATMCI_SHUTDOWN flag before
|
|
|
|
* freeing the interrupt. We must not re-enable the interrupt
|
|
|
|
* if it has been freed, and if we're shutting down, it
|
|
|
|
* doesn't really matter whether the card is present or not.
|
atmel-mci: Driver for Atmel on-chip MMC controllers
This is a driver for the MMC controller on the AP7000 chips from
Atmel. It should in theory work on AT91 systems too with some
tweaking, but since the DMA interface is quite different, it's not
entirely clear if it's worth merging this with the at91_mci driver.
This driver has been around for a while in BSPs and kernel sources
provided by Atmel, but this particular version uses the generic DMA
Engine framework (with the slave extensions) instead of an
avr32-only DMA controller framework.
This driver can also use PIO transfers when no DMA channels are
available, and for transfers where using DMA may be difficult or
impractical for some reason (e.g. the DMA setup overhead is usually
not worth it for very short transfers, and badly aligned buffers or
lengths are difficult to handle.)
Currently, the driver only support PIO transfers. DMA support has been
split out to a separate patch to hopefully make it easier to review.
The driver has been tested using mmc-block and ext3fs on several SD,
SDHC and MMC+ cards. Reads and writes work fine, with read transfer
rates up to 3.5 MiB/s on fast cards with debugging disabled.
The driver has also been tested using the mmc_test module on the same
cards. All tests except 7, 9, 15 and 17 succeed. The first two are
unsupported by all the cards I have, so I don't know if the driver
handles this correctly. The last two fail because the hardware flags a
Data CRC Error instead of a Data Timeout error. I'm not sure how to deal
with that.
Documentation for this controller can be found in many data sheets from
Atmel, including the AT32AP7000 data sheet which can be found here:
http://www.atmel.com/dyn/products/datasheets.asp?family_id=682
Signed-off-by: Haavard Skinnemoen <haavard.skinnemoen@atmel.com>
Signed-off-by: Pierre Ossman <drzeus@drzeus.cx>
2008-06-30 10:35:03 -06:00
|
|
|
*/
|
|
|
|
smp_rmb();
|
atmel-mci: support multiple mmc slots
The Atmel MCI controller can drive multiple cards through separate sets
of pins, but only one at a time. This patch adds support for
multiplexing access to the controller so that multiple card slots can be
used as if they were hooked up to separate mmc controllers.
The atmel-mci driver registers each slot as a separate mmc_host. Both
access the same common controller state, but they also have some state
on their own for card detection/write protect handling, and separate
shadows of the MR and SDCR registers.
When one of the slots receives a request from the mmc core, the common
controller state is checked. If it's idle, the request is submitted
immediately. If not, the request is added to a queue. When a request is
done, the queue is checked and if there is a queued request, it is
submitted before the completion callback is called.
This patch also includes a few cleanups and fixes, including a locking
overhaul. I had to change the locking extensively in any case, so I
might as well try to get it right. The driver no longer takes any
irq-safe locks, which may or may not improve the overall system
performance.
This patch also adds a bit of documentation of the internal data
structures.
Signed-off-by: Haavard Skinnemoen <haavard.skinnemoen@atmel.com>
2008-09-17 12:53:55 -06:00
|
|
|
if (test_bit(ATMCI_SHUTDOWN, &slot->flags))
|
atmel-mci: Driver for Atmel on-chip MMC controllers
This is a driver for the MMC controller on the AP7000 chips from
Atmel. It should in theory work on AT91 systems too with some
tweaking, but since the DMA interface is quite different, it's not
entirely clear if it's worth merging this with the at91_mci driver.
This driver has been around for a while in BSPs and kernel sources
provided by Atmel, but this particular version uses the generic DMA
Engine framework (with the slave extensions) instead of an
avr32-only DMA controller framework.
This driver can also use PIO transfers when no DMA channels are
available, and for transfers where using DMA may be difficult or
impractical for some reason (e.g. the DMA setup overhead is usually
not worth it for very short transfers, and badly aligned buffers or
lengths are difficult to handle.)
Currently, the driver only support PIO transfers. DMA support has been
split out to a separate patch to hopefully make it easier to review.
The driver has been tested using mmc-block and ext3fs on several SD,
SDHC and MMC+ cards. Reads and writes work fine, with read transfer
rates up to 3.5 MiB/s on fast cards with debugging disabled.
The driver has also been tested using the mmc_test module on the same
cards. All tests except 7, 9, 15 and 17 succeed. The first two are
unsupported by all the cards I have, so I don't know if the driver
handles this correctly. The last two fail because the hardware flags a
Data CRC Error instead of a Data Timeout error. I'm not sure how to deal
with that.
Documentation for this controller can be found in many data sheets from
Atmel, including the AT32AP7000 data sheet which can be found here:
http://www.atmel.com/dyn/products/datasheets.asp?family_id=682
Signed-off-by: Haavard Skinnemoen <haavard.skinnemoen@atmel.com>
Signed-off-by: Pierre Ossman <drzeus@drzeus.cx>
2008-06-30 10:35:03 -06:00
|
|
|
return;
|
|
|
|
|
atmel-mci: support multiple mmc slots
The Atmel MCI controller can drive multiple cards through separate sets
of pins, but only one at a time. This patch adds support for
multiplexing access to the controller so that multiple card slots can be
used as if they were hooked up to separate mmc controllers.
The atmel-mci driver registers each slot as a separate mmc_host. Both
access the same common controller state, but they also have some state
on their own for card detection/write protect handling, and separate
shadows of the MR and SDCR registers.
When one of the slots receives a request from the mmc core, the common
controller state is checked. If it's idle, the request is submitted
immediately. If not, the request is added to a queue. When a request is
done, the queue is checked and if there is a queued request, it is
submitted before the completion callback is called.
This patch also includes a few cleanups and fixes, including a locking
overhaul. I had to change the locking extensively in any case, so I
might as well try to get it right. The driver no longer takes any
irq-safe locks, which may or may not improve the overall system
performance.
This patch also adds a bit of documentation of the internal data
structures.
Signed-off-by: Haavard Skinnemoen <haavard.skinnemoen@atmel.com>
2008-09-17 12:53:55 -06:00
|
|
|
enable_irq(gpio_to_irq(slot->detect_pin));
|
2009-03-31 03:16:48 -06:00
|
|
|
present = !(gpio_get_value(slot->detect_pin) ^
|
|
|
|
slot->detect_is_active_high);
|
atmel-mci: support multiple mmc slots
The Atmel MCI controller can drive multiple cards through separate sets
of pins, but only one at a time. This patch adds support for
multiplexing access to the controller so that multiple card slots can be
used as if they were hooked up to separate mmc controllers.
The atmel-mci driver registers each slot as a separate mmc_host. Both
access the same common controller state, but they also have some state
on their own for card detection/write protect handling, and separate
shadows of the MR and SDCR registers.
When one of the slots receives a request from the mmc core, the common
controller state is checked. If it's idle, the request is submitted
immediately. If not, the request is added to a queue. When a request is
done, the queue is checked and if there is a queued request, it is
submitted before the completion callback is called.
This patch also includes a few cleanups and fixes, including a locking
overhaul. I had to change the locking extensively in any case, so I
might as well try to get it right. The driver no longer takes any
irq-safe locks, which may or may not improve the overall system
performance.
This patch also adds a bit of documentation of the internal data
structures.
Signed-off-by: Haavard Skinnemoen <haavard.skinnemoen@atmel.com>
2008-09-17 12:53:55 -06:00
|
|
|
present_old = test_bit(ATMCI_CARD_PRESENT, &slot->flags);
|
atmel-mci: Driver for Atmel on-chip MMC controllers
This is a driver for the MMC controller on the AP7000 chips from
Atmel. It should in theory work on AT91 systems too with some
tweaking, but since the DMA interface is quite different, it's not
entirely clear if it's worth merging this with the at91_mci driver.
This driver has been around for a while in BSPs and kernel sources
provided by Atmel, but this particular version uses the generic DMA
Engine framework (with the slave extensions) instead of an
avr32-only DMA controller framework.
This driver can also use PIO transfers when no DMA channels are
available, and for transfers where using DMA may be difficult or
impractical for some reason (e.g. the DMA setup overhead is usually
not worth it for very short transfers, and badly aligned buffers or
lengths are difficult to handle.)
Currently, the driver only support PIO transfers. DMA support has been
split out to a separate patch to hopefully make it easier to review.
The driver has been tested using mmc-block and ext3fs on several SD,
SDHC and MMC+ cards. Reads and writes work fine, with read transfer
rates up to 3.5 MiB/s on fast cards with debugging disabled.
The driver has also been tested using the mmc_test module on the same
cards. All tests except 7, 9, 15 and 17 succeed. The first two are
unsupported by all the cards I have, so I don't know if the driver
handles this correctly. The last two fail because the hardware flags a
Data CRC Error instead of a Data Timeout error. I'm not sure how to deal
with that.
Documentation for this controller can be found in many data sheets from
Atmel, including the AT32AP7000 data sheet which can be found here:
http://www.atmel.com/dyn/products/datasheets.asp?family_id=682
Signed-off-by: Haavard Skinnemoen <haavard.skinnemoen@atmel.com>
Signed-off-by: Pierre Ossman <drzeus@drzeus.cx>
2008-06-30 10:35:03 -06:00
|
|
|
|
atmel-mci: support multiple mmc slots
The Atmel MCI controller can drive multiple cards through separate sets
of pins, but only one at a time. This patch adds support for
multiplexing access to the controller so that multiple card slots can be
used as if they were hooked up to separate mmc controllers.
The atmel-mci driver registers each slot as a separate mmc_host. Both
access the same common controller state, but they also have some state
on their own for card detection/write protect handling, and separate
shadows of the MR and SDCR registers.
When one of the slots receives a request from the mmc core, the common
controller state is checked. If it's idle, the request is submitted
immediately. If not, the request is added to a queue. When a request is
done, the queue is checked and if there is a queued request, it is
submitted before the completion callback is called.
This patch also includes a few cleanups and fixes, including a locking
overhaul. I had to change the locking extensively in any case, so I
might as well try to get it right. The driver no longer takes any
irq-safe locks, which may or may not improve the overall system
performance.
This patch also adds a bit of documentation of the internal data
structures.
Signed-off-by: Haavard Skinnemoen <haavard.skinnemoen@atmel.com>
2008-09-17 12:53:55 -06:00
|
|
|
dev_vdbg(&slot->mmc->class_dev, "detect change: %d (was %d)\n",
|
|
|
|
present, present_old);
|
atmel-mci: Driver for Atmel on-chip MMC controllers
This is a driver for the MMC controller on the AP7000 chips from
Atmel. It should in theory work on AT91 systems too with some
tweaking, but since the DMA interface is quite different, it's not
entirely clear if it's worth merging this with the at91_mci driver.
This driver has been around for a while in BSPs and kernel sources
provided by Atmel, but this particular version uses the generic DMA
Engine framework (with the slave extensions) instead of an
avr32-only DMA controller framework.
This driver can also use PIO transfers when no DMA channels are
available, and for transfers where using DMA may be difficult or
impractical for some reason (e.g. the DMA setup overhead is usually
not worth it for very short transfers, and badly aligned buffers or
lengths are difficult to handle.)
Currently, the driver only support PIO transfers. DMA support has been
split out to a separate patch to hopefully make it easier to review.
The driver has been tested using mmc-block and ext3fs on several SD,
SDHC and MMC+ cards. Reads and writes work fine, with read transfer
rates up to 3.5 MiB/s on fast cards with debugging disabled.
The driver has also been tested using the mmc_test module on the same
cards. All tests except 7, 9, 15 and 17 succeed. The first two are
unsupported by all the cards I have, so I don't know if the driver
handles this correctly. The last two fail because the hardware flags a
Data CRC Error instead of a Data Timeout error. I'm not sure how to deal
with that.
Documentation for this controller can be found in many data sheets from
Atmel, including the AT32AP7000 data sheet which can be found here:
http://www.atmel.com/dyn/products/datasheets.asp?family_id=682
Signed-off-by: Haavard Skinnemoen <haavard.skinnemoen@atmel.com>
Signed-off-by: Pierre Ossman <drzeus@drzeus.cx>
2008-06-30 10:35:03 -06:00
|
|
|
|
atmel-mci: support multiple mmc slots
The Atmel MCI controller can drive multiple cards through separate sets
of pins, but only one at a time. This patch adds support for
multiplexing access to the controller so that multiple card slots can be
used as if they were hooked up to separate mmc controllers.
The atmel-mci driver registers each slot as a separate mmc_host. Both
access the same common controller state, but they also have some state
on their own for card detection/write protect handling, and separate
shadows of the MR and SDCR registers.
When one of the slots receives a request from the mmc core, the common
controller state is checked. If it's idle, the request is submitted
immediately. If not, the request is added to a queue. When a request is
done, the queue is checked and if there is a queued request, it is
submitted before the completion callback is called.
This patch also includes a few cleanups and fixes, including a locking
overhaul. I had to change the locking extensively in any case, so I
might as well try to get it right. The driver no longer takes any
irq-safe locks, which may or may not improve the overall system
performance.
This patch also adds a bit of documentation of the internal data
structures.
Signed-off-by: Haavard Skinnemoen <haavard.skinnemoen@atmel.com>
2008-09-17 12:53:55 -06:00
|
|
|
if (present != present_old) {
|
|
|
|
struct atmel_mci *host = slot->host;
|
|
|
|
struct mmc_request *mrq;
|
|
|
|
|
|
|
|
dev_dbg(&slot->mmc->class_dev, "card %s\n",
|
atmel-mci: Driver for Atmel on-chip MMC controllers
This is a driver for the MMC controller on the AP7000 chips from
Atmel. It should in theory work on AT91 systems too with some
tweaking, but since the DMA interface is quite different, it's not
entirely clear if it's worth merging this with the at91_mci driver.
This driver has been around for a while in BSPs and kernel sources
provided by Atmel, but this particular version uses the generic DMA
Engine framework (with the slave extensions) instead of an
avr32-only DMA controller framework.
This driver can also use PIO transfers when no DMA channels are
available, and for transfers where using DMA may be difficult or
impractical for some reason (e.g. the DMA setup overhead is usually
not worth it for very short transfers, and badly aligned buffers or
lengths are difficult to handle.)
Currently, the driver only support PIO transfers. DMA support has been
split out to a separate patch to hopefully make it easier to review.
The driver has been tested using mmc-block and ext3fs on several SD,
SDHC and MMC+ cards. Reads and writes work fine, with read transfer
rates up to 3.5 MiB/s on fast cards with debugging disabled.
The driver has also been tested using the mmc_test module on the same
cards. All tests except 7, 9, 15 and 17 succeed. The first two are
unsupported by all the cards I have, so I don't know if the driver
handles this correctly. The last two fail because the hardware flags a
Data CRC Error instead of a Data Timeout error. I'm not sure how to deal
with that.
Documentation for this controller can be found in many data sheets from
Atmel, including the AT32AP7000 data sheet which can be found here:
http://www.atmel.com/dyn/products/datasheets.asp?family_id=682
Signed-off-by: Haavard Skinnemoen <haavard.skinnemoen@atmel.com>
Signed-off-by: Pierre Ossman <drzeus@drzeus.cx>
2008-06-30 10:35:03 -06:00
|
|
|
present ? "inserted" : "removed");
|
|
|
|
|
atmel-mci: support multiple mmc slots
The Atmel MCI controller can drive multiple cards through separate sets
of pins, but only one at a time. This patch adds support for
multiplexing access to the controller so that multiple card slots can be
used as if they were hooked up to separate mmc controllers.
The atmel-mci driver registers each slot as a separate mmc_host. Both
access the same common controller state, but they also have some state
on their own for card detection/write protect handling, and separate
shadows of the MR and SDCR registers.
When one of the slots receives a request from the mmc core, the common
controller state is checked. If it's idle, the request is submitted
immediately. If not, the request is added to a queue. When a request is
done, the queue is checked and if there is a queued request, it is
submitted before the completion callback is called.
This patch also includes a few cleanups and fixes, including a locking
overhaul. I had to change the locking extensively in any case, so I
might as well try to get it right. The driver no longer takes any
irq-safe locks, which may or may not improve the overall system
performance.
This patch also adds a bit of documentation of the internal data
structures.
Signed-off-by: Haavard Skinnemoen <haavard.skinnemoen@atmel.com>
2008-09-17 12:53:55 -06:00
|
|
|
spin_lock(&host->lock);
|
|
|
|
|
|
|
|
if (!present)
|
|
|
|
clear_bit(ATMCI_CARD_PRESENT, &slot->flags);
|
|
|
|
else
|
|
|
|
set_bit(ATMCI_CARD_PRESENT, &slot->flags);
|
atmel-mci: Driver for Atmel on-chip MMC controllers
This is a driver for the MMC controller on the AP7000 chips from
Atmel. It should in theory work on AT91 systems too with some
tweaking, but since the DMA interface is quite different, it's not
entirely clear if it's worth merging this with the at91_mci driver.
This driver has been around for a while in BSPs and kernel sources
provided by Atmel, but this particular version uses the generic DMA
Engine framework (with the slave extensions) instead of an
avr32-only DMA controller framework.
This driver can also use PIO transfers when no DMA channels are
available, and for transfers where using DMA may be difficult or
impractical for some reason (e.g. the DMA setup overhead is usually
not worth it for very short transfers, and badly aligned buffers or
lengths are difficult to handle.)
Currently, the driver only support PIO transfers. DMA support has been
split out to a separate patch to hopefully make it easier to review.
The driver has been tested using mmc-block and ext3fs on several SD,
SDHC and MMC+ cards. Reads and writes work fine, with read transfer
rates up to 3.5 MiB/s on fast cards with debugging disabled.
The driver has also been tested using the mmc_test module on the same
cards. All tests except 7, 9, 15 and 17 succeed. The first two are
unsupported by all the cards I have, so I don't know if the driver
handles this correctly. The last two fail because the hardware flags a
Data CRC Error instead of a Data Timeout error. I'm not sure how to deal
with that.
Documentation for this controller can be found in many data sheets from
Atmel, including the AT32AP7000 data sheet which can be found here:
http://www.atmel.com/dyn/products/datasheets.asp?family_id=682
Signed-off-by: Haavard Skinnemoen <haavard.skinnemoen@atmel.com>
Signed-off-by: Pierre Ossman <drzeus@drzeus.cx>
2008-06-30 10:35:03 -06:00
|
|
|
|
|
|
|
/* Clean up queue if present */
|
atmel-mci: support multiple mmc slots
The Atmel MCI controller can drive multiple cards through separate sets
of pins, but only one at a time. This patch adds support for
multiplexing access to the controller so that multiple card slots can be
used as if they were hooked up to separate mmc controllers.
The atmel-mci driver registers each slot as a separate mmc_host. Both
access the same common controller state, but they also have some state
on their own for card detection/write protect handling, and separate
shadows of the MR and SDCR registers.
When one of the slots receives a request from the mmc core, the common
controller state is checked. If it's idle, the request is submitted
immediately. If not, the request is added to a queue. When a request is
done, the queue is checked and if there is a queued request, it is
submitted before the completion callback is called.
This patch also includes a few cleanups and fixes, including a locking
overhaul. I had to change the locking extensively in any case, so I
might as well try to get it right. The driver no longer takes any
irq-safe locks, which may or may not improve the overall system
performance.
This patch also adds a bit of documentation of the internal data
structures.
Signed-off-by: Haavard Skinnemoen <haavard.skinnemoen@atmel.com>
2008-09-17 12:53:55 -06:00
|
|
|
mrq = slot->mrq;
|
atmel-mci: Driver for Atmel on-chip MMC controllers
This is a driver for the MMC controller on the AP7000 chips from
Atmel. It should in theory work on AT91 systems too with some
tweaking, but since the DMA interface is quite different, it's not
entirely clear if it's worth merging this with the at91_mci driver.
This driver has been around for a while in BSPs and kernel sources
provided by Atmel, but this particular version uses the generic DMA
Engine framework (with the slave extensions) instead of an
avr32-only DMA controller framework.
This driver can also use PIO transfers when no DMA channels are
available, and for transfers where using DMA may be difficult or
impractical for some reason (e.g. the DMA setup overhead is usually
not worth it for very short transfers, and badly aligned buffers or
lengths are difficult to handle.)
Currently, the driver only support PIO transfers. DMA support has been
split out to a separate patch to hopefully make it easier to review.
The driver has been tested using mmc-block and ext3fs on several SD,
SDHC and MMC+ cards. Reads and writes work fine, with read transfer
rates up to 3.5 MiB/s on fast cards with debugging disabled.
The driver has also been tested using the mmc_test module on the same
cards. All tests except 7, 9, 15 and 17 succeed. The first two are
unsupported by all the cards I have, so I don't know if the driver
handles this correctly. The last two fail because the hardware flags a
Data CRC Error instead of a Data Timeout error. I'm not sure how to deal
with that.
Documentation for this controller can be found in many data sheets from
Atmel, including the AT32AP7000 data sheet which can be found here:
http://www.atmel.com/dyn/products/datasheets.asp?family_id=682
Signed-off-by: Haavard Skinnemoen <haavard.skinnemoen@atmel.com>
Signed-off-by: Pierre Ossman <drzeus@drzeus.cx>
2008-06-30 10:35:03 -06:00
|
|
|
if (mrq) {
|
atmel-mci: support multiple mmc slots
The Atmel MCI controller can drive multiple cards through separate sets
of pins, but only one at a time. This patch adds support for
multiplexing access to the controller so that multiple card slots can be
used as if they were hooked up to separate mmc controllers.
The atmel-mci driver registers each slot as a separate mmc_host. Both
access the same common controller state, but they also have some state
on their own for card detection/write protect handling, and separate
shadows of the MR and SDCR registers.
When one of the slots receives a request from the mmc core, the common
controller state is checked. If it's idle, the request is submitted
immediately. If not, the request is added to a queue. When a request is
done, the queue is checked and if there is a queued request, it is
submitted before the completion callback is called.
This patch also includes a few cleanups and fixes, including a locking
overhaul. I had to change the locking extensively in any case, so I
might as well try to get it right. The driver no longer takes any
irq-safe locks, which may or may not improve the overall system
performance.
This patch also adds a bit of documentation of the internal data
structures.
Signed-off-by: Haavard Skinnemoen <haavard.skinnemoen@atmel.com>
2008-09-17 12:53:55 -06:00
|
|
|
if (mrq == host->mrq) {
|
|
|
|
/*
|
|
|
|
* Reset controller to terminate any ongoing
|
|
|
|
* commands or data transfers.
|
|
|
|
*/
|
2011-08-11 09:25:42 -06:00
|
|
|
atmci_writel(host, ATMCI_CR, ATMCI_CR_SWRST);
|
|
|
|
atmci_writel(host, ATMCI_CR, ATMCI_CR_MCIEN);
|
|
|
|
atmci_writel(host, ATMCI_MR, host->mode_reg);
|
2011-08-11 09:25:44 -06:00
|
|
|
if (host->caps.has_cfg_reg)
|
2011-08-11 09:25:42 -06:00
|
|
|
atmci_writel(host, ATMCI_CFG, host->cfg_reg);
|
atmel-mci: support multiple mmc slots
The Atmel MCI controller can drive multiple cards through separate sets
of pins, but only one at a time. This patch adds support for
multiplexing access to the controller so that multiple card slots can be
used as if they were hooked up to separate mmc controllers.
The atmel-mci driver registers each slot as a separate mmc_host. Both
access the same common controller state, but they also have some state
on their own for card detection/write protect handling, and separate
shadows of the MR and SDCR registers.
When one of the slots receives a request from the mmc core, the common
controller state is checked. If it's idle, the request is submitted
immediately. If not, the request is added to a queue. When a request is
done, the queue is checked and if there is a queued request, it is
submitted before the completion callback is called.
This patch also includes a few cleanups and fixes, including a locking
overhaul. I had to change the locking extensively in any case, so I
might as well try to get it right. The driver no longer takes any
irq-safe locks, which may or may not improve the overall system
performance.
This patch also adds a bit of documentation of the internal data
structures.
Signed-off-by: Haavard Skinnemoen <haavard.skinnemoen@atmel.com>
2008-09-17 12:53:55 -06:00
|
|
|
|
|
|
|
host->data = NULL;
|
|
|
|
host->cmd = NULL;
|
|
|
|
|
|
|
|
switch (host->state) {
|
|
|
|
case STATE_IDLE:
|
2008-07-31 06:49:16 -06:00
|
|
|
break;
|
atmel-mci: support multiple mmc slots
The Atmel MCI controller can drive multiple cards through separate sets
of pins, but only one at a time. This patch adds support for
multiplexing access to the controller so that multiple card slots can be
used as if they were hooked up to separate mmc controllers.
The atmel-mci driver registers each slot as a separate mmc_host. Both
access the same common controller state, but they also have some state
on their own for card detection/write protect handling, and separate
shadows of the MR and SDCR registers.
When one of the slots receives a request from the mmc core, the common
controller state is checked. If it's idle, the request is submitted
immediately. If not, the request is added to a queue. When a request is
done, the queue is checked and if there is a queued request, it is
submitted before the completion callback is called.
This patch also includes a few cleanups and fixes, including a locking
overhaul. I had to change the locking extensively in any case, so I
might as well try to get it right. The driver no longer takes any
irq-safe locks, which may or may not improve the overall system
performance.
This patch also adds a bit of documentation of the internal data
structures.
Signed-off-by: Haavard Skinnemoen <haavard.skinnemoen@atmel.com>
2008-09-17 12:53:55 -06:00
|
|
|
case STATE_SENDING_CMD:
|
|
|
|
mrq->cmd->error = -ENOMEDIUM;
|
2012-05-16 07:25:59 -06:00
|
|
|
if (mrq->data)
|
|
|
|
host->stop_transfer(host);
|
|
|
|
break;
|
|
|
|
case STATE_DATA_XFER:
|
2008-07-31 06:49:16 -06:00
|
|
|
mrq->data->error = -ENOMEDIUM;
|
2011-08-11 09:25:44 -06:00
|
|
|
host->stop_transfer(host);
|
2008-07-31 06:49:16 -06:00
|
|
|
break;
|
2012-05-16 07:25:59 -06:00
|
|
|
case STATE_WAITING_NOTBUSY:
|
|
|
|
mrq->data->error = -ENOMEDIUM;
|
|
|
|
break;
|
atmel-mci: support multiple mmc slots
The Atmel MCI controller can drive multiple cards through separate sets
of pins, but only one at a time. This patch adds support for
multiplexing access to the controller so that multiple card slots can be
used as if they were hooked up to separate mmc controllers.
The atmel-mci driver registers each slot as a separate mmc_host. Both
access the same common controller state, but they also have some state
on their own for card detection/write protect handling, and separate
shadows of the MR and SDCR registers.
When one of the slots receives a request from the mmc core, the common
controller state is checked. If it's idle, the request is submitted
immediately. If not, the request is added to a queue. When a request is
done, the queue is checked and if there is a queued request, it is
submitted before the completion callback is called.
This patch also includes a few cleanups and fixes, including a locking
overhaul. I had to change the locking extensively in any case, so I
might as well try to get it right. The driver no longer takes any
irq-safe locks, which may or may not improve the overall system
performance.
This patch also adds a bit of documentation of the internal data
structures.
Signed-off-by: Haavard Skinnemoen <haavard.skinnemoen@atmel.com>
2008-09-17 12:53:55 -06:00
|
|
|
case STATE_SENDING_STOP:
|
|
|
|
mrq->stop->error = -ENOMEDIUM;
|
|
|
|
break;
|
2012-05-16 07:25:59 -06:00
|
|
|
case STATE_END_REQUEST:
|
|
|
|
break;
|
atmel-mci: support multiple mmc slots
The Atmel MCI controller can drive multiple cards through separate sets
of pins, but only one at a time. This patch adds support for
multiplexing access to the controller so that multiple card slots can be
used as if they were hooked up to separate mmc controllers.
The atmel-mci driver registers each slot as a separate mmc_host. Both
access the same common controller state, but they also have some state
on their own for card detection/write protect handling, and separate
shadows of the MR and SDCR registers.
When one of the slots receives a request from the mmc core, the common
controller state is checked. If it's idle, the request is submitted
immediately. If not, the request is added to a queue. When a request is
done, the queue is checked and if there is a queued request, it is
submitted before the completion callback is called.
This patch also includes a few cleanups and fixes, including a locking
overhaul. I had to change the locking extensively in any case, so I
might as well try to get it right. The driver no longer takes any
irq-safe locks, which may or may not improve the overall system
performance.
This patch also adds a bit of documentation of the internal data
structures.
Signed-off-by: Haavard Skinnemoen <haavard.skinnemoen@atmel.com>
2008-09-17 12:53:55 -06:00
|
|
|
}
|
atmel-mci: Driver for Atmel on-chip MMC controllers
This is a driver for the MMC controller on the AP7000 chips from
Atmel. It should in theory work on AT91 systems too with some
tweaking, but since the DMA interface is quite different, it's not
entirely clear if it's worth merging this with the at91_mci driver.
This driver has been around for a while in BSPs and kernel sources
provided by Atmel, but this particular version uses the generic DMA
Engine framework (with the slave extensions) instead of an
avr32-only DMA controller framework.
This driver can also use PIO transfers when no DMA channels are
available, and for transfers where using DMA may be difficult or
impractical for some reason (e.g. the DMA setup overhead is usually
not worth it for very short transfers, and badly aligned buffers or
lengths are difficult to handle.)
Currently, the driver only support PIO transfers. DMA support has been
split out to a separate patch to hopefully make it easier to review.
The driver has been tested using mmc-block and ext3fs on several SD,
SDHC and MMC+ cards. Reads and writes work fine, with read transfer
rates up to 3.5 MiB/s on fast cards with debugging disabled.
The driver has also been tested using the mmc_test module on the same
cards. All tests except 7, 9, 15 and 17 succeed. The first two are
unsupported by all the cards I have, so I don't know if the driver
handles this correctly. The last two fail because the hardware flags a
Data CRC Error instead of a Data Timeout error. I'm not sure how to deal
with that.
Documentation for this controller can be found in many data sheets from
Atmel, including the AT32AP7000 data sheet which can be found here:
http://www.atmel.com/dyn/products/datasheets.asp?family_id=682
Signed-off-by: Haavard Skinnemoen <haavard.skinnemoen@atmel.com>
Signed-off-by: Pierre Ossman <drzeus@drzeus.cx>
2008-06-30 10:35:03 -06:00
|
|
|
|
atmel-mci: support multiple mmc slots
The Atmel MCI controller can drive multiple cards through separate sets
of pins, but only one at a time. This patch adds support for
multiplexing access to the controller so that multiple card slots can be
used as if they were hooked up to separate mmc controllers.
The atmel-mci driver registers each slot as a separate mmc_host. Both
access the same common controller state, but they also have some state
on their own for card detection/write protect handling, and separate
shadows of the MR and SDCR registers.
When one of the slots receives a request from the mmc core, the common
controller state is checked. If it's idle, the request is submitted
immediately. If not, the request is added to a queue. When a request is
done, the queue is checked and if there is a queued request, it is
submitted before the completion callback is called.
This patch also includes a few cleanups and fixes, including a locking
overhaul. I had to change the locking extensively in any case, so I
might as well try to get it right. The driver no longer takes any
irq-safe locks, which may or may not improve the overall system
performance.
This patch also adds a bit of documentation of the internal data
structures.
Signed-off-by: Haavard Skinnemoen <haavard.skinnemoen@atmel.com>
2008-09-17 12:53:55 -06:00
|
|
|
atmci_request_end(host, mrq);
|
|
|
|
} else {
|
|
|
|
list_del(&slot->queue_node);
|
|
|
|
mrq->cmd->error = -ENOMEDIUM;
|
|
|
|
if (mrq->data)
|
|
|
|
mrq->data->error = -ENOMEDIUM;
|
|
|
|
if (mrq->stop)
|
|
|
|
mrq->stop->error = -ENOMEDIUM;
|
|
|
|
|
|
|
|
spin_unlock(&host->lock);
|
|
|
|
mmc_request_done(slot->mmc, mrq);
|
|
|
|
spin_lock(&host->lock);
|
|
|
|
}
|
atmel-mci: Driver for Atmel on-chip MMC controllers
This is a driver for the MMC controller on the AP7000 chips from
Atmel. It should in theory work on AT91 systems too with some
tweaking, but since the DMA interface is quite different, it's not
entirely clear if it's worth merging this with the at91_mci driver.
This driver has been around for a while in BSPs and kernel sources
provided by Atmel, but this particular version uses the generic DMA
Engine framework (with the slave extensions) instead of an
avr32-only DMA controller framework.
This driver can also use PIO transfers when no DMA channels are
available, and for transfers where using DMA may be difficult or
impractical for some reason (e.g. the DMA setup overhead is usually
not worth it for very short transfers, and badly aligned buffers or
lengths are difficult to handle.)
Currently, the driver only support PIO transfers. DMA support has been
split out to a separate patch to hopefully make it easier to review.
The driver has been tested using mmc-block and ext3fs on several SD,
SDHC and MMC+ cards. Reads and writes work fine, with read transfer
rates up to 3.5 MiB/s on fast cards with debugging disabled.
The driver has also been tested using the mmc_test module on the same
cards. All tests except 7, 9, 15 and 17 succeed. The first two are
unsupported by all the cards I have, so I don't know if the driver
handles this correctly. The last two fail because the hardware flags a
Data CRC Error instead of a Data Timeout error. I'm not sure how to deal
with that.
Documentation for this controller can be found in many data sheets from
Atmel, including the AT32AP7000 data sheet which can be found here:
http://www.atmel.com/dyn/products/datasheets.asp?family_id=682
Signed-off-by: Haavard Skinnemoen <haavard.skinnemoen@atmel.com>
Signed-off-by: Pierre Ossman <drzeus@drzeus.cx>
2008-06-30 10:35:03 -06:00
|
|
|
}
|
atmel-mci: support multiple mmc slots
The Atmel MCI controller can drive multiple cards through separate sets
of pins, but only one at a time. This patch adds support for
multiplexing access to the controller so that multiple card slots can be
used as if they were hooked up to separate mmc controllers.
The atmel-mci driver registers each slot as a separate mmc_host. Both
access the same common controller state, but they also have some state
on their own for card detection/write protect handling, and separate
shadows of the MR and SDCR registers.
When one of the slots receives a request from the mmc core, the common
controller state is checked. If it's idle, the request is submitted
immediately. If not, the request is added to a queue. When a request is
done, the queue is checked and if there is a queued request, it is
submitted before the completion callback is called.
This patch also includes a few cleanups and fixes, including a locking
overhaul. I had to change the locking extensively in any case, so I
might as well try to get it right. The driver no longer takes any
irq-safe locks, which may or may not improve the overall system
performance.
This patch also adds a bit of documentation of the internal data
structures.
Signed-off-by: Haavard Skinnemoen <haavard.skinnemoen@atmel.com>
2008-09-17 12:53:55 -06:00
|
|
|
spin_unlock(&host->lock);
|
atmel-mci: Driver for Atmel on-chip MMC controllers
This is a driver for the MMC controller on the AP7000 chips from
Atmel. It should in theory work on AT91 systems too with some
tweaking, but since the DMA interface is quite different, it's not
entirely clear if it's worth merging this with the at91_mci driver.
This driver has been around for a while in BSPs and kernel sources
provided by Atmel, but this particular version uses the generic DMA
Engine framework (with the slave extensions) instead of an
avr32-only DMA controller framework.
This driver can also use PIO transfers when no DMA channels are
available, and for transfers where using DMA may be difficult or
impractical for some reason (e.g. the DMA setup overhead is usually
not worth it for very short transfers, and badly aligned buffers or
lengths are difficult to handle.)
Currently, the driver only support PIO transfers. DMA support has been
split out to a separate patch to hopefully make it easier to review.
The driver has been tested using mmc-block and ext3fs on several SD,
SDHC and MMC+ cards. Reads and writes work fine, with read transfer
rates up to 3.5 MiB/s on fast cards with debugging disabled.
The driver has also been tested using the mmc_test module on the same
cards. All tests except 7, 9, 15 and 17 succeed. The first two are
unsupported by all the cards I have, so I don't know if the driver
handles this correctly. The last two fail because the hardware flags a
Data CRC Error instead of a Data Timeout error. I'm not sure how to deal
with that.
Documentation for this controller can be found in many data sheets from
Atmel, including the AT32AP7000 data sheet which can be found here:
http://www.atmel.com/dyn/products/datasheets.asp?family_id=682
Signed-off-by: Haavard Skinnemoen <haavard.skinnemoen@atmel.com>
Signed-off-by: Pierre Ossman <drzeus@drzeus.cx>
2008-06-30 10:35:03 -06:00
|
|
|
|
atmel-mci: support multiple mmc slots
The Atmel MCI controller can drive multiple cards through separate sets
of pins, but only one at a time. This patch adds support for
multiplexing access to the controller so that multiple card slots can be
used as if they were hooked up to separate mmc controllers.
The atmel-mci driver registers each slot as a separate mmc_host. Both
access the same common controller state, but they also have some state
on their own for card detection/write protect handling, and separate
shadows of the MR and SDCR registers.
When one of the slots receives a request from the mmc core, the common
controller state is checked. If it's idle, the request is submitted
immediately. If not, the request is added to a queue. When a request is
done, the queue is checked and if there is a queued request, it is
submitted before the completion callback is called.
This patch also includes a few cleanups and fixes, including a locking
overhaul. I had to change the locking extensively in any case, so I
might as well try to get it right. The driver no longer takes any
irq-safe locks, which may or may not improve the overall system
performance.
This patch also adds a bit of documentation of the internal data
structures.
Signed-off-by: Haavard Skinnemoen <haavard.skinnemoen@atmel.com>
2008-09-17 12:53:55 -06:00
|
|
|
mmc_detect_change(slot->mmc, 0);
|
atmel-mci: Driver for Atmel on-chip MMC controllers
This is a driver for the MMC controller on the AP7000 chips from
Atmel. It should in theory work on AT91 systems too with some
tweaking, but since the DMA interface is quite different, it's not
entirely clear if it's worth merging this with the at91_mci driver.
This driver has been around for a while in BSPs and kernel sources
provided by Atmel, but this particular version uses the generic DMA
Engine framework (with the slave extensions) instead of an
avr32-only DMA controller framework.
This driver can also use PIO transfers when no DMA channels are
available, and for transfers where using DMA may be difficult or
impractical for some reason (e.g. the DMA setup overhead is usually
not worth it for very short transfers, and badly aligned buffers or
lengths are difficult to handle.)
Currently, the driver only support PIO transfers. DMA support has been
split out to a separate patch to hopefully make it easier to review.
The driver has been tested using mmc-block and ext3fs on several SD,
SDHC and MMC+ cards. Reads and writes work fine, with read transfer
rates up to 3.5 MiB/s on fast cards with debugging disabled.
The driver has also been tested using the mmc_test module on the same
cards. All tests except 7, 9, 15 and 17 succeed. The first two are
unsupported by all the cards I have, so I don't know if the driver
handles this correctly. The last two fail because the hardware flags a
Data CRC Error instead of a Data Timeout error. I'm not sure how to deal
with that.
Documentation for this controller can be found in many data sheets from
Atmel, including the AT32AP7000 data sheet which can be found here:
http://www.atmel.com/dyn/products/datasheets.asp?family_id=682
Signed-off-by: Haavard Skinnemoen <haavard.skinnemoen@atmel.com>
Signed-off-by: Pierre Ossman <drzeus@drzeus.cx>
2008-06-30 10:35:03 -06:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
static void atmci_tasklet_func(unsigned long priv)
|
|
|
|
{
|
atmel-mci: support multiple mmc slots
The Atmel MCI controller can drive multiple cards through separate sets
of pins, but only one at a time. This patch adds support for
multiplexing access to the controller so that multiple card slots can be
used as if they were hooked up to separate mmc controllers.
The atmel-mci driver registers each slot as a separate mmc_host. Both
access the same common controller state, but they also have some state
on their own for card detection/write protect handling, and separate
shadows of the MR and SDCR registers.
When one of the slots receives a request from the mmc core, the common
controller state is checked. If it's idle, the request is submitted
immediately. If not, the request is added to a queue. When a request is
done, the queue is checked and if there is a queued request, it is
submitted before the completion callback is called.
This patch also includes a few cleanups and fixes, including a locking
overhaul. I had to change the locking extensively in any case, so I
might as well try to get it right. The driver no longer takes any
irq-safe locks, which may or may not improve the overall system
performance.
This patch also adds a bit of documentation of the internal data
structures.
Signed-off-by: Haavard Skinnemoen <haavard.skinnemoen@atmel.com>
2008-09-17 12:53:55 -06:00
|
|
|
struct atmel_mci *host = (struct atmel_mci *)priv;
|
atmel-mci: Driver for Atmel on-chip MMC controllers
This is a driver for the MMC controller on the AP7000 chips from
Atmel. It should in theory work on AT91 systems too with some
tweaking, but since the DMA interface is quite different, it's not
entirely clear if it's worth merging this with the at91_mci driver.
This driver has been around for a while in BSPs and kernel sources
provided by Atmel, but this particular version uses the generic DMA
Engine framework (with the slave extensions) instead of an
avr32-only DMA controller framework.
This driver can also use PIO transfers when no DMA channels are
available, and for transfers where using DMA may be difficult or
impractical for some reason (e.g. the DMA setup overhead is usually
not worth it for very short transfers, and badly aligned buffers or
lengths are difficult to handle.)
Currently, the driver only support PIO transfers. DMA support has been
split out to a separate patch to hopefully make it easier to review.
The driver has been tested using mmc-block and ext3fs on several SD,
SDHC and MMC+ cards. Reads and writes work fine, with read transfer
rates up to 3.5 MiB/s on fast cards with debugging disabled.
The driver has also been tested using the mmc_test module on the same
cards. All tests except 7, 9, 15 and 17 succeed. The first two are
unsupported by all the cards I have, so I don't know if the driver
handles this correctly. The last two fail because the hardware flags a
Data CRC Error instead of a Data Timeout error. I'm not sure how to deal
with that.
Documentation for this controller can be found in many data sheets from
Atmel, including the AT32AP7000 data sheet which can be found here:
http://www.atmel.com/dyn/products/datasheets.asp?family_id=682
Signed-off-by: Haavard Skinnemoen <haavard.skinnemoen@atmel.com>
Signed-off-by: Pierre Ossman <drzeus@drzeus.cx>
2008-06-30 10:35:03 -06:00
|
|
|
struct mmc_request *mrq = host->mrq;
|
|
|
|
struct mmc_data *data = host->data;
|
2008-07-31 06:49:16 -06:00
|
|
|
enum atmel_mci_state state = host->state;
|
|
|
|
enum atmel_mci_state prev_state;
|
|
|
|
u32 status;
|
|
|
|
|
atmel-mci: support multiple mmc slots
The Atmel MCI controller can drive multiple cards through separate sets
of pins, but only one at a time. This patch adds support for
multiplexing access to the controller so that multiple card slots can be
used as if they were hooked up to separate mmc controllers.
The atmel-mci driver registers each slot as a separate mmc_host. Both
access the same common controller state, but they also have some state
on their own for card detection/write protect handling, and separate
shadows of the MR and SDCR registers.
When one of the slots receives a request from the mmc core, the common
controller state is checked. If it's idle, the request is submitted
immediately. If not, the request is added to a queue. When a request is
done, the queue is checked and if there is a queued request, it is
submitted before the completion callback is called.
This patch also includes a few cleanups and fixes, including a locking
overhaul. I had to change the locking extensively in any case, so I
might as well try to get it right. The driver no longer takes any
irq-safe locks, which may or may not improve the overall system
performance.
This patch also adds a bit of documentation of the internal data
structures.
Signed-off-by: Haavard Skinnemoen <haavard.skinnemoen@atmel.com>
2008-09-17 12:53:55 -06:00
|
|
|
spin_lock(&host->lock);
|
|
|
|
|
2008-07-31 06:49:16 -06:00
|
|
|
state = host->state;
|
atmel-mci: Driver for Atmel on-chip MMC controllers
This is a driver for the MMC controller on the AP7000 chips from
Atmel. It should in theory work on AT91 systems too with some
tweaking, but since the DMA interface is quite different, it's not
entirely clear if it's worth merging this with the at91_mci driver.
This driver has been around for a while in BSPs and kernel sources
provided by Atmel, but this particular version uses the generic DMA
Engine framework (with the slave extensions) instead of an
avr32-only DMA controller framework.
This driver can also use PIO transfers when no DMA channels are
available, and for transfers where using DMA may be difficult or
impractical for some reason (e.g. the DMA setup overhead is usually
not worth it for very short transfers, and badly aligned buffers or
lengths are difficult to handle.)
Currently, the driver only support PIO transfers. DMA support has been
split out to a separate patch to hopefully make it easier to review.
The driver has been tested using mmc-block and ext3fs on several SD,
SDHC and MMC+ cards. Reads and writes work fine, with read transfer
rates up to 3.5 MiB/s on fast cards with debugging disabled.
The driver has also been tested using the mmc_test module on the same
cards. All tests except 7, 9, 15 and 17 succeed. The first two are
unsupported by all the cards I have, so I don't know if the driver
handles this correctly. The last two fail because the hardware flags a
Data CRC Error instead of a Data Timeout error. I'm not sure how to deal
with that.
Documentation for this controller can be found in many data sheets from
Atmel, including the AT32AP7000 data sheet which can be found here:
http://www.atmel.com/dyn/products/datasheets.asp?family_id=682
Signed-off-by: Haavard Skinnemoen <haavard.skinnemoen@atmel.com>
Signed-off-by: Pierre Ossman <drzeus@drzeus.cx>
2008-06-30 10:35:03 -06:00
|
|
|
|
atmel-mci: support multiple mmc slots
The Atmel MCI controller can drive multiple cards through separate sets
of pins, but only one at a time. This patch adds support for
multiplexing access to the controller so that multiple card slots can be
used as if they were hooked up to separate mmc controllers.
The atmel-mci driver registers each slot as a separate mmc_host. Both
access the same common controller state, but they also have some state
on their own for card detection/write protect handling, and separate
shadows of the MR and SDCR registers.
When one of the slots receives a request from the mmc core, the common
controller state is checked. If it's idle, the request is submitted
immediately. If not, the request is added to a queue. When a request is
done, the queue is checked and if there is a queued request, it is
submitted before the completion callback is called.
This patch also includes a few cleanups and fixes, including a locking
overhaul. I had to change the locking extensively in any case, so I
might as well try to get it right. The driver no longer takes any
irq-safe locks, which may or may not improve the overall system
performance.
This patch also adds a bit of documentation of the internal data
structures.
Signed-off-by: Haavard Skinnemoen <haavard.skinnemoen@atmel.com>
2008-09-17 12:53:55 -06:00
|
|
|
dev_vdbg(&host->pdev->dev,
|
2008-07-31 06:49:16 -06:00
|
|
|
"tasklet: state %u pending/completed/mask %lx/%lx/%x\n",
|
|
|
|
state, host->pending_events, host->completed_events,
|
2011-08-11 09:25:42 -06:00
|
|
|
atmci_readl(host, ATMCI_IMR));
|
atmel-mci: Driver for Atmel on-chip MMC controllers
This is a driver for the MMC controller on the AP7000 chips from
Atmel. It should in theory work on AT91 systems too with some
tweaking, but since the DMA interface is quite different, it's not
entirely clear if it's worth merging this with the at91_mci driver.
This driver has been around for a while in BSPs and kernel sources
provided by Atmel, but this particular version uses the generic DMA
Engine framework (with the slave extensions) instead of an
avr32-only DMA controller framework.
This driver can also use PIO transfers when no DMA channels are
available, and for transfers where using DMA may be difficult or
impractical for some reason (e.g. the DMA setup overhead is usually
not worth it for very short transfers, and badly aligned buffers or
lengths are difficult to handle.)
Currently, the driver only support PIO transfers. DMA support has been
split out to a separate patch to hopefully make it easier to review.
The driver has been tested using mmc-block and ext3fs on several SD,
SDHC and MMC+ cards. Reads and writes work fine, with read transfer
rates up to 3.5 MiB/s on fast cards with debugging disabled.
The driver has also been tested using the mmc_test module on the same
cards. All tests except 7, 9, 15 and 17 succeed. The first two are
unsupported by all the cards I have, so I don't know if the driver
handles this correctly. The last two fail because the hardware flags a
Data CRC Error instead of a Data Timeout error. I'm not sure how to deal
with that.
Documentation for this controller can be found in many data sheets from
Atmel, including the AT32AP7000 data sheet which can be found here:
http://www.atmel.com/dyn/products/datasheets.asp?family_id=682
Signed-off-by: Haavard Skinnemoen <haavard.skinnemoen@atmel.com>
Signed-off-by: Pierre Ossman <drzeus@drzeus.cx>
2008-06-30 10:35:03 -06:00
|
|
|
|
2008-07-31 06:49:16 -06:00
|
|
|
do {
|
|
|
|
prev_state = state;
|
2012-05-16 07:26:01 -06:00
|
|
|
dev_dbg(&host->pdev->dev, "FSM: state=%d\n", state);
|
atmel-mci: Driver for Atmel on-chip MMC controllers
This is a driver for the MMC controller on the AP7000 chips from
Atmel. It should in theory work on AT91 systems too with some
tweaking, but since the DMA interface is quite different, it's not
entirely clear if it's worth merging this with the at91_mci driver.
This driver has been around for a while in BSPs and kernel sources
provided by Atmel, but this particular version uses the generic DMA
Engine framework (with the slave extensions) instead of an
avr32-only DMA controller framework.
This driver can also use PIO transfers when no DMA channels are
available, and for transfers where using DMA may be difficult or
impractical for some reason (e.g. the DMA setup overhead is usually
not worth it for very short transfers, and badly aligned buffers or
lengths are difficult to handle.)
Currently, the driver only support PIO transfers. DMA support has been
split out to a separate patch to hopefully make it easier to review.
The driver has been tested using mmc-block and ext3fs on several SD,
SDHC and MMC+ cards. Reads and writes work fine, with read transfer
rates up to 3.5 MiB/s on fast cards with debugging disabled.
The driver has also been tested using the mmc_test module on the same
cards. All tests except 7, 9, 15 and 17 succeed. The first two are
unsupported by all the cards I have, so I don't know if the driver
handles this correctly. The last two fail because the hardware flags a
Data CRC Error instead of a Data Timeout error. I'm not sure how to deal
with that.
Documentation for this controller can be found in many data sheets from
Atmel, including the AT32AP7000 data sheet which can be found here:
http://www.atmel.com/dyn/products/datasheets.asp?family_id=682
Signed-off-by: Haavard Skinnemoen <haavard.skinnemoen@atmel.com>
Signed-off-by: Pierre Ossman <drzeus@drzeus.cx>
2008-06-30 10:35:03 -06:00
|
|
|
|
2008-07-31 06:49:16 -06:00
|
|
|
switch (state) {
|
atmel-mci: support multiple mmc slots
The Atmel MCI controller can drive multiple cards through separate sets
of pins, but only one at a time. This patch adds support for
multiplexing access to the controller so that multiple card slots can be
used as if they were hooked up to separate mmc controllers.
The atmel-mci driver registers each slot as a separate mmc_host. Both
access the same common controller state, but they also have some state
on their own for card detection/write protect handling, and separate
shadows of the MR and SDCR registers.
When one of the slots receives a request from the mmc core, the common
controller state is checked. If it's idle, the request is submitted
immediately. If not, the request is added to a queue. When a request is
done, the queue is checked and if there is a queued request, it is
submitted before the completion callback is called.
This patch also includes a few cleanups and fixes, including a locking
overhaul. I had to change the locking extensively in any case, so I
might as well try to get it right. The driver no longer takes any
irq-safe locks, which may or may not improve the overall system
performance.
This patch also adds a bit of documentation of the internal data
structures.
Signed-off-by: Haavard Skinnemoen <haavard.skinnemoen@atmel.com>
2008-09-17 12:53:55 -06:00
|
|
|
case STATE_IDLE:
|
|
|
|
break;
|
|
|
|
|
2008-07-31 06:49:16 -06:00
|
|
|
case STATE_SENDING_CMD:
|
2012-05-16 07:25:59 -06:00
|
|
|
/*
|
|
|
|
* Command has been sent, we are waiting for command
|
|
|
|
* ready. Then we have three next states possible:
|
|
|
|
* END_REQUEST by default, WAITING_NOTBUSY if it's a
|
|
|
|
* command needing it or DATA_XFER if there is data.
|
|
|
|
*/
|
2012-05-16 07:26:01 -06:00
|
|
|
dev_dbg(&host->pdev->dev, "FSM: cmd ready?\n");
|
2008-07-31 06:49:16 -06:00
|
|
|
if (!atmci_test_and_clear_pending(host,
|
2012-05-16 07:25:59 -06:00
|
|
|
EVENT_CMD_RDY))
|
2008-07-31 06:49:16 -06:00
|
|
|
break;
|
atmel-mci: Driver for Atmel on-chip MMC controllers
This is a driver for the MMC controller on the AP7000 chips from
Atmel. It should in theory work on AT91 systems too with some
tweaking, but since the DMA interface is quite different, it's not
entirely clear if it's worth merging this with the at91_mci driver.
This driver has been around for a while in BSPs and kernel sources
provided by Atmel, but this particular version uses the generic DMA
Engine framework (with the slave extensions) instead of an
avr32-only DMA controller framework.
This driver can also use PIO transfers when no DMA channels are
available, and for transfers where using DMA may be difficult or
impractical for some reason (e.g. the DMA setup overhead is usually
not worth it for very short transfers, and badly aligned buffers or
lengths are difficult to handle.)
Currently, the driver only support PIO transfers. DMA support has been
split out to a separate patch to hopefully make it easier to review.
The driver has been tested using mmc-block and ext3fs on several SD,
SDHC and MMC+ cards. Reads and writes work fine, with read transfer
rates up to 3.5 MiB/s on fast cards with debugging disabled.
The driver has also been tested using the mmc_test module on the same
cards. All tests except 7, 9, 15 and 17 succeed. The first two are
unsupported by all the cards I have, so I don't know if the driver
handles this correctly. The last two fail because the hardware flags a
Data CRC Error instead of a Data Timeout error. I'm not sure how to deal
with that.
Documentation for this controller can be found in many data sheets from
Atmel, including the AT32AP7000 data sheet which can be found here:
http://www.atmel.com/dyn/products/datasheets.asp?family_id=682
Signed-off-by: Haavard Skinnemoen <haavard.skinnemoen@atmel.com>
Signed-off-by: Pierre Ossman <drzeus@drzeus.cx>
2008-06-30 10:35:03 -06:00
|
|
|
|
2012-05-16 07:26:01 -06:00
|
|
|
dev_dbg(&host->pdev->dev, "set completed cmd ready\n");
|
2008-07-31 06:49:16 -06:00
|
|
|
host->cmd = NULL;
|
2012-05-16 07:25:59 -06:00
|
|
|
atmci_set_completed(host, EVENT_CMD_RDY);
|
2008-07-31 06:49:16 -06:00
|
|
|
atmci_command_complete(host, mrq->cmd);
|
2012-05-16 07:25:59 -06:00
|
|
|
if (mrq->data) {
|
2012-05-16 07:26:01 -06:00
|
|
|
dev_dbg(&host->pdev->dev,
|
|
|
|
"command with data transfer");
|
2012-05-16 07:25:59 -06:00
|
|
|
/*
|
|
|
|
* If there is a command error don't start
|
|
|
|
* data transfer.
|
|
|
|
*/
|
|
|
|
if (mrq->cmd->error) {
|
|
|
|
host->stop_transfer(host);
|
|
|
|
host->data = NULL;
|
|
|
|
atmci_writel(host, ATMCI_IDR,
|
|
|
|
ATMCI_TXRDY | ATMCI_RXRDY
|
|
|
|
| ATMCI_DATA_ERROR_FLAGS);
|
|
|
|
state = STATE_END_REQUEST;
|
|
|
|
} else
|
|
|
|
state = STATE_DATA_XFER;
|
|
|
|
} else if ((!mrq->data) && (mrq->cmd->flags & MMC_RSP_BUSY)) {
|
2012-05-16 07:26:01 -06:00
|
|
|
dev_dbg(&host->pdev->dev,
|
|
|
|
"command response need waiting notbusy");
|
2012-05-16 07:25:59 -06:00
|
|
|
atmci_writel(host, ATMCI_IER, ATMCI_NOTBUSY);
|
|
|
|
state = STATE_WAITING_NOTBUSY;
|
|
|
|
} else
|
|
|
|
state = STATE_END_REQUEST;
|
atmel-mci: Driver for Atmel on-chip MMC controllers
This is a driver for the MMC controller on the AP7000 chips from
Atmel. It should in theory work on AT91 systems too with some
tweaking, but since the DMA interface is quite different, it's not
entirely clear if it's worth merging this with the at91_mci driver.
This driver has been around for a while in BSPs and kernel sources
provided by Atmel, but this particular version uses the generic DMA
Engine framework (with the slave extensions) instead of an
avr32-only DMA controller framework.
This driver can also use PIO transfers when no DMA channels are
available, and for transfers where using DMA may be difficult or
impractical for some reason (e.g. the DMA setup overhead is usually
not worth it for very short transfers, and badly aligned buffers or
lengths are difficult to handle.)
Currently, the driver only support PIO transfers. DMA support has been
split out to a separate patch to hopefully make it easier to review.
The driver has been tested using mmc-block and ext3fs on several SD,
SDHC and MMC+ cards. Reads and writes work fine, with read transfer
rates up to 3.5 MiB/s on fast cards with debugging disabled.
The driver has also been tested using the mmc_test module on the same
cards. All tests except 7, 9, 15 and 17 succeed. The first two are
unsupported by all the cards I have, so I don't know if the driver
handles this correctly. The last two fail because the hardware flags a
Data CRC Error instead of a Data Timeout error. I'm not sure how to deal
with that.
Documentation for this controller can be found in many data sheets from
Atmel, including the AT32AP7000 data sheet which can be found here:
http://www.atmel.com/dyn/products/datasheets.asp?family_id=682
Signed-off-by: Haavard Skinnemoen <haavard.skinnemoen@atmel.com>
Signed-off-by: Pierre Ossman <drzeus@drzeus.cx>
2008-06-30 10:35:03 -06:00
|
|
|
|
2012-05-16 07:25:59 -06:00
|
|
|
break;
|
atmel-mci: Driver for Atmel on-chip MMC controllers
This is a driver for the MMC controller on the AP7000 chips from
Atmel. It should in theory work on AT91 systems too with some
tweaking, but since the DMA interface is quite different, it's not
entirely clear if it's worth merging this with the at91_mci driver.
This driver has been around for a while in BSPs and kernel sources
provided by Atmel, but this particular version uses the generic DMA
Engine framework (with the slave extensions) instead of an
avr32-only DMA controller framework.
This driver can also use PIO transfers when no DMA channels are
available, and for transfers where using DMA may be difficult or
impractical for some reason (e.g. the DMA setup overhead is usually
not worth it for very short transfers, and badly aligned buffers or
lengths are difficult to handle.)
Currently, the driver only support PIO transfers. DMA support has been
split out to a separate patch to hopefully make it easier to review.
The driver has been tested using mmc-block and ext3fs on several SD,
SDHC and MMC+ cards. Reads and writes work fine, with read transfer
rates up to 3.5 MiB/s on fast cards with debugging disabled.
The driver has also been tested using the mmc_test module on the same
cards. All tests except 7, 9, 15 and 17 succeed. The first two are
unsupported by all the cards I have, so I don't know if the driver
handles this correctly. The last two fail because the hardware flags a
Data CRC Error instead of a Data Timeout error. I'm not sure how to deal
with that.
Documentation for this controller can be found in many data sheets from
Atmel, including the AT32AP7000 data sheet which can be found here:
http://www.atmel.com/dyn/products/datasheets.asp?family_id=682
Signed-off-by: Haavard Skinnemoen <haavard.skinnemoen@atmel.com>
Signed-off-by: Pierre Ossman <drzeus@drzeus.cx>
2008-06-30 10:35:03 -06:00
|
|
|
|
2012-05-16 07:25:59 -06:00
|
|
|
case STATE_DATA_XFER:
|
2008-07-31 06:49:16 -06:00
|
|
|
if (atmci_test_and_clear_pending(host,
|
|
|
|
EVENT_DATA_ERROR)) {
|
2012-05-16 07:26:01 -06:00
|
|
|
dev_dbg(&host->pdev->dev, "set completed data error\n");
|
2012-05-16 07:25:59 -06:00
|
|
|
atmci_set_completed(host, EVENT_DATA_ERROR);
|
|
|
|
state = STATE_END_REQUEST;
|
2008-07-31 06:49:16 -06:00
|
|
|
break;
|
|
|
|
}
|
atmel-mci: Driver for Atmel on-chip MMC controllers
This is a driver for the MMC controller on the AP7000 chips from
Atmel. It should in theory work on AT91 systems too with some
tweaking, but since the DMA interface is quite different, it's not
entirely clear if it's worth merging this with the at91_mci driver.
This driver has been around for a while in BSPs and kernel sources
provided by Atmel, but this particular version uses the generic DMA
Engine framework (with the slave extensions) instead of an
avr32-only DMA controller framework.
This driver can also use PIO transfers when no DMA channels are
available, and for transfers where using DMA may be difficult or
impractical for some reason (e.g. the DMA setup overhead is usually
not worth it for very short transfers, and badly aligned buffers or
lengths are difficult to handle.)
Currently, the driver only support PIO transfers. DMA support has been
split out to a separate patch to hopefully make it easier to review.
The driver has been tested using mmc-block and ext3fs on several SD,
SDHC and MMC+ cards. Reads and writes work fine, with read transfer
rates up to 3.5 MiB/s on fast cards with debugging disabled.
The driver has also been tested using the mmc_test module on the same
cards. All tests except 7, 9, 15 and 17 succeed. The first two are
unsupported by all the cards I have, so I don't know if the driver
handles this correctly. The last two fail because the hardware flags a
Data CRC Error instead of a Data Timeout error. I'm not sure how to deal
with that.
Documentation for this controller can be found in many data sheets from
Atmel, including the AT32AP7000 data sheet which can be found here:
http://www.atmel.com/dyn/products/datasheets.asp?family_id=682
Signed-off-by: Haavard Skinnemoen <haavard.skinnemoen@atmel.com>
Signed-off-by: Pierre Ossman <drzeus@drzeus.cx>
2008-06-30 10:35:03 -06:00
|
|
|
|
2012-05-16 07:25:59 -06:00
|
|
|
/*
|
|
|
|
* A data transfer is in progress. The event expected
|
|
|
|
* to move to the next state depends of data transfer
|
|
|
|
* type (PDC or DMA). Once transfer done we can move
|
|
|
|
* to the next step which is WAITING_NOTBUSY in write
|
|
|
|
* case and directly SENDING_STOP in read case.
|
|
|
|
*/
|
2012-05-16 07:26:01 -06:00
|
|
|
dev_dbg(&host->pdev->dev, "FSM: xfer complete?\n");
|
2008-07-31 06:49:16 -06:00
|
|
|
if (!atmci_test_and_clear_pending(host,
|
|
|
|
EVENT_XFER_COMPLETE))
|
|
|
|
break;
|
atmel-mci: Driver for Atmel on-chip MMC controllers
This is a driver for the MMC controller on the AP7000 chips from
Atmel. It should in theory work on AT91 systems too with some
tweaking, but since the DMA interface is quite different, it's not
entirely clear if it's worth merging this with the at91_mci driver.
This driver has been around for a while in BSPs and kernel sources
provided by Atmel, but this particular version uses the generic DMA
Engine framework (with the slave extensions) instead of an
avr32-only DMA controller framework.
This driver can also use PIO transfers when no DMA channels are
available, and for transfers where using DMA may be difficult or
impractical for some reason (e.g. the DMA setup overhead is usually
not worth it for very short transfers, and badly aligned buffers or
lengths are difficult to handle.)
Currently, the driver only support PIO transfers. DMA support has been
split out to a separate patch to hopefully make it easier to review.
The driver has been tested using mmc-block and ext3fs on several SD,
SDHC and MMC+ cards. Reads and writes work fine, with read transfer
rates up to 3.5 MiB/s on fast cards with debugging disabled.
The driver has also been tested using the mmc_test module on the same
cards. All tests except 7, 9, 15 and 17 succeed. The first two are
unsupported by all the cards I have, so I don't know if the driver
handles this correctly. The last two fail because the hardware flags a
Data CRC Error instead of a Data Timeout error. I'm not sure how to deal
with that.
Documentation for this controller can be found in many data sheets from
Atmel, including the AT32AP7000 data sheet which can be found here:
http://www.atmel.com/dyn/products/datasheets.asp?family_id=682
Signed-off-by: Haavard Skinnemoen <haavard.skinnemoen@atmel.com>
Signed-off-by: Pierre Ossman <drzeus@drzeus.cx>
2008-06-30 10:35:03 -06:00
|
|
|
|
2012-05-16 07:26:01 -06:00
|
|
|
dev_dbg(&host->pdev->dev,
|
|
|
|
"(%s) set completed xfer complete\n",
|
|
|
|
__func__);
|
2008-07-31 06:49:16 -06:00
|
|
|
atmci_set_completed(host, EVENT_XFER_COMPLETE);
|
atmel-mci: Driver for Atmel on-chip MMC controllers
This is a driver for the MMC controller on the AP7000 chips from
Atmel. It should in theory work on AT91 systems too with some
tweaking, but since the DMA interface is quite different, it's not
entirely clear if it's worth merging this with the at91_mci driver.
This driver has been around for a while in BSPs and kernel sources
provided by Atmel, but this particular version uses the generic DMA
Engine framework (with the slave extensions) instead of an
avr32-only DMA controller framework.
This driver can also use PIO transfers when no DMA channels are
available, and for transfers where using DMA may be difficult or
impractical for some reason (e.g. the DMA setup overhead is usually
not worth it for very short transfers, and badly aligned buffers or
lengths are difficult to handle.)
Currently, the driver only support PIO transfers. DMA support has been
split out to a separate patch to hopefully make it easier to review.
The driver has been tested using mmc-block and ext3fs on several SD,
SDHC and MMC+ cards. Reads and writes work fine, with read transfer
rates up to 3.5 MiB/s on fast cards with debugging disabled.
The driver has also been tested using the mmc_test module on the same
cards. All tests except 7, 9, 15 and 17 succeed. The first two are
unsupported by all the cards I have, so I don't know if the driver
handles this correctly. The last two fail because the hardware flags a
Data CRC Error instead of a Data Timeout error. I'm not sure how to deal
with that.
Documentation for this controller can be found in many data sheets from
Atmel, including the AT32AP7000 data sheet which can be found here:
http://www.atmel.com/dyn/products/datasheets.asp?family_id=682
Signed-off-by: Haavard Skinnemoen <haavard.skinnemoen@atmel.com>
Signed-off-by: Pierre Ossman <drzeus@drzeus.cx>
2008-06-30 10:35:03 -06:00
|
|
|
|
2012-07-24 03:42:04 -06:00
|
|
|
if (host->caps.need_notbusy_for_read_ops ||
|
|
|
|
(host->data->flags & MMC_DATA_WRITE)) {
|
2012-05-16 07:25:59 -06:00
|
|
|
atmci_writel(host, ATMCI_IER, ATMCI_NOTBUSY);
|
|
|
|
state = STATE_WAITING_NOTBUSY;
|
|
|
|
} else if (host->mrq->stop) {
|
|
|
|
atmci_writel(host, ATMCI_IER, ATMCI_CMDRDY);
|
|
|
|
atmci_send_stop_cmd(host, data);
|
|
|
|
state = STATE_SENDING_STOP;
|
2008-07-31 06:49:16 -06:00
|
|
|
} else {
|
2012-05-16 07:25:59 -06:00
|
|
|
host->data = NULL;
|
2008-07-31 06:49:16 -06:00
|
|
|
data->bytes_xfered = data->blocks * data->blksz;
|
|
|
|
data->error = 0;
|
2012-05-16 07:25:59 -06:00
|
|
|
state = STATE_END_REQUEST;
|
2008-07-31 06:49:16 -06:00
|
|
|
}
|
2012-05-16 07:25:59 -06:00
|
|
|
break;
|
2008-07-31 06:49:16 -06:00
|
|
|
|
2012-05-16 07:25:59 -06:00
|
|
|
case STATE_WAITING_NOTBUSY:
|
|
|
|
/*
|
|
|
|
* We can be in the state for two reasons: a command
|
|
|
|
* requiring waiting not busy signal (stop command
|
|
|
|
* included) or a write operation. In the latest case,
|
|
|
|
* we need to send a stop command.
|
|
|
|
*/
|
2012-05-16 07:26:01 -06:00
|
|
|
dev_dbg(&host->pdev->dev, "FSM: not busy?\n");
|
2012-05-16 07:25:59 -06:00
|
|
|
if (!atmci_test_and_clear_pending(host,
|
|
|
|
EVENT_NOTBUSY))
|
|
|
|
break;
|
atmel-mci: Driver for Atmel on-chip MMC controllers
This is a driver for the MMC controller on the AP7000 chips from
Atmel. It should in theory work on AT91 systems too with some
tweaking, but since the DMA interface is quite different, it's not
entirely clear if it's worth merging this with the at91_mci driver.
This driver has been around for a while in BSPs and kernel sources
provided by Atmel, but this particular version uses the generic DMA
Engine framework (with the slave extensions) instead of an
avr32-only DMA controller framework.
This driver can also use PIO transfers when no DMA channels are
available, and for transfers where using DMA may be difficult or
impractical for some reason (e.g. the DMA setup overhead is usually
not worth it for very short transfers, and badly aligned buffers or
lengths are difficult to handle.)
Currently, the driver only support PIO transfers. DMA support has been
split out to a separate patch to hopefully make it easier to review.
The driver has been tested using mmc-block and ext3fs on several SD,
SDHC and MMC+ cards. Reads and writes work fine, with read transfer
rates up to 3.5 MiB/s on fast cards with debugging disabled.
The driver has also been tested using the mmc_test module on the same
cards. All tests except 7, 9, 15 and 17 succeed. The first two are
unsupported by all the cards I have, so I don't know if the driver
handles this correctly. The last two fail because the hardware flags a
Data CRC Error instead of a Data Timeout error. I'm not sure how to deal
with that.
Documentation for this controller can be found in many data sheets from
Atmel, including the AT32AP7000 data sheet which can be found here:
http://www.atmel.com/dyn/products/datasheets.asp?family_id=682
Signed-off-by: Haavard Skinnemoen <haavard.skinnemoen@atmel.com>
Signed-off-by: Pierre Ossman <drzeus@drzeus.cx>
2008-06-30 10:35:03 -06:00
|
|
|
|
2012-05-16 07:26:01 -06:00
|
|
|
dev_dbg(&host->pdev->dev, "set completed not busy\n");
|
2012-05-16 07:25:59 -06:00
|
|
|
atmci_set_completed(host, EVENT_NOTBUSY);
|
|
|
|
|
|
|
|
if (host->data) {
|
|
|
|
/*
|
|
|
|
* For some commands such as CMD53, even if
|
|
|
|
* there is data transfer, there is no stop
|
|
|
|
* command to send.
|
|
|
|
*/
|
|
|
|
if (host->mrq->stop) {
|
|
|
|
atmci_writel(host, ATMCI_IER,
|
|
|
|
ATMCI_CMDRDY);
|
|
|
|
atmci_send_stop_cmd(host, data);
|
|
|
|
state = STATE_SENDING_STOP;
|
|
|
|
} else {
|
|
|
|
host->data = NULL;
|
|
|
|
data->bytes_xfered = data->blocks
|
|
|
|
* data->blksz;
|
|
|
|
data->error = 0;
|
|
|
|
state = STATE_END_REQUEST;
|
|
|
|
}
|
|
|
|
} else
|
|
|
|
state = STATE_END_REQUEST;
|
|
|
|
break;
|
2008-07-31 06:49:16 -06:00
|
|
|
|
|
|
|
case STATE_SENDING_STOP:
|
2012-05-16 07:25:59 -06:00
|
|
|
/*
|
|
|
|
* In this state, it is important to set host->data to
|
|
|
|
* NULL (which is tested in the waiting notbusy state)
|
|
|
|
* in order to go to the end request state instead of
|
|
|
|
* sending stop again.
|
|
|
|
*/
|
2012-05-16 07:26:01 -06:00
|
|
|
dev_dbg(&host->pdev->dev, "FSM: cmd ready?\n");
|
2008-07-31 06:49:16 -06:00
|
|
|
if (!atmci_test_and_clear_pending(host,
|
2012-05-16 07:25:59 -06:00
|
|
|
EVENT_CMD_RDY))
|
2008-07-31 06:49:16 -06:00
|
|
|
break;
|
|
|
|
|
2012-05-16 07:26:01 -06:00
|
|
|
dev_dbg(&host->pdev->dev, "FSM: cmd ready\n");
|
2008-07-31 06:49:16 -06:00
|
|
|
host->cmd = NULL;
|
2012-05-16 07:25:59 -06:00
|
|
|
data->bytes_xfered = data->blocks * data->blksz;
|
|
|
|
data->error = 0;
|
2008-07-31 06:49:16 -06:00
|
|
|
atmci_command_complete(host, mrq->stop);
|
2012-05-16 07:25:59 -06:00
|
|
|
if (mrq->stop->error) {
|
|
|
|
host->stop_transfer(host);
|
|
|
|
atmci_writel(host, ATMCI_IDR,
|
|
|
|
ATMCI_TXRDY | ATMCI_RXRDY
|
|
|
|
| ATMCI_DATA_ERROR_FLAGS);
|
|
|
|
state = STATE_END_REQUEST;
|
|
|
|
} else {
|
|
|
|
atmci_writel(host, ATMCI_IER, ATMCI_NOTBUSY);
|
|
|
|
state = STATE_WAITING_NOTBUSY;
|
|
|
|
}
|
2012-07-06 03:58:33 -06:00
|
|
|
host->data = NULL;
|
2012-05-16 07:25:59 -06:00
|
|
|
break;
|
2008-07-31 06:49:16 -06:00
|
|
|
|
2012-05-16 07:25:59 -06:00
|
|
|
case STATE_END_REQUEST:
|
|
|
|
atmci_writel(host, ATMCI_IDR, ATMCI_TXRDY | ATMCI_RXRDY
|
|
|
|
| ATMCI_DATA_ERROR_FLAGS);
|
|
|
|
status = host->data_status;
|
|
|
|
if (unlikely(status)) {
|
|
|
|
host->stop_transfer(host);
|
|
|
|
host->data = NULL;
|
2013-09-09 09:31:59 -06:00
|
|
|
if (data) {
|
|
|
|
if (status & ATMCI_DTOE) {
|
|
|
|
data->error = -ETIMEDOUT;
|
|
|
|
} else if (status & ATMCI_DCRCE) {
|
|
|
|
data->error = -EILSEQ;
|
|
|
|
} else {
|
|
|
|
data->error = -EIO;
|
|
|
|
}
|
2012-05-16 07:25:59 -06:00
|
|
|
}
|
|
|
|
}
|
2008-07-31 06:49:16 -06:00
|
|
|
|
2012-05-16 07:25:59 -06:00
|
|
|
atmci_request_end(host, host->mrq);
|
|
|
|
state = STATE_IDLE;
|
2008-07-31 06:49:16 -06:00
|
|
|
break;
|
|
|
|
}
|
|
|
|
} while (state != prev_state);
|
|
|
|
|
|
|
|
host->state = state;
|
atmel-mci: support multiple mmc slots
The Atmel MCI controller can drive multiple cards through separate sets
of pins, but only one at a time. This patch adds support for
multiplexing access to the controller so that multiple card slots can be
used as if they were hooked up to separate mmc controllers.
The atmel-mci driver registers each slot as a separate mmc_host. Both
access the same common controller state, but they also have some state
on their own for card detection/write protect handling, and separate
shadows of the MR and SDCR registers.
When one of the slots receives a request from the mmc core, the common
controller state is checked. If it's idle, the request is submitted
immediately. If not, the request is added to a queue. When a request is
done, the queue is checked and if there is a queued request, it is
submitted before the completion callback is called.
This patch also includes a few cleanups and fixes, including a locking
overhaul. I had to change the locking extensively in any case, so I
might as well try to get it right. The driver no longer takes any
irq-safe locks, which may or may not improve the overall system
performance.
This patch also adds a bit of documentation of the internal data
structures.
Signed-off-by: Haavard Skinnemoen <haavard.skinnemoen@atmel.com>
2008-09-17 12:53:55 -06:00
|
|
|
|
|
|
|
spin_unlock(&host->lock);
|
atmel-mci: Driver for Atmel on-chip MMC controllers
This is a driver for the MMC controller on the AP7000 chips from
Atmel. It should in theory work on AT91 systems too with some
tweaking, but since the DMA interface is quite different, it's not
entirely clear if it's worth merging this with the at91_mci driver.
This driver has been around for a while in BSPs and kernel sources
provided by Atmel, but this particular version uses the generic DMA
Engine framework (with the slave extensions) instead of an
avr32-only DMA controller framework.
This driver can also use PIO transfers when no DMA channels are
available, and for transfers where using DMA may be difficult or
impractical for some reason (e.g. the DMA setup overhead is usually
not worth it for very short transfers, and badly aligned buffers or
lengths are difficult to handle.)
Currently, the driver only support PIO transfers. DMA support has been
split out to a separate patch to hopefully make it easier to review.
The driver has been tested using mmc-block and ext3fs on several SD,
SDHC and MMC+ cards. Reads and writes work fine, with read transfer
rates up to 3.5 MiB/s on fast cards with debugging disabled.
The driver has also been tested using the mmc_test module on the same
cards. All tests except 7, 9, 15 and 17 succeed. The first two are
unsupported by all the cards I have, so I don't know if the driver
handles this correctly. The last two fail because the hardware flags a
Data CRC Error instead of a Data Timeout error. I'm not sure how to deal
with that.
Documentation for this controller can be found in many data sheets from
Atmel, including the AT32AP7000 data sheet which can be found here:
http://www.atmel.com/dyn/products/datasheets.asp?family_id=682
Signed-off-by: Haavard Skinnemoen <haavard.skinnemoen@atmel.com>
Signed-off-by: Pierre Ossman <drzeus@drzeus.cx>
2008-06-30 10:35:03 -06:00
|
|
|
}
|
|
|
|
|
|
|
|
static void atmci_read_data_pio(struct atmel_mci *host)
|
|
|
|
{
|
|
|
|
struct scatterlist *sg = host->sg;
|
|
|
|
void *buf = sg_virt(sg);
|
|
|
|
unsigned int offset = host->pio_offset;
|
|
|
|
struct mmc_data *data = host->data;
|
|
|
|
u32 value;
|
|
|
|
u32 status;
|
|
|
|
unsigned int nbytes = 0;
|
|
|
|
|
|
|
|
do {
|
2011-08-11 09:25:42 -06:00
|
|
|
value = atmci_readl(host, ATMCI_RDR);
|
atmel-mci: Driver for Atmel on-chip MMC controllers
This is a driver for the MMC controller on the AP7000 chips from
Atmel. It should in theory work on AT91 systems too with some
tweaking, but since the DMA interface is quite different, it's not
entirely clear if it's worth merging this with the at91_mci driver.
This driver has been around for a while in BSPs and kernel sources
provided by Atmel, but this particular version uses the generic DMA
Engine framework (with the slave extensions) instead of an
avr32-only DMA controller framework.
This driver can also use PIO transfers when no DMA channels are
available, and for transfers where using DMA may be difficult or
impractical for some reason (e.g. the DMA setup overhead is usually
not worth it for very short transfers, and badly aligned buffers or
lengths are difficult to handle.)
Currently, the driver only support PIO transfers. DMA support has been
split out to a separate patch to hopefully make it easier to review.
The driver has been tested using mmc-block and ext3fs on several SD,
SDHC and MMC+ cards. Reads and writes work fine, with read transfer
rates up to 3.5 MiB/s on fast cards with debugging disabled.
The driver has also been tested using the mmc_test module on the same
cards. All tests except 7, 9, 15 and 17 succeed. The first two are
unsupported by all the cards I have, so I don't know if the driver
handles this correctly. The last two fail because the hardware flags a
Data CRC Error instead of a Data Timeout error. I'm not sure how to deal
with that.
Documentation for this controller can be found in many data sheets from
Atmel, including the AT32AP7000 data sheet which can be found here:
http://www.atmel.com/dyn/products/datasheets.asp?family_id=682
Signed-off-by: Haavard Skinnemoen <haavard.skinnemoen@atmel.com>
Signed-off-by: Pierre Ossman <drzeus@drzeus.cx>
2008-06-30 10:35:03 -06:00
|
|
|
if (likely(offset + 4 <= sg->length)) {
|
|
|
|
put_unaligned(value, (u32 *)(buf + offset));
|
|
|
|
|
|
|
|
offset += 4;
|
|
|
|
nbytes += 4;
|
|
|
|
|
|
|
|
if (offset == sg->length) {
|
2008-10-05 07:27:50 -06:00
|
|
|
flush_dcache_page(sg_page(sg));
|
atmel-mci: Driver for Atmel on-chip MMC controllers
This is a driver for the MMC controller on the AP7000 chips from
Atmel. It should in theory work on AT91 systems too with some
tweaking, but since the DMA interface is quite different, it's not
entirely clear if it's worth merging this with the at91_mci driver.
This driver has been around for a while in BSPs and kernel sources
provided by Atmel, but this particular version uses the generic DMA
Engine framework (with the slave extensions) instead of an
avr32-only DMA controller framework.
This driver can also use PIO transfers when no DMA channels are
available, and for transfers where using DMA may be difficult or
impractical for some reason (e.g. the DMA setup overhead is usually
not worth it for very short transfers, and badly aligned buffers or
lengths are difficult to handle.)
Currently, the driver only support PIO transfers. DMA support has been
split out to a separate patch to hopefully make it easier to review.
The driver has been tested using mmc-block and ext3fs on several SD,
SDHC and MMC+ cards. Reads and writes work fine, with read transfer
rates up to 3.5 MiB/s on fast cards with debugging disabled.
The driver has also been tested using the mmc_test module on the same
cards. All tests except 7, 9, 15 and 17 succeed. The first two are
unsupported by all the cards I have, so I don't know if the driver
handles this correctly. The last two fail because the hardware flags a
Data CRC Error instead of a Data Timeout error. I'm not sure how to deal
with that.
Documentation for this controller can be found in many data sheets from
Atmel, including the AT32AP7000 data sheet which can be found here:
http://www.atmel.com/dyn/products/datasheets.asp?family_id=682
Signed-off-by: Haavard Skinnemoen <haavard.skinnemoen@atmel.com>
Signed-off-by: Pierre Ossman <drzeus@drzeus.cx>
2008-06-30 10:35:03 -06:00
|
|
|
host->sg = sg = sg_next(sg);
|
2013-04-08 10:05:47 -06:00
|
|
|
host->sg_len--;
|
|
|
|
if (!sg || !host->sg_len)
|
atmel-mci: Driver for Atmel on-chip MMC controllers
This is a driver for the MMC controller on the AP7000 chips from
Atmel. It should in theory work on AT91 systems too with some
tweaking, but since the DMA interface is quite different, it's not
entirely clear if it's worth merging this with the at91_mci driver.
This driver has been around for a while in BSPs and kernel sources
provided by Atmel, but this particular version uses the generic DMA
Engine framework (with the slave extensions) instead of an
avr32-only DMA controller framework.
This driver can also use PIO transfers when no DMA channels are
available, and for transfers where using DMA may be difficult or
impractical for some reason (e.g. the DMA setup overhead is usually
not worth it for very short transfers, and badly aligned buffers or
lengths are difficult to handle.)
Currently, the driver only support PIO transfers. DMA support has been
split out to a separate patch to hopefully make it easier to review.
The driver has been tested using mmc-block and ext3fs on several SD,
SDHC and MMC+ cards. Reads and writes work fine, with read transfer
rates up to 3.5 MiB/s on fast cards with debugging disabled.
The driver has also been tested using the mmc_test module on the same
cards. All tests except 7, 9, 15 and 17 succeed. The first two are
unsupported by all the cards I have, so I don't know if the driver
handles this correctly. The last two fail because the hardware flags a
Data CRC Error instead of a Data Timeout error. I'm not sure how to deal
with that.
Documentation for this controller can be found in many data sheets from
Atmel, including the AT32AP7000 data sheet which can be found here:
http://www.atmel.com/dyn/products/datasheets.asp?family_id=682
Signed-off-by: Haavard Skinnemoen <haavard.skinnemoen@atmel.com>
Signed-off-by: Pierre Ossman <drzeus@drzeus.cx>
2008-06-30 10:35:03 -06:00
|
|
|
goto done;
|
|
|
|
|
|
|
|
offset = 0;
|
|
|
|
buf = sg_virt(sg);
|
|
|
|
}
|
|
|
|
} else {
|
|
|
|
unsigned int remaining = sg->length - offset;
|
|
|
|
memcpy(buf + offset, &value, remaining);
|
|
|
|
nbytes += remaining;
|
|
|
|
|
|
|
|
flush_dcache_page(sg_page(sg));
|
|
|
|
host->sg = sg = sg_next(sg);
|
2013-04-08 10:05:47 -06:00
|
|
|
host->sg_len--;
|
|
|
|
if (!sg || !host->sg_len)
|
atmel-mci: Driver for Atmel on-chip MMC controllers
This is a driver for the MMC controller on the AP7000 chips from
Atmel. It should in theory work on AT91 systems too with some
tweaking, but since the DMA interface is quite different, it's not
entirely clear if it's worth merging this with the at91_mci driver.
This driver has been around for a while in BSPs and kernel sources
provided by Atmel, but this particular version uses the generic DMA
Engine framework (with the slave extensions) instead of an
avr32-only DMA controller framework.
This driver can also use PIO transfers when no DMA channels are
available, and for transfers where using DMA may be difficult or
impractical for some reason (e.g. the DMA setup overhead is usually
not worth it for very short transfers, and badly aligned buffers or
lengths are difficult to handle.)
Currently, the driver only support PIO transfers. DMA support has been
split out to a separate patch to hopefully make it easier to review.
The driver has been tested using mmc-block and ext3fs on several SD,
SDHC and MMC+ cards. Reads and writes work fine, with read transfer
rates up to 3.5 MiB/s on fast cards with debugging disabled.
The driver has also been tested using the mmc_test module on the same
cards. All tests except 7, 9, 15 and 17 succeed. The first two are
unsupported by all the cards I have, so I don't know if the driver
handles this correctly. The last two fail because the hardware flags a
Data CRC Error instead of a Data Timeout error. I'm not sure how to deal
with that.
Documentation for this controller can be found in many data sheets from
Atmel, including the AT32AP7000 data sheet which can be found here:
http://www.atmel.com/dyn/products/datasheets.asp?family_id=682
Signed-off-by: Haavard Skinnemoen <haavard.skinnemoen@atmel.com>
Signed-off-by: Pierre Ossman <drzeus@drzeus.cx>
2008-06-30 10:35:03 -06:00
|
|
|
goto done;
|
|
|
|
|
|
|
|
offset = 4 - remaining;
|
|
|
|
buf = sg_virt(sg);
|
|
|
|
memcpy(buf, (u8 *)&value + remaining, offset);
|
|
|
|
nbytes += offset;
|
|
|
|
}
|
|
|
|
|
2011-08-11 09:25:42 -06:00
|
|
|
status = atmci_readl(host, ATMCI_SR);
|
atmel-mci: Driver for Atmel on-chip MMC controllers
This is a driver for the MMC controller on the AP7000 chips from
Atmel. It should in theory work on AT91 systems too with some
tweaking, but since the DMA interface is quite different, it's not
entirely clear if it's worth merging this with the at91_mci driver.
This driver has been around for a while in BSPs and kernel sources
provided by Atmel, but this particular version uses the generic DMA
Engine framework (with the slave extensions) instead of an
avr32-only DMA controller framework.
This driver can also use PIO transfers when no DMA channels are
available, and for transfers where using DMA may be difficult or
impractical for some reason (e.g. the DMA setup overhead is usually
not worth it for very short transfers, and badly aligned buffers or
lengths are difficult to handle.)
Currently, the driver only support PIO transfers. DMA support has been
split out to a separate patch to hopefully make it easier to review.
The driver has been tested using mmc-block and ext3fs on several SD,
SDHC and MMC+ cards. Reads and writes work fine, with read transfer
rates up to 3.5 MiB/s on fast cards with debugging disabled.
The driver has also been tested using the mmc_test module on the same
cards. All tests except 7, 9, 15 and 17 succeed. The first two are
unsupported by all the cards I have, so I don't know if the driver
handles this correctly. The last two fail because the hardware flags a
Data CRC Error instead of a Data Timeout error. I'm not sure how to deal
with that.
Documentation for this controller can be found in many data sheets from
Atmel, including the AT32AP7000 data sheet which can be found here:
http://www.atmel.com/dyn/products/datasheets.asp?family_id=682
Signed-off-by: Haavard Skinnemoen <haavard.skinnemoen@atmel.com>
Signed-off-by: Pierre Ossman <drzeus@drzeus.cx>
2008-06-30 10:35:03 -06:00
|
|
|
if (status & ATMCI_DATA_ERROR_FLAGS) {
|
2011-08-11 09:25:42 -06:00
|
|
|
atmci_writel(host, ATMCI_IDR, (ATMCI_NOTBUSY | ATMCI_RXRDY
|
atmel-mci: Driver for Atmel on-chip MMC controllers
This is a driver for the MMC controller on the AP7000 chips from
Atmel. It should in theory work on AT91 systems too with some
tweaking, but since the DMA interface is quite different, it's not
entirely clear if it's worth merging this with the at91_mci driver.
This driver has been around for a while in BSPs and kernel sources
provided by Atmel, but this particular version uses the generic DMA
Engine framework (with the slave extensions) instead of an
avr32-only DMA controller framework.
This driver can also use PIO transfers when no DMA channels are
available, and for transfers where using DMA may be difficult or
impractical for some reason (e.g. the DMA setup overhead is usually
not worth it for very short transfers, and badly aligned buffers or
lengths are difficult to handle.)
Currently, the driver only support PIO transfers. DMA support has been
split out to a separate patch to hopefully make it easier to review.
The driver has been tested using mmc-block and ext3fs on several SD,
SDHC and MMC+ cards. Reads and writes work fine, with read transfer
rates up to 3.5 MiB/s on fast cards with debugging disabled.
The driver has also been tested using the mmc_test module on the same
cards. All tests except 7, 9, 15 and 17 succeed. The first two are
unsupported by all the cards I have, so I don't know if the driver
handles this correctly. The last two fail because the hardware flags a
Data CRC Error instead of a Data Timeout error. I'm not sure how to deal
with that.
Documentation for this controller can be found in many data sheets from
Atmel, including the AT32AP7000 data sheet which can be found here:
http://www.atmel.com/dyn/products/datasheets.asp?family_id=682
Signed-off-by: Haavard Skinnemoen <haavard.skinnemoen@atmel.com>
Signed-off-by: Pierre Ossman <drzeus@drzeus.cx>
2008-06-30 10:35:03 -06:00
|
|
|
| ATMCI_DATA_ERROR_FLAGS));
|
|
|
|
host->data_status = status;
|
atmel-mci: support multiple mmc slots
The Atmel MCI controller can drive multiple cards through separate sets
of pins, but only one at a time. This patch adds support for
multiplexing access to the controller so that multiple card slots can be
used as if they were hooked up to separate mmc controllers.
The atmel-mci driver registers each slot as a separate mmc_host. Both
access the same common controller state, but they also have some state
on their own for card detection/write protect handling, and separate
shadows of the MR and SDCR registers.
When one of the slots receives a request from the mmc core, the common
controller state is checked. If it's idle, the request is submitted
immediately. If not, the request is added to a queue. When a request is
done, the queue is checked and if there is a queued request, it is
submitted before the completion callback is called.
This patch also includes a few cleanups and fixes, including a locking
overhaul. I had to change the locking extensively in any case, so I
might as well try to get it right. The driver no longer takes any
irq-safe locks, which may or may not improve the overall system
performance.
This patch also adds a bit of documentation of the internal data
structures.
Signed-off-by: Haavard Skinnemoen <haavard.skinnemoen@atmel.com>
2008-09-17 12:53:55 -06:00
|
|
|
data->bytes_xfered += nbytes;
|
|
|
|
return;
|
atmel-mci: Driver for Atmel on-chip MMC controllers
This is a driver for the MMC controller on the AP7000 chips from
Atmel. It should in theory work on AT91 systems too with some
tweaking, but since the DMA interface is quite different, it's not
entirely clear if it's worth merging this with the at91_mci driver.
This driver has been around for a while in BSPs and kernel sources
provided by Atmel, but this particular version uses the generic DMA
Engine framework (with the slave extensions) instead of an
avr32-only DMA controller framework.
This driver can also use PIO transfers when no DMA channels are
available, and for transfers where using DMA may be difficult or
impractical for some reason (e.g. the DMA setup overhead is usually
not worth it for very short transfers, and badly aligned buffers or
lengths are difficult to handle.)
Currently, the driver only support PIO transfers. DMA support has been
split out to a separate patch to hopefully make it easier to review.
The driver has been tested using mmc-block and ext3fs on several SD,
SDHC and MMC+ cards. Reads and writes work fine, with read transfer
rates up to 3.5 MiB/s on fast cards with debugging disabled.
The driver has also been tested using the mmc_test module on the same
cards. All tests except 7, 9, 15 and 17 succeed. The first two are
unsupported by all the cards I have, so I don't know if the driver
handles this correctly. The last two fail because the hardware flags a
Data CRC Error instead of a Data Timeout error. I'm not sure how to deal
with that.
Documentation for this controller can be found in many data sheets from
Atmel, including the AT32AP7000 data sheet which can be found here:
http://www.atmel.com/dyn/products/datasheets.asp?family_id=682
Signed-off-by: Haavard Skinnemoen <haavard.skinnemoen@atmel.com>
Signed-off-by: Pierre Ossman <drzeus@drzeus.cx>
2008-06-30 10:35:03 -06:00
|
|
|
}
|
2011-08-11 09:25:41 -06:00
|
|
|
} while (status & ATMCI_RXRDY);
|
atmel-mci: Driver for Atmel on-chip MMC controllers
This is a driver for the MMC controller on the AP7000 chips from
Atmel. It should in theory work on AT91 systems too with some
tweaking, but since the DMA interface is quite different, it's not
entirely clear if it's worth merging this with the at91_mci driver.
This driver has been around for a while in BSPs and kernel sources
provided by Atmel, but this particular version uses the generic DMA
Engine framework (with the slave extensions) instead of an
avr32-only DMA controller framework.
This driver can also use PIO transfers when no DMA channels are
available, and for transfers where using DMA may be difficult or
impractical for some reason (e.g. the DMA setup overhead is usually
not worth it for very short transfers, and badly aligned buffers or
lengths are difficult to handle.)
Currently, the driver only support PIO transfers. DMA support has been
split out to a separate patch to hopefully make it easier to review.
The driver has been tested using mmc-block and ext3fs on several SD,
SDHC and MMC+ cards. Reads and writes work fine, with read transfer
rates up to 3.5 MiB/s on fast cards with debugging disabled.
The driver has also been tested using the mmc_test module on the same
cards. All tests except 7, 9, 15 and 17 succeed. The first two are
unsupported by all the cards I have, so I don't know if the driver
handles this correctly. The last two fail because the hardware flags a
Data CRC Error instead of a Data Timeout error. I'm not sure how to deal
with that.
Documentation for this controller can be found in many data sheets from
Atmel, including the AT32AP7000 data sheet which can be found here:
http://www.atmel.com/dyn/products/datasheets.asp?family_id=682
Signed-off-by: Haavard Skinnemoen <haavard.skinnemoen@atmel.com>
Signed-off-by: Pierre Ossman <drzeus@drzeus.cx>
2008-06-30 10:35:03 -06:00
|
|
|
|
|
|
|
host->pio_offset = offset;
|
|
|
|
data->bytes_xfered += nbytes;
|
|
|
|
|
|
|
|
return;
|
|
|
|
|
|
|
|
done:
|
2011-08-11 09:25:42 -06:00
|
|
|
atmci_writel(host, ATMCI_IDR, ATMCI_RXRDY);
|
|
|
|
atmci_writel(host, ATMCI_IER, ATMCI_NOTBUSY);
|
atmel-mci: Driver for Atmel on-chip MMC controllers
This is a driver for the MMC controller on the AP7000 chips from
Atmel. It should in theory work on AT91 systems too with some
tweaking, but since the DMA interface is quite different, it's not
entirely clear if it's worth merging this with the at91_mci driver.
This driver has been around for a while in BSPs and kernel sources
provided by Atmel, but this particular version uses the generic DMA
Engine framework (with the slave extensions) instead of an
avr32-only DMA controller framework.
This driver can also use PIO transfers when no DMA channels are
available, and for transfers where using DMA may be difficult or
impractical for some reason (e.g. the DMA setup overhead is usually
not worth it for very short transfers, and badly aligned buffers or
lengths are difficult to handle.)
Currently, the driver only support PIO transfers. DMA support has been
split out to a separate patch to hopefully make it easier to review.
The driver has been tested using mmc-block and ext3fs on several SD,
SDHC and MMC+ cards. Reads and writes work fine, with read transfer
rates up to 3.5 MiB/s on fast cards with debugging disabled.
The driver has also been tested using the mmc_test module on the same
cards. All tests except 7, 9, 15 and 17 succeed. The first two are
unsupported by all the cards I have, so I don't know if the driver
handles this correctly. The last two fail because the hardware flags a
Data CRC Error instead of a Data Timeout error. I'm not sure how to deal
with that.
Documentation for this controller can be found in many data sheets from
Atmel, including the AT32AP7000 data sheet which can be found here:
http://www.atmel.com/dyn/products/datasheets.asp?family_id=682
Signed-off-by: Haavard Skinnemoen <haavard.skinnemoen@atmel.com>
Signed-off-by: Pierre Ossman <drzeus@drzeus.cx>
2008-06-30 10:35:03 -06:00
|
|
|
data->bytes_xfered += nbytes;
|
atmel-mci: support multiple mmc slots
The Atmel MCI controller can drive multiple cards through separate sets
of pins, but only one at a time. This patch adds support for
multiplexing access to the controller so that multiple card slots can be
used as if they were hooked up to separate mmc controllers.
The atmel-mci driver registers each slot as a separate mmc_host. Both
access the same common controller state, but they also have some state
on their own for card detection/write protect handling, and separate
shadows of the MR and SDCR registers.
When one of the slots receives a request from the mmc core, the common
controller state is checked. If it's idle, the request is submitted
immediately. If not, the request is added to a queue. When a request is
done, the queue is checked and if there is a queued request, it is
submitted before the completion callback is called.
This patch also includes a few cleanups and fixes, including a locking
overhaul. I had to change the locking extensively in any case, so I
might as well try to get it right. The driver no longer takes any
irq-safe locks, which may or may not improve the overall system
performance.
This patch also adds a bit of documentation of the internal data
structures.
Signed-off-by: Haavard Skinnemoen <haavard.skinnemoen@atmel.com>
2008-09-17 12:53:55 -06:00
|
|
|
smp_wmb();
|
2008-07-31 06:49:16 -06:00
|
|
|
atmci_set_pending(host, EVENT_XFER_COMPLETE);
|
atmel-mci: Driver for Atmel on-chip MMC controllers
This is a driver for the MMC controller on the AP7000 chips from
Atmel. It should in theory work on AT91 systems too with some
tweaking, but since the DMA interface is quite different, it's not
entirely clear if it's worth merging this with the at91_mci driver.
This driver has been around for a while in BSPs and kernel sources
provided by Atmel, but this particular version uses the generic DMA
Engine framework (with the slave extensions) instead of an
avr32-only DMA controller framework.
This driver can also use PIO transfers when no DMA channels are
available, and for transfers where using DMA may be difficult or
impractical for some reason (e.g. the DMA setup overhead is usually
not worth it for very short transfers, and badly aligned buffers or
lengths are difficult to handle.)
Currently, the driver only support PIO transfers. DMA support has been
split out to a separate patch to hopefully make it easier to review.
The driver has been tested using mmc-block and ext3fs on several SD,
SDHC and MMC+ cards. Reads and writes work fine, with read transfer
rates up to 3.5 MiB/s on fast cards with debugging disabled.
The driver has also been tested using the mmc_test module on the same
cards. All tests except 7, 9, 15 and 17 succeed. The first two are
unsupported by all the cards I have, so I don't know if the driver
handles this correctly. The last two fail because the hardware flags a
Data CRC Error instead of a Data Timeout error. I'm not sure how to deal
with that.
Documentation for this controller can be found in many data sheets from
Atmel, including the AT32AP7000 data sheet which can be found here:
http://www.atmel.com/dyn/products/datasheets.asp?family_id=682
Signed-off-by: Haavard Skinnemoen <haavard.skinnemoen@atmel.com>
Signed-off-by: Pierre Ossman <drzeus@drzeus.cx>
2008-06-30 10:35:03 -06:00
|
|
|
}
|
|
|
|
|
|
|
|
static void atmci_write_data_pio(struct atmel_mci *host)
|
|
|
|
{
|
|
|
|
struct scatterlist *sg = host->sg;
|
|
|
|
void *buf = sg_virt(sg);
|
|
|
|
unsigned int offset = host->pio_offset;
|
|
|
|
struct mmc_data *data = host->data;
|
|
|
|
u32 value;
|
|
|
|
u32 status;
|
|
|
|
unsigned int nbytes = 0;
|
|
|
|
|
|
|
|
do {
|
|
|
|
if (likely(offset + 4 <= sg->length)) {
|
|
|
|
value = get_unaligned((u32 *)(buf + offset));
|
2011-08-11 09:25:42 -06:00
|
|
|
atmci_writel(host, ATMCI_TDR, value);
|
atmel-mci: Driver for Atmel on-chip MMC controllers
This is a driver for the MMC controller on the AP7000 chips from
Atmel. It should in theory work on AT91 systems too with some
tweaking, but since the DMA interface is quite different, it's not
entirely clear if it's worth merging this with the at91_mci driver.
This driver has been around for a while in BSPs and kernel sources
provided by Atmel, but this particular version uses the generic DMA
Engine framework (with the slave extensions) instead of an
avr32-only DMA controller framework.
This driver can also use PIO transfers when no DMA channels are
available, and for transfers where using DMA may be difficult or
impractical for some reason (e.g. the DMA setup overhead is usually
not worth it for very short transfers, and badly aligned buffers or
lengths are difficult to handle.)
Currently, the driver only support PIO transfers. DMA support has been
split out to a separate patch to hopefully make it easier to review.
The driver has been tested using mmc-block and ext3fs on several SD,
SDHC and MMC+ cards. Reads and writes work fine, with read transfer
rates up to 3.5 MiB/s on fast cards with debugging disabled.
The driver has also been tested using the mmc_test module on the same
cards. All tests except 7, 9, 15 and 17 succeed. The first two are
unsupported by all the cards I have, so I don't know if the driver
handles this correctly. The last two fail because the hardware flags a
Data CRC Error instead of a Data Timeout error. I'm not sure how to deal
with that.
Documentation for this controller can be found in many data sheets from
Atmel, including the AT32AP7000 data sheet which can be found here:
http://www.atmel.com/dyn/products/datasheets.asp?family_id=682
Signed-off-by: Haavard Skinnemoen <haavard.skinnemoen@atmel.com>
Signed-off-by: Pierre Ossman <drzeus@drzeus.cx>
2008-06-30 10:35:03 -06:00
|
|
|
|
|
|
|
offset += 4;
|
|
|
|
nbytes += 4;
|
|
|
|
if (offset == sg->length) {
|
|
|
|
host->sg = sg = sg_next(sg);
|
2013-04-08 10:05:47 -06:00
|
|
|
host->sg_len--;
|
|
|
|
if (!sg || !host->sg_len)
|
atmel-mci: Driver for Atmel on-chip MMC controllers
This is a driver for the MMC controller on the AP7000 chips from
Atmel. It should in theory work on AT91 systems too with some
tweaking, but since the DMA interface is quite different, it's not
entirely clear if it's worth merging this with the at91_mci driver.
This driver has been around for a while in BSPs and kernel sources
provided by Atmel, but this particular version uses the generic DMA
Engine framework (with the slave extensions) instead of an
avr32-only DMA controller framework.
This driver can also use PIO transfers when no DMA channels are
available, and for transfers where using DMA may be difficult or
impractical for some reason (e.g. the DMA setup overhead is usually
not worth it for very short transfers, and badly aligned buffers or
lengths are difficult to handle.)
Currently, the driver only support PIO transfers. DMA support has been
split out to a separate patch to hopefully make it easier to review.
The driver has been tested using mmc-block and ext3fs on several SD,
SDHC and MMC+ cards. Reads and writes work fine, with read transfer
rates up to 3.5 MiB/s on fast cards with debugging disabled.
The driver has also been tested using the mmc_test module on the same
cards. All tests except 7, 9, 15 and 17 succeed. The first two are
unsupported by all the cards I have, so I don't know if the driver
handles this correctly. The last two fail because the hardware flags a
Data CRC Error instead of a Data Timeout error. I'm not sure how to deal
with that.
Documentation for this controller can be found in many data sheets from
Atmel, including the AT32AP7000 data sheet which can be found here:
http://www.atmel.com/dyn/products/datasheets.asp?family_id=682
Signed-off-by: Haavard Skinnemoen <haavard.skinnemoen@atmel.com>
Signed-off-by: Pierre Ossman <drzeus@drzeus.cx>
2008-06-30 10:35:03 -06:00
|
|
|
goto done;
|
|
|
|
|
|
|
|
offset = 0;
|
|
|
|
buf = sg_virt(sg);
|
|
|
|
}
|
|
|
|
} else {
|
|
|
|
unsigned int remaining = sg->length - offset;
|
|
|
|
|
|
|
|
value = 0;
|
|
|
|
memcpy(&value, buf + offset, remaining);
|
|
|
|
nbytes += remaining;
|
|
|
|
|
|
|
|
host->sg = sg = sg_next(sg);
|
2013-04-08 10:05:47 -06:00
|
|
|
host->sg_len--;
|
|
|
|
if (!sg || !host->sg_len) {
|
2011-08-11 09:25:42 -06:00
|
|
|
atmci_writel(host, ATMCI_TDR, value);
|
atmel-mci: Driver for Atmel on-chip MMC controllers
This is a driver for the MMC controller on the AP7000 chips from
Atmel. It should in theory work on AT91 systems too with some
tweaking, but since the DMA interface is quite different, it's not
entirely clear if it's worth merging this with the at91_mci driver.
This driver has been around for a while in BSPs and kernel sources
provided by Atmel, but this particular version uses the generic DMA
Engine framework (with the slave extensions) instead of an
avr32-only DMA controller framework.
This driver can also use PIO transfers when no DMA channels are
available, and for transfers where using DMA may be difficult or
impractical for some reason (e.g. the DMA setup overhead is usually
not worth it for very short transfers, and badly aligned buffers or
lengths are difficult to handle.)
Currently, the driver only support PIO transfers. DMA support has been
split out to a separate patch to hopefully make it easier to review.
The driver has been tested using mmc-block and ext3fs on several SD,
SDHC and MMC+ cards. Reads and writes work fine, with read transfer
rates up to 3.5 MiB/s on fast cards with debugging disabled.
The driver has also been tested using the mmc_test module on the same
cards. All tests except 7, 9, 15 and 17 succeed. The first two are
unsupported by all the cards I have, so I don't know if the driver
handles this correctly. The last two fail because the hardware flags a
Data CRC Error instead of a Data Timeout error. I'm not sure how to deal
with that.
Documentation for this controller can be found in many data sheets from
Atmel, including the AT32AP7000 data sheet which can be found here:
http://www.atmel.com/dyn/products/datasheets.asp?family_id=682
Signed-off-by: Haavard Skinnemoen <haavard.skinnemoen@atmel.com>
Signed-off-by: Pierre Ossman <drzeus@drzeus.cx>
2008-06-30 10:35:03 -06:00
|
|
|
goto done;
|
|
|
|
}
|
|
|
|
|
|
|
|
offset = 4 - remaining;
|
|
|
|
buf = sg_virt(sg);
|
|
|
|
memcpy((u8 *)&value + remaining, buf, offset);
|
2011-08-11 09:25:42 -06:00
|
|
|
atmci_writel(host, ATMCI_TDR, value);
|
atmel-mci: Driver for Atmel on-chip MMC controllers
This is a driver for the MMC controller on the AP7000 chips from
Atmel. It should in theory work on AT91 systems too with some
tweaking, but since the DMA interface is quite different, it's not
entirely clear if it's worth merging this with the at91_mci driver.
This driver has been around for a while in BSPs and kernel sources
provided by Atmel, but this particular version uses the generic DMA
Engine framework (with the slave extensions) instead of an
avr32-only DMA controller framework.
This driver can also use PIO transfers when no DMA channels are
available, and for transfers where using DMA may be difficult or
impractical for some reason (e.g. the DMA setup overhead is usually
not worth it for very short transfers, and badly aligned buffers or
lengths are difficult to handle.)
Currently, the driver only support PIO transfers. DMA support has been
split out to a separate patch to hopefully make it easier to review.
The driver has been tested using mmc-block and ext3fs on several SD,
SDHC and MMC+ cards. Reads and writes work fine, with read transfer
rates up to 3.5 MiB/s on fast cards with debugging disabled.
The driver has also been tested using the mmc_test module on the same
cards. All tests except 7, 9, 15 and 17 succeed. The first two are
unsupported by all the cards I have, so I don't know if the driver
handles this correctly. The last two fail because the hardware flags a
Data CRC Error instead of a Data Timeout error. I'm not sure how to deal
with that.
Documentation for this controller can be found in many data sheets from
Atmel, including the AT32AP7000 data sheet which can be found here:
http://www.atmel.com/dyn/products/datasheets.asp?family_id=682
Signed-off-by: Haavard Skinnemoen <haavard.skinnemoen@atmel.com>
Signed-off-by: Pierre Ossman <drzeus@drzeus.cx>
2008-06-30 10:35:03 -06:00
|
|
|
nbytes += offset;
|
|
|
|
}
|
|
|
|
|
2011-08-11 09:25:42 -06:00
|
|
|
status = atmci_readl(host, ATMCI_SR);
|
atmel-mci: Driver for Atmel on-chip MMC controllers
This is a driver for the MMC controller on the AP7000 chips from
Atmel. It should in theory work on AT91 systems too with some
tweaking, but since the DMA interface is quite different, it's not
entirely clear if it's worth merging this with the at91_mci driver.
This driver has been around for a while in BSPs and kernel sources
provided by Atmel, but this particular version uses the generic DMA
Engine framework (with the slave extensions) instead of an
avr32-only DMA controller framework.
This driver can also use PIO transfers when no DMA channels are
available, and for transfers where using DMA may be difficult or
impractical for some reason (e.g. the DMA setup overhead is usually
not worth it for very short transfers, and badly aligned buffers or
lengths are difficult to handle.)
Currently, the driver only support PIO transfers. DMA support has been
split out to a separate patch to hopefully make it easier to review.
The driver has been tested using mmc-block and ext3fs on several SD,
SDHC and MMC+ cards. Reads and writes work fine, with read transfer
rates up to 3.5 MiB/s on fast cards with debugging disabled.
The driver has also been tested using the mmc_test module on the same
cards. All tests except 7, 9, 15 and 17 succeed. The first two are
unsupported by all the cards I have, so I don't know if the driver
handles this correctly. The last two fail because the hardware flags a
Data CRC Error instead of a Data Timeout error. I'm not sure how to deal
with that.
Documentation for this controller can be found in many data sheets from
Atmel, including the AT32AP7000 data sheet which can be found here:
http://www.atmel.com/dyn/products/datasheets.asp?family_id=682
Signed-off-by: Haavard Skinnemoen <haavard.skinnemoen@atmel.com>
Signed-off-by: Pierre Ossman <drzeus@drzeus.cx>
2008-06-30 10:35:03 -06:00
|
|
|
if (status & ATMCI_DATA_ERROR_FLAGS) {
|
2011-08-11 09:25:42 -06:00
|
|
|
atmci_writel(host, ATMCI_IDR, (ATMCI_NOTBUSY | ATMCI_TXRDY
|
atmel-mci: Driver for Atmel on-chip MMC controllers
This is a driver for the MMC controller on the AP7000 chips from
Atmel. It should in theory work on AT91 systems too with some
tweaking, but since the DMA interface is quite different, it's not
entirely clear if it's worth merging this with the at91_mci driver.
This driver has been around for a while in BSPs and kernel sources
provided by Atmel, but this particular version uses the generic DMA
Engine framework (with the slave extensions) instead of an
avr32-only DMA controller framework.
This driver can also use PIO transfers when no DMA channels are
available, and for transfers where using DMA may be difficult or
impractical for some reason (e.g. the DMA setup overhead is usually
not worth it for very short transfers, and badly aligned buffers or
lengths are difficult to handle.)
Currently, the driver only support PIO transfers. DMA support has been
split out to a separate patch to hopefully make it easier to review.
The driver has been tested using mmc-block and ext3fs on several SD,
SDHC and MMC+ cards. Reads and writes work fine, with read transfer
rates up to 3.5 MiB/s on fast cards with debugging disabled.
The driver has also been tested using the mmc_test module on the same
cards. All tests except 7, 9, 15 and 17 succeed. The first two are
unsupported by all the cards I have, so I don't know if the driver
handles this correctly. The last two fail because the hardware flags a
Data CRC Error instead of a Data Timeout error. I'm not sure how to deal
with that.
Documentation for this controller can be found in many data sheets from
Atmel, including the AT32AP7000 data sheet which can be found here:
http://www.atmel.com/dyn/products/datasheets.asp?family_id=682
Signed-off-by: Haavard Skinnemoen <haavard.skinnemoen@atmel.com>
Signed-off-by: Pierre Ossman <drzeus@drzeus.cx>
2008-06-30 10:35:03 -06:00
|
|
|
| ATMCI_DATA_ERROR_FLAGS));
|
|
|
|
host->data_status = status;
|
atmel-mci: support multiple mmc slots
The Atmel MCI controller can drive multiple cards through separate sets
of pins, but only one at a time. This patch adds support for
multiplexing access to the controller so that multiple card slots can be
used as if they were hooked up to separate mmc controllers.
The atmel-mci driver registers each slot as a separate mmc_host. Both
access the same common controller state, but they also have some state
on their own for card detection/write protect handling, and separate
shadows of the MR and SDCR registers.
When one of the slots receives a request from the mmc core, the common
controller state is checked. If it's idle, the request is submitted
immediately. If not, the request is added to a queue. When a request is
done, the queue is checked and if there is a queued request, it is
submitted before the completion callback is called.
This patch also includes a few cleanups and fixes, including a locking
overhaul. I had to change the locking extensively in any case, so I
might as well try to get it right. The driver no longer takes any
irq-safe locks, which may or may not improve the overall system
performance.
This patch also adds a bit of documentation of the internal data
structures.
Signed-off-by: Haavard Skinnemoen <haavard.skinnemoen@atmel.com>
2008-09-17 12:53:55 -06:00
|
|
|
data->bytes_xfered += nbytes;
|
|
|
|
return;
|
atmel-mci: Driver for Atmel on-chip MMC controllers
This is a driver for the MMC controller on the AP7000 chips from
Atmel. It should in theory work on AT91 systems too with some
tweaking, but since the DMA interface is quite different, it's not
entirely clear if it's worth merging this with the at91_mci driver.
This driver has been around for a while in BSPs and kernel sources
provided by Atmel, but this particular version uses the generic DMA
Engine framework (with the slave extensions) instead of an
avr32-only DMA controller framework.
This driver can also use PIO transfers when no DMA channels are
available, and for transfers where using DMA may be difficult or
impractical for some reason (e.g. the DMA setup overhead is usually
not worth it for very short transfers, and badly aligned buffers or
lengths are difficult to handle.)
Currently, the driver only support PIO transfers. DMA support has been
split out to a separate patch to hopefully make it easier to review.
The driver has been tested using mmc-block and ext3fs on several SD,
SDHC and MMC+ cards. Reads and writes work fine, with read transfer
rates up to 3.5 MiB/s on fast cards with debugging disabled.
The driver has also been tested using the mmc_test module on the same
cards. All tests except 7, 9, 15 and 17 succeed. The first two are
unsupported by all the cards I have, so I don't know if the driver
handles this correctly. The last two fail because the hardware flags a
Data CRC Error instead of a Data Timeout error. I'm not sure how to deal
with that.
Documentation for this controller can be found in many data sheets from
Atmel, including the AT32AP7000 data sheet which can be found here:
http://www.atmel.com/dyn/products/datasheets.asp?family_id=682
Signed-off-by: Haavard Skinnemoen <haavard.skinnemoen@atmel.com>
Signed-off-by: Pierre Ossman <drzeus@drzeus.cx>
2008-06-30 10:35:03 -06:00
|
|
|
}
|
2011-08-11 09:25:41 -06:00
|
|
|
} while (status & ATMCI_TXRDY);
|
atmel-mci: Driver for Atmel on-chip MMC controllers
This is a driver for the MMC controller on the AP7000 chips from
Atmel. It should in theory work on AT91 systems too with some
tweaking, but since the DMA interface is quite different, it's not
entirely clear if it's worth merging this with the at91_mci driver.
This driver has been around for a while in BSPs and kernel sources
provided by Atmel, but this particular version uses the generic DMA
Engine framework (with the slave extensions) instead of an
avr32-only DMA controller framework.
This driver can also use PIO transfers when no DMA channels are
available, and for transfers where using DMA may be difficult or
impractical for some reason (e.g. the DMA setup overhead is usually
not worth it for very short transfers, and badly aligned buffers or
lengths are difficult to handle.)
Currently, the driver only support PIO transfers. DMA support has been
split out to a separate patch to hopefully make it easier to review.
The driver has been tested using mmc-block and ext3fs on several SD,
SDHC and MMC+ cards. Reads and writes work fine, with read transfer
rates up to 3.5 MiB/s on fast cards with debugging disabled.
The driver has also been tested using the mmc_test module on the same
cards. All tests except 7, 9, 15 and 17 succeed. The first two are
unsupported by all the cards I have, so I don't know if the driver
handles this correctly. The last two fail because the hardware flags a
Data CRC Error instead of a Data Timeout error. I'm not sure how to deal
with that.
Documentation for this controller can be found in many data sheets from
Atmel, including the AT32AP7000 data sheet which can be found here:
http://www.atmel.com/dyn/products/datasheets.asp?family_id=682
Signed-off-by: Haavard Skinnemoen <haavard.skinnemoen@atmel.com>
Signed-off-by: Pierre Ossman <drzeus@drzeus.cx>
2008-06-30 10:35:03 -06:00
|
|
|
|
|
|
|
host->pio_offset = offset;
|
|
|
|
data->bytes_xfered += nbytes;
|
|
|
|
|
|
|
|
return;
|
|
|
|
|
|
|
|
done:
|
2011-08-11 09:25:42 -06:00
|
|
|
atmci_writel(host, ATMCI_IDR, ATMCI_TXRDY);
|
|
|
|
atmci_writel(host, ATMCI_IER, ATMCI_NOTBUSY);
|
atmel-mci: Driver for Atmel on-chip MMC controllers
This is a driver for the MMC controller on the AP7000 chips from
Atmel. It should in theory work on AT91 systems too with some
tweaking, but since the DMA interface is quite different, it's not
entirely clear if it's worth merging this with the at91_mci driver.
This driver has been around for a while in BSPs and kernel sources
provided by Atmel, but this particular version uses the generic DMA
Engine framework (with the slave extensions) instead of an
avr32-only DMA controller framework.
This driver can also use PIO transfers when no DMA channels are
available, and for transfers where using DMA may be difficult or
impractical for some reason (e.g. the DMA setup overhead is usually
not worth it for very short transfers, and badly aligned buffers or
lengths are difficult to handle.)
Currently, the driver only support PIO transfers. DMA support has been
split out to a separate patch to hopefully make it easier to review.
The driver has been tested using mmc-block and ext3fs on several SD,
SDHC and MMC+ cards. Reads and writes work fine, with read transfer
rates up to 3.5 MiB/s on fast cards with debugging disabled.
The driver has also been tested using the mmc_test module on the same
cards. All tests except 7, 9, 15 and 17 succeed. The first two are
unsupported by all the cards I have, so I don't know if the driver
handles this correctly. The last two fail because the hardware flags a
Data CRC Error instead of a Data Timeout error. I'm not sure how to deal
with that.
Documentation for this controller can be found in many data sheets from
Atmel, including the AT32AP7000 data sheet which can be found here:
http://www.atmel.com/dyn/products/datasheets.asp?family_id=682
Signed-off-by: Haavard Skinnemoen <haavard.skinnemoen@atmel.com>
Signed-off-by: Pierre Ossman <drzeus@drzeus.cx>
2008-06-30 10:35:03 -06:00
|
|
|
data->bytes_xfered += nbytes;
|
atmel-mci: support multiple mmc slots
The Atmel MCI controller can drive multiple cards through separate sets
of pins, but only one at a time. This patch adds support for
multiplexing access to the controller so that multiple card slots can be
used as if they were hooked up to separate mmc controllers.
The atmel-mci driver registers each slot as a separate mmc_host. Both
access the same common controller state, but they also have some state
on their own for card detection/write protect handling, and separate
shadows of the MR and SDCR registers.
When one of the slots receives a request from the mmc core, the common
controller state is checked. If it's idle, the request is submitted
immediately. If not, the request is added to a queue. When a request is
done, the queue is checked and if there is a queued request, it is
submitted before the completion callback is called.
This patch also includes a few cleanups and fixes, including a locking
overhaul. I had to change the locking extensively in any case, so I
might as well try to get it right. The driver no longer takes any
irq-safe locks, which may or may not improve the overall system
performance.
This patch also adds a bit of documentation of the internal data
structures.
Signed-off-by: Haavard Skinnemoen <haavard.skinnemoen@atmel.com>
2008-09-17 12:53:55 -06:00
|
|
|
smp_wmb();
|
2008-07-31 06:49:16 -06:00
|
|
|
atmci_set_pending(host, EVENT_XFER_COMPLETE);
|
atmel-mci: Driver for Atmel on-chip MMC controllers
This is a driver for the MMC controller on the AP7000 chips from
Atmel. It should in theory work on AT91 systems too with some
tweaking, but since the DMA interface is quite different, it's not
entirely clear if it's worth merging this with the at91_mci driver.
This driver has been around for a while in BSPs and kernel sources
provided by Atmel, but this particular version uses the generic DMA
Engine framework (with the slave extensions) instead of an
avr32-only DMA controller framework.
This driver can also use PIO transfers when no DMA channels are
available, and for transfers where using DMA may be difficult or
impractical for some reason (e.g. the DMA setup overhead is usually
not worth it for very short transfers, and badly aligned buffers or
lengths are difficult to handle.)
Currently, the driver only support PIO transfers. DMA support has been
split out to a separate patch to hopefully make it easier to review.
The driver has been tested using mmc-block and ext3fs on several SD,
SDHC and MMC+ cards. Reads and writes work fine, with read transfer
rates up to 3.5 MiB/s on fast cards with debugging disabled.
The driver has also been tested using the mmc_test module on the same
cards. All tests except 7, 9, 15 and 17 succeed. The first two are
unsupported by all the cards I have, so I don't know if the driver
handles this correctly. The last two fail because the hardware flags a
Data CRC Error instead of a Data Timeout error. I'm not sure how to deal
with that.
Documentation for this controller can be found in many data sheets from
Atmel, including the AT32AP7000 data sheet which can be found here:
http://www.atmel.com/dyn/products/datasheets.asp?family_id=682
Signed-off-by: Haavard Skinnemoen <haavard.skinnemoen@atmel.com>
Signed-off-by: Pierre Ossman <drzeus@drzeus.cx>
2008-06-30 10:35:03 -06:00
|
|
|
}
|
|
|
|
|
2010-05-26 15:42:01 -06:00
|
|
|
static void atmci_sdio_interrupt(struct atmel_mci *host, u32 status)
|
|
|
|
{
|
|
|
|
int i;
|
|
|
|
|
2011-08-11 09:25:41 -06:00
|
|
|
for (i = 0; i < ATMCI_MAX_NR_SLOTS; i++) {
|
2010-05-26 15:42:01 -06:00
|
|
|
struct atmel_mci_slot *slot = host->slot[i];
|
|
|
|
if (slot && (status & slot->sdio_irq)) {
|
|
|
|
mmc_signal_sdio_irq(slot->mmc);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
|
atmel-mci: Driver for Atmel on-chip MMC controllers
This is a driver for the MMC controller on the AP7000 chips from
Atmel. It should in theory work on AT91 systems too with some
tweaking, but since the DMA interface is quite different, it's not
entirely clear if it's worth merging this with the at91_mci driver.
This driver has been around for a while in BSPs and kernel sources
provided by Atmel, but this particular version uses the generic DMA
Engine framework (with the slave extensions) instead of an
avr32-only DMA controller framework.
This driver can also use PIO transfers when no DMA channels are
available, and for transfers where using DMA may be difficult or
impractical for some reason (e.g. the DMA setup overhead is usually
not worth it for very short transfers, and badly aligned buffers or
lengths are difficult to handle.)
Currently, the driver only support PIO transfers. DMA support has been
split out to a separate patch to hopefully make it easier to review.
The driver has been tested using mmc-block and ext3fs on several SD,
SDHC and MMC+ cards. Reads and writes work fine, with read transfer
rates up to 3.5 MiB/s on fast cards with debugging disabled.
The driver has also been tested using the mmc_test module on the same
cards. All tests except 7, 9, 15 and 17 succeed. The first two are
unsupported by all the cards I have, so I don't know if the driver
handles this correctly. The last two fail because the hardware flags a
Data CRC Error instead of a Data Timeout error. I'm not sure how to deal
with that.
Documentation for this controller can be found in many data sheets from
Atmel, including the AT32AP7000 data sheet which can be found here:
http://www.atmel.com/dyn/products/datasheets.asp?family_id=682
Signed-off-by: Haavard Skinnemoen <haavard.skinnemoen@atmel.com>
Signed-off-by: Pierre Ossman <drzeus@drzeus.cx>
2008-06-30 10:35:03 -06:00
|
|
|
static irqreturn_t atmci_interrupt(int irq, void *dev_id)
|
|
|
|
{
|
atmel-mci: support multiple mmc slots
The Atmel MCI controller can drive multiple cards through separate sets
of pins, but only one at a time. This patch adds support for
multiplexing access to the controller so that multiple card slots can be
used as if they were hooked up to separate mmc controllers.
The atmel-mci driver registers each slot as a separate mmc_host. Both
access the same common controller state, but they also have some state
on their own for card detection/write protect handling, and separate
shadows of the MR and SDCR registers.
When one of the slots receives a request from the mmc core, the common
controller state is checked. If it's idle, the request is submitted
immediately. If not, the request is added to a queue. When a request is
done, the queue is checked and if there is a queued request, it is
submitted before the completion callback is called.
This patch also includes a few cleanups and fixes, including a locking
overhaul. I had to change the locking extensively in any case, so I
might as well try to get it right. The driver no longer takes any
irq-safe locks, which may or may not improve the overall system
performance.
This patch also adds a bit of documentation of the internal data
structures.
Signed-off-by: Haavard Skinnemoen <haavard.skinnemoen@atmel.com>
2008-09-17 12:53:55 -06:00
|
|
|
struct atmel_mci *host = dev_id;
|
atmel-mci: Driver for Atmel on-chip MMC controllers
This is a driver for the MMC controller on the AP7000 chips from
Atmel. It should in theory work on AT91 systems too with some
tweaking, but since the DMA interface is quite different, it's not
entirely clear if it's worth merging this with the at91_mci driver.
This driver has been around for a while in BSPs and kernel sources
provided by Atmel, but this particular version uses the generic DMA
Engine framework (with the slave extensions) instead of an
avr32-only DMA controller framework.
This driver can also use PIO transfers when no DMA channels are
available, and for transfers where using DMA may be difficult or
impractical for some reason (e.g. the DMA setup overhead is usually
not worth it for very short transfers, and badly aligned buffers or
lengths are difficult to handle.)
Currently, the driver only support PIO transfers. DMA support has been
split out to a separate patch to hopefully make it easier to review.
The driver has been tested using mmc-block and ext3fs on several SD,
SDHC and MMC+ cards. Reads and writes work fine, with read transfer
rates up to 3.5 MiB/s on fast cards with debugging disabled.
The driver has also been tested using the mmc_test module on the same
cards. All tests except 7, 9, 15 and 17 succeed. The first two are
unsupported by all the cards I have, so I don't know if the driver
handles this correctly. The last two fail because the hardware flags a
Data CRC Error instead of a Data Timeout error. I'm not sure how to deal
with that.
Documentation for this controller can be found in many data sheets from
Atmel, including the AT32AP7000 data sheet which can be found here:
http://www.atmel.com/dyn/products/datasheets.asp?family_id=682
Signed-off-by: Haavard Skinnemoen <haavard.skinnemoen@atmel.com>
Signed-off-by: Pierre Ossman <drzeus@drzeus.cx>
2008-06-30 10:35:03 -06:00
|
|
|
u32 status, mask, pending;
|
|
|
|
unsigned int pass_count = 0;
|
|
|
|
|
|
|
|
do {
|
2011-08-11 09:25:42 -06:00
|
|
|
status = atmci_readl(host, ATMCI_SR);
|
|
|
|
mask = atmci_readl(host, ATMCI_IMR);
|
atmel-mci: Driver for Atmel on-chip MMC controllers
This is a driver for the MMC controller on the AP7000 chips from
Atmel. It should in theory work on AT91 systems too with some
tweaking, but since the DMA interface is quite different, it's not
entirely clear if it's worth merging this with the at91_mci driver.
This driver has been around for a while in BSPs and kernel sources
provided by Atmel, but this particular version uses the generic DMA
Engine framework (with the slave extensions) instead of an
avr32-only DMA controller framework.
This driver can also use PIO transfers when no DMA channels are
available, and for transfers where using DMA may be difficult or
impractical for some reason (e.g. the DMA setup overhead is usually
not worth it for very short transfers, and badly aligned buffers or
lengths are difficult to handle.)
Currently, the driver only support PIO transfers. DMA support has been
split out to a separate patch to hopefully make it easier to review.
The driver has been tested using mmc-block and ext3fs on several SD,
SDHC and MMC+ cards. Reads and writes work fine, with read transfer
rates up to 3.5 MiB/s on fast cards with debugging disabled.
The driver has also been tested using the mmc_test module on the same
cards. All tests except 7, 9, 15 and 17 succeed. The first two are
unsupported by all the cards I have, so I don't know if the driver
handles this correctly. The last two fail because the hardware flags a
Data CRC Error instead of a Data Timeout error. I'm not sure how to deal
with that.
Documentation for this controller can be found in many data sheets from
Atmel, including the AT32AP7000 data sheet which can be found here:
http://www.atmel.com/dyn/products/datasheets.asp?family_id=682
Signed-off-by: Haavard Skinnemoen <haavard.skinnemoen@atmel.com>
Signed-off-by: Pierre Ossman <drzeus@drzeus.cx>
2008-06-30 10:35:03 -06:00
|
|
|
pending = status & mask;
|
|
|
|
if (!pending)
|
|
|
|
break;
|
|
|
|
|
|
|
|
if (pending & ATMCI_DATA_ERROR_FLAGS) {
|
2012-05-16 07:26:01 -06:00
|
|
|
dev_dbg(&host->pdev->dev, "IRQ: data error\n");
|
2011-08-11 09:25:42 -06:00
|
|
|
atmci_writel(host, ATMCI_IDR, ATMCI_DATA_ERROR_FLAGS
|
2012-05-16 07:25:59 -06:00
|
|
|
| ATMCI_RXRDY | ATMCI_TXRDY
|
|
|
|
| ATMCI_ENDRX | ATMCI_ENDTX
|
|
|
|
| ATMCI_RXBUFF | ATMCI_TXBUFE);
|
atmel-mci: support multiple mmc slots
The Atmel MCI controller can drive multiple cards through separate sets
of pins, but only one at a time. This patch adds support for
multiplexing access to the controller so that multiple card slots can be
used as if they were hooked up to separate mmc controllers.
The atmel-mci driver registers each slot as a separate mmc_host. Both
access the same common controller state, but they also have some state
on their own for card detection/write protect handling, and separate
shadows of the MR and SDCR registers.
When one of the slots receives a request from the mmc core, the common
controller state is checked. If it's idle, the request is submitted
immediately. If not, the request is added to a queue. When a request is
done, the queue is checked and if there is a queued request, it is
submitted before the completion callback is called.
This patch also includes a few cleanups and fixes, including a locking
overhaul. I had to change the locking extensively in any case, so I
might as well try to get it right. The driver no longer takes any
irq-safe locks, which may or may not improve the overall system
performance.
This patch also adds a bit of documentation of the internal data
structures.
Signed-off-by: Haavard Skinnemoen <haavard.skinnemoen@atmel.com>
2008-09-17 12:53:55 -06:00
|
|
|
|
atmel-mci: Driver for Atmel on-chip MMC controllers
This is a driver for the MMC controller on the AP7000 chips from
Atmel. It should in theory work on AT91 systems too with some
tweaking, but since the DMA interface is quite different, it's not
entirely clear if it's worth merging this with the at91_mci driver.
This driver has been around for a while in BSPs and kernel sources
provided by Atmel, but this particular version uses the generic DMA
Engine framework (with the slave extensions) instead of an
avr32-only DMA controller framework.
This driver can also use PIO transfers when no DMA channels are
available, and for transfers where using DMA may be difficult or
impractical for some reason (e.g. the DMA setup overhead is usually
not worth it for very short transfers, and badly aligned buffers or
lengths are difficult to handle.)
Currently, the driver only support PIO transfers. DMA support has been
split out to a separate patch to hopefully make it easier to review.
The driver has been tested using mmc-block and ext3fs on several SD,
SDHC and MMC+ cards. Reads and writes work fine, with read transfer
rates up to 3.5 MiB/s on fast cards with debugging disabled.
The driver has also been tested using the mmc_test module on the same
cards. All tests except 7, 9, 15 and 17 succeed. The first two are
unsupported by all the cards I have, so I don't know if the driver
handles this correctly. The last two fail because the hardware flags a
Data CRC Error instead of a Data Timeout error. I'm not sure how to deal
with that.
Documentation for this controller can be found in many data sheets from
Atmel, including the AT32AP7000 data sheet which can be found here:
http://www.atmel.com/dyn/products/datasheets.asp?family_id=682
Signed-off-by: Haavard Skinnemoen <haavard.skinnemoen@atmel.com>
Signed-off-by: Pierre Ossman <drzeus@drzeus.cx>
2008-06-30 10:35:03 -06:00
|
|
|
host->data_status = status;
|
2012-05-16 07:26:01 -06:00
|
|
|
dev_dbg(&host->pdev->dev, "set pending data error\n");
|
atmel-mci: support multiple mmc slots
The Atmel MCI controller can drive multiple cards through separate sets
of pins, but only one at a time. This patch adds support for
multiplexing access to the controller so that multiple card slots can be
used as if they were hooked up to separate mmc controllers.
The atmel-mci driver registers each slot as a separate mmc_host. Both
access the same common controller state, but they also have some state
on their own for card detection/write protect handling, and separate
shadows of the MR and SDCR registers.
When one of the slots receives a request from the mmc core, the common
controller state is checked. If it's idle, the request is submitted
immediately. If not, the request is added to a queue. When a request is
done, the queue is checked and if there is a queued request, it is
submitted before the completion callback is called.
This patch also includes a few cleanups and fixes, including a locking
overhaul. I had to change the locking extensively in any case, so I
might as well try to get it right. The driver no longer takes any
irq-safe locks, which may or may not improve the overall system
performance.
This patch also adds a bit of documentation of the internal data
structures.
Signed-off-by: Haavard Skinnemoen <haavard.skinnemoen@atmel.com>
2008-09-17 12:53:55 -06:00
|
|
|
smp_wmb();
|
atmel-mci: Driver for Atmel on-chip MMC controllers
This is a driver for the MMC controller on the AP7000 chips from
Atmel. It should in theory work on AT91 systems too with some
tweaking, but since the DMA interface is quite different, it's not
entirely clear if it's worth merging this with the at91_mci driver.
This driver has been around for a while in BSPs and kernel sources
provided by Atmel, but this particular version uses the generic DMA
Engine framework (with the slave extensions) instead of an
avr32-only DMA controller framework.
This driver can also use PIO transfers when no DMA channels are
available, and for transfers where using DMA may be difficult or
impractical for some reason (e.g. the DMA setup overhead is usually
not worth it for very short transfers, and badly aligned buffers or
lengths are difficult to handle.)
Currently, the driver only support PIO transfers. DMA support has been
split out to a separate patch to hopefully make it easier to review.
The driver has been tested using mmc-block and ext3fs on several SD,
SDHC and MMC+ cards. Reads and writes work fine, with read transfer
rates up to 3.5 MiB/s on fast cards with debugging disabled.
The driver has also been tested using the mmc_test module on the same
cards. All tests except 7, 9, 15 and 17 succeed. The first two are
unsupported by all the cards I have, so I don't know if the driver
handles this correctly. The last two fail because the hardware flags a
Data CRC Error instead of a Data Timeout error. I'm not sure how to deal
with that.
Documentation for this controller can be found in many data sheets from
Atmel, including the AT32AP7000 data sheet which can be found here:
http://www.atmel.com/dyn/products/datasheets.asp?family_id=682
Signed-off-by: Haavard Skinnemoen <haavard.skinnemoen@atmel.com>
Signed-off-by: Pierre Ossman <drzeus@drzeus.cx>
2008-06-30 10:35:03 -06:00
|
|
|
atmci_set_pending(host, EVENT_DATA_ERROR);
|
|
|
|
tasklet_schedule(&host->tasklet);
|
|
|
|
}
|
2011-08-11 09:25:44 -06:00
|
|
|
|
|
|
|
if (pending & ATMCI_TXBUFE) {
|
2012-05-16 07:26:01 -06:00
|
|
|
dev_dbg(&host->pdev->dev, "IRQ: tx buffer empty\n");
|
2011-08-11 09:25:44 -06:00
|
|
|
atmci_writel(host, ATMCI_IDR, ATMCI_TXBUFE);
|
2011-08-11 09:25:48 -06:00
|
|
|
atmci_writel(host, ATMCI_IDR, ATMCI_ENDTX);
|
2011-08-11 09:25:44 -06:00
|
|
|
/*
|
|
|
|
* We can receive this interruption before having configured
|
|
|
|
* the second pdc buffer, so we need to reconfigure first and
|
|
|
|
* second buffers again
|
|
|
|
*/
|
|
|
|
if (host->data_size) {
|
|
|
|
atmci_pdc_set_both_buf(host, XFER_TRANSMIT);
|
2011-08-11 09:25:48 -06:00
|
|
|
atmci_writel(host, ATMCI_IER, ATMCI_ENDTX);
|
2011-08-11 09:25:44 -06:00
|
|
|
atmci_writel(host, ATMCI_IER, ATMCI_TXBUFE);
|
|
|
|
} else {
|
|
|
|
atmci_pdc_complete(host);
|
|
|
|
}
|
2011-08-11 09:25:48 -06:00
|
|
|
} else if (pending & ATMCI_ENDTX) {
|
2012-05-16 07:26:01 -06:00
|
|
|
dev_dbg(&host->pdev->dev, "IRQ: end of tx buffer\n");
|
2011-08-11 09:25:48 -06:00
|
|
|
atmci_writel(host, ATMCI_IDR, ATMCI_ENDTX);
|
2011-08-11 09:25:44 -06:00
|
|
|
|
|
|
|
if (host->data_size) {
|
|
|
|
atmci_pdc_set_single_buf(host,
|
2011-08-11 09:25:48 -06:00
|
|
|
XFER_TRANSMIT, PDC_SECOND_BUF);
|
|
|
|
atmci_writel(host, ATMCI_IER, ATMCI_ENDTX);
|
2011-08-11 09:25:44 -06:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
if (pending & ATMCI_RXBUFF) {
|
2012-05-16 07:26:01 -06:00
|
|
|
dev_dbg(&host->pdev->dev, "IRQ: rx buffer full\n");
|
2011-08-11 09:25:44 -06:00
|
|
|
atmci_writel(host, ATMCI_IDR, ATMCI_RXBUFF);
|
2011-08-11 09:25:48 -06:00
|
|
|
atmci_writel(host, ATMCI_IDR, ATMCI_ENDRX);
|
2011-08-11 09:25:44 -06:00
|
|
|
/*
|
|
|
|
* We can receive this interruption before having configured
|
|
|
|
* the second pdc buffer, so we need to reconfigure first and
|
|
|
|
* second buffers again
|
|
|
|
*/
|
|
|
|
if (host->data_size) {
|
|
|
|
atmci_pdc_set_both_buf(host, XFER_RECEIVE);
|
2011-08-11 09:25:48 -06:00
|
|
|
atmci_writel(host, ATMCI_IER, ATMCI_ENDRX);
|
2011-08-11 09:25:44 -06:00
|
|
|
atmci_writel(host, ATMCI_IER, ATMCI_RXBUFF);
|
|
|
|
} else {
|
|
|
|
atmci_pdc_complete(host);
|
|
|
|
}
|
2011-08-11 09:25:48 -06:00
|
|
|
} else if (pending & ATMCI_ENDRX) {
|
2012-05-16 07:26:01 -06:00
|
|
|
dev_dbg(&host->pdev->dev, "IRQ: end of rx buffer\n");
|
2011-08-11 09:25:48 -06:00
|
|
|
atmci_writel(host, ATMCI_IDR, ATMCI_ENDRX);
|
|
|
|
|
|
|
|
if (host->data_size) {
|
|
|
|
atmci_pdc_set_single_buf(host,
|
|
|
|
XFER_RECEIVE, PDC_SECOND_BUF);
|
|
|
|
atmci_writel(host, ATMCI_IER, ATMCI_ENDRX);
|
|
|
|
}
|
2011-08-11 09:25:44 -06:00
|
|
|
}
|
|
|
|
|
2012-05-16 07:25:59 -06:00
|
|
|
/*
|
|
|
|
* First mci IPs, so mainly the ones having pdc, have some
|
|
|
|
* issues with the notbusy signal. You can't get it after
|
|
|
|
* data transmission if you have not sent a stop command.
|
|
|
|
* The appropriate workaround is to use the BLKE signal.
|
|
|
|
*/
|
|
|
|
if (pending & ATMCI_BLKE) {
|
2012-05-16 07:26:01 -06:00
|
|
|
dev_dbg(&host->pdev->dev, "IRQ: blke\n");
|
2012-05-16 07:25:59 -06:00
|
|
|
atmci_writel(host, ATMCI_IDR, ATMCI_BLKE);
|
|
|
|
smp_wmb();
|
2012-05-16 07:26:01 -06:00
|
|
|
dev_dbg(&host->pdev->dev, "set pending notbusy\n");
|
2012-05-16 07:25:59 -06:00
|
|
|
atmci_set_pending(host, EVENT_NOTBUSY);
|
|
|
|
tasklet_schedule(&host->tasklet);
|
|
|
|
}
|
2011-08-11 09:25:48 -06:00
|
|
|
|
2011-08-11 09:25:41 -06:00
|
|
|
if (pending & ATMCI_NOTBUSY) {
|
2012-05-16 07:26:01 -06:00
|
|
|
dev_dbg(&host->pdev->dev, "IRQ: not_busy\n");
|
2012-05-16 07:25:59 -06:00
|
|
|
atmci_writel(host, ATMCI_IDR, ATMCI_NOTBUSY);
|
atmel-mci: support multiple mmc slots
The Atmel MCI controller can drive multiple cards through separate sets
of pins, but only one at a time. This patch adds support for
multiplexing access to the controller so that multiple card slots can be
used as if they were hooked up to separate mmc controllers.
The atmel-mci driver registers each slot as a separate mmc_host. Both
access the same common controller state, but they also have some state
on their own for card detection/write protect handling, and separate
shadows of the MR and SDCR registers.
When one of the slots receives a request from the mmc core, the common
controller state is checked. If it's idle, the request is submitted
immediately. If not, the request is added to a queue. When a request is
done, the queue is checked and if there is a queued request, it is
submitted before the completion callback is called.
This patch also includes a few cleanups and fixes, including a locking
overhaul. I had to change the locking extensively in any case, so I
might as well try to get it right. The driver no longer takes any
irq-safe locks, which may or may not improve the overall system
performance.
This patch also adds a bit of documentation of the internal data
structures.
Signed-off-by: Haavard Skinnemoen <haavard.skinnemoen@atmel.com>
2008-09-17 12:53:55 -06:00
|
|
|
smp_wmb();
|
2012-05-16 07:26:01 -06:00
|
|
|
dev_dbg(&host->pdev->dev, "set pending notbusy\n");
|
2012-05-16 07:25:59 -06:00
|
|
|
atmci_set_pending(host, EVENT_NOTBUSY);
|
atmel-mci: Driver for Atmel on-chip MMC controllers
This is a driver for the MMC controller on the AP7000 chips from
Atmel. It should in theory work on AT91 systems too with some
tweaking, but since the DMA interface is quite different, it's not
entirely clear if it's worth merging this with the at91_mci driver.
This driver has been around for a while in BSPs and kernel sources
provided by Atmel, but this particular version uses the generic DMA
Engine framework (with the slave extensions) instead of an
avr32-only DMA controller framework.
This driver can also use PIO transfers when no DMA channels are
available, and for transfers where using DMA may be difficult or
impractical for some reason (e.g. the DMA setup overhead is usually
not worth it for very short transfers, and badly aligned buffers or
lengths are difficult to handle.)
Currently, the driver only support PIO transfers. DMA support has been
split out to a separate patch to hopefully make it easier to review.
The driver has been tested using mmc-block and ext3fs on several SD,
SDHC and MMC+ cards. Reads and writes work fine, with read transfer
rates up to 3.5 MiB/s on fast cards with debugging disabled.
The driver has also been tested using the mmc_test module on the same
cards. All tests except 7, 9, 15 and 17 succeed. The first two are
unsupported by all the cards I have, so I don't know if the driver
handles this correctly. The last two fail because the hardware flags a
Data CRC Error instead of a Data Timeout error. I'm not sure how to deal
with that.
Documentation for this controller can be found in many data sheets from
Atmel, including the AT32AP7000 data sheet which can be found here:
http://www.atmel.com/dyn/products/datasheets.asp?family_id=682
Signed-off-by: Haavard Skinnemoen <haavard.skinnemoen@atmel.com>
Signed-off-by: Pierre Ossman <drzeus@drzeus.cx>
2008-06-30 10:35:03 -06:00
|
|
|
tasklet_schedule(&host->tasklet);
|
|
|
|
}
|
2012-05-16 07:25:59 -06:00
|
|
|
|
2011-08-11 09:25:41 -06:00
|
|
|
if (pending & ATMCI_RXRDY)
|
atmel-mci: Driver for Atmel on-chip MMC controllers
This is a driver for the MMC controller on the AP7000 chips from
Atmel. It should in theory work on AT91 systems too with some
tweaking, but since the DMA interface is quite different, it's not
entirely clear if it's worth merging this with the at91_mci driver.
This driver has been around for a while in BSPs and kernel sources
provided by Atmel, but this particular version uses the generic DMA
Engine framework (with the slave extensions) instead of an
avr32-only DMA controller framework.
This driver can also use PIO transfers when no DMA channels are
available, and for transfers where using DMA may be difficult or
impractical for some reason (e.g. the DMA setup overhead is usually
not worth it for very short transfers, and badly aligned buffers or
lengths are difficult to handle.)
Currently, the driver only support PIO transfers. DMA support has been
split out to a separate patch to hopefully make it easier to review.
The driver has been tested using mmc-block and ext3fs on several SD,
SDHC and MMC+ cards. Reads and writes work fine, with read transfer
rates up to 3.5 MiB/s on fast cards with debugging disabled.
The driver has also been tested using the mmc_test module on the same
cards. All tests except 7, 9, 15 and 17 succeed. The first two are
unsupported by all the cards I have, so I don't know if the driver
handles this correctly. The last two fail because the hardware flags a
Data CRC Error instead of a Data Timeout error. I'm not sure how to deal
with that.
Documentation for this controller can be found in many data sheets from
Atmel, including the AT32AP7000 data sheet which can be found here:
http://www.atmel.com/dyn/products/datasheets.asp?family_id=682
Signed-off-by: Haavard Skinnemoen <haavard.skinnemoen@atmel.com>
Signed-off-by: Pierre Ossman <drzeus@drzeus.cx>
2008-06-30 10:35:03 -06:00
|
|
|
atmci_read_data_pio(host);
|
2011-08-11 09:25:41 -06:00
|
|
|
if (pending & ATMCI_TXRDY)
|
atmel-mci: Driver for Atmel on-chip MMC controllers
This is a driver for the MMC controller on the AP7000 chips from
Atmel. It should in theory work on AT91 systems too with some
tweaking, but since the DMA interface is quite different, it's not
entirely clear if it's worth merging this with the at91_mci driver.
This driver has been around for a while in BSPs and kernel sources
provided by Atmel, but this particular version uses the generic DMA
Engine framework (with the slave extensions) instead of an
avr32-only DMA controller framework.
This driver can also use PIO transfers when no DMA channels are
available, and for transfers where using DMA may be difficult or
impractical for some reason (e.g. the DMA setup overhead is usually
not worth it for very short transfers, and badly aligned buffers or
lengths are difficult to handle.)
Currently, the driver only support PIO transfers. DMA support has been
split out to a separate patch to hopefully make it easier to review.
The driver has been tested using mmc-block and ext3fs on several SD,
SDHC and MMC+ cards. Reads and writes work fine, with read transfer
rates up to 3.5 MiB/s on fast cards with debugging disabled.
The driver has also been tested using the mmc_test module on the same
cards. All tests except 7, 9, 15 and 17 succeed. The first two are
unsupported by all the cards I have, so I don't know if the driver
handles this correctly. The last two fail because the hardware flags a
Data CRC Error instead of a Data Timeout error. I'm not sure how to deal
with that.
Documentation for this controller can be found in many data sheets from
Atmel, including the AT32AP7000 data sheet which can be found here:
http://www.atmel.com/dyn/products/datasheets.asp?family_id=682
Signed-off-by: Haavard Skinnemoen <haavard.skinnemoen@atmel.com>
Signed-off-by: Pierre Ossman <drzeus@drzeus.cx>
2008-06-30 10:35:03 -06:00
|
|
|
atmci_write_data_pio(host);
|
|
|
|
|
2012-05-16 07:25:59 -06:00
|
|
|
if (pending & ATMCI_CMDRDY) {
|
2012-05-16 07:26:01 -06:00
|
|
|
dev_dbg(&host->pdev->dev, "IRQ: cmd ready\n");
|
2012-05-16 07:25:59 -06:00
|
|
|
atmci_writel(host, ATMCI_IDR, ATMCI_CMDRDY);
|
|
|
|
host->cmd_status = status;
|
|
|
|
smp_wmb();
|
2012-05-16 07:26:01 -06:00
|
|
|
dev_dbg(&host->pdev->dev, "set pending cmd rdy\n");
|
2012-05-16 07:25:59 -06:00
|
|
|
atmci_set_pending(host, EVENT_CMD_RDY);
|
|
|
|
tasklet_schedule(&host->tasklet);
|
|
|
|
}
|
2010-05-26 15:42:01 -06:00
|
|
|
|
2011-08-11 09:25:41 -06:00
|
|
|
if (pending & (ATMCI_SDIOIRQA | ATMCI_SDIOIRQB))
|
2010-05-26 15:42:01 -06:00
|
|
|
atmci_sdio_interrupt(host, status);
|
|
|
|
|
atmel-mci: Driver for Atmel on-chip MMC controllers
This is a driver for the MMC controller on the AP7000 chips from
Atmel. It should in theory work on AT91 systems too with some
tweaking, but since the DMA interface is quite different, it's not
entirely clear if it's worth merging this with the at91_mci driver.
This driver has been around for a while in BSPs and kernel sources
provided by Atmel, but this particular version uses the generic DMA
Engine framework (with the slave extensions) instead of an
avr32-only DMA controller framework.
This driver can also use PIO transfers when no DMA channels are
available, and for transfers where using DMA may be difficult or
impractical for some reason (e.g. the DMA setup overhead is usually
not worth it for very short transfers, and badly aligned buffers or
lengths are difficult to handle.)
Currently, the driver only support PIO transfers. DMA support has been
split out to a separate patch to hopefully make it easier to review.
The driver has been tested using mmc-block and ext3fs on several SD,
SDHC and MMC+ cards. Reads and writes work fine, with read transfer
rates up to 3.5 MiB/s on fast cards with debugging disabled.
The driver has also been tested using the mmc_test module on the same
cards. All tests except 7, 9, 15 and 17 succeed. The first two are
unsupported by all the cards I have, so I don't know if the driver
handles this correctly. The last two fail because the hardware flags a
Data CRC Error instead of a Data Timeout error. I'm not sure how to deal
with that.
Documentation for this controller can be found in many data sheets from
Atmel, including the AT32AP7000 data sheet which can be found here:
http://www.atmel.com/dyn/products/datasheets.asp?family_id=682
Signed-off-by: Haavard Skinnemoen <haavard.skinnemoen@atmel.com>
Signed-off-by: Pierre Ossman <drzeus@drzeus.cx>
2008-06-30 10:35:03 -06:00
|
|
|
} while (pass_count++ < 5);
|
|
|
|
|
|
|
|
return pass_count ? IRQ_HANDLED : IRQ_NONE;
|
|
|
|
}
|
|
|
|
|
|
|
|
static irqreturn_t atmci_detect_interrupt(int irq, void *dev_id)
|
|
|
|
{
|
atmel-mci: support multiple mmc slots
The Atmel MCI controller can drive multiple cards through separate sets
of pins, but only one at a time. This patch adds support for
multiplexing access to the controller so that multiple card slots can be
used as if they were hooked up to separate mmc controllers.
The atmel-mci driver registers each slot as a separate mmc_host. Both
access the same common controller state, but they also have some state
on their own for card detection/write protect handling, and separate
shadows of the MR and SDCR registers.
When one of the slots receives a request from the mmc core, the common
controller state is checked. If it's idle, the request is submitted
immediately. If not, the request is added to a queue. When a request is
done, the queue is checked and if there is a queued request, it is
submitted before the completion callback is called.
This patch also includes a few cleanups and fixes, including a locking
overhaul. I had to change the locking extensively in any case, so I
might as well try to get it right. The driver no longer takes any
irq-safe locks, which may or may not improve the overall system
performance.
This patch also adds a bit of documentation of the internal data
structures.
Signed-off-by: Haavard Skinnemoen <haavard.skinnemoen@atmel.com>
2008-09-17 12:53:55 -06:00
|
|
|
struct atmel_mci_slot *slot = dev_id;
|
atmel-mci: Driver for Atmel on-chip MMC controllers
This is a driver for the MMC controller on the AP7000 chips from
Atmel. It should in theory work on AT91 systems too with some
tweaking, but since the DMA interface is quite different, it's not
entirely clear if it's worth merging this with the at91_mci driver.
This driver has been around for a while in BSPs and kernel sources
provided by Atmel, but this particular version uses the generic DMA
Engine framework (with the slave extensions) instead of an
avr32-only DMA controller framework.
This driver can also use PIO transfers when no DMA channels are
available, and for transfers where using DMA may be difficult or
impractical for some reason (e.g. the DMA setup overhead is usually
not worth it for very short transfers, and badly aligned buffers or
lengths are difficult to handle.)
Currently, the driver only support PIO transfers. DMA support has been
split out to a separate patch to hopefully make it easier to review.
The driver has been tested using mmc-block and ext3fs on several SD,
SDHC and MMC+ cards. Reads and writes work fine, with read transfer
rates up to 3.5 MiB/s on fast cards with debugging disabled.
The driver has also been tested using the mmc_test module on the same
cards. All tests except 7, 9, 15 and 17 succeed. The first two are
unsupported by all the cards I have, so I don't know if the driver
handles this correctly. The last two fail because the hardware flags a
Data CRC Error instead of a Data Timeout error. I'm not sure how to deal
with that.
Documentation for this controller can be found in many data sheets from
Atmel, including the AT32AP7000 data sheet which can be found here:
http://www.atmel.com/dyn/products/datasheets.asp?family_id=682
Signed-off-by: Haavard Skinnemoen <haavard.skinnemoen@atmel.com>
Signed-off-by: Pierre Ossman <drzeus@drzeus.cx>
2008-06-30 10:35:03 -06:00
|
|
|
|
|
|
|
/*
|
|
|
|
* Disable interrupts until the pin has stabilized and check
|
|
|
|
* the state then. Use mod_timer() since we may be in the
|
|
|
|
* middle of the timer routine when this interrupt triggers.
|
|
|
|
*/
|
|
|
|
disable_irq_nosync(irq);
|
atmel-mci: support multiple mmc slots
The Atmel MCI controller can drive multiple cards through separate sets
of pins, but only one at a time. This patch adds support for
multiplexing access to the controller so that multiple card slots can be
used as if they were hooked up to separate mmc controllers.
The atmel-mci driver registers each slot as a separate mmc_host. Both
access the same common controller state, but they also have some state
on their own for card detection/write protect handling, and separate
shadows of the MR and SDCR registers.
When one of the slots receives a request from the mmc core, the common
controller state is checked. If it's idle, the request is submitted
immediately. If not, the request is added to a queue. When a request is
done, the queue is checked and if there is a queued request, it is
submitted before the completion callback is called.
This patch also includes a few cleanups and fixes, including a locking
overhaul. I had to change the locking extensively in any case, so I
might as well try to get it right. The driver no longer takes any
irq-safe locks, which may or may not improve the overall system
performance.
This patch also adds a bit of documentation of the internal data
structures.
Signed-off-by: Haavard Skinnemoen <haavard.skinnemoen@atmel.com>
2008-09-17 12:53:55 -06:00
|
|
|
mod_timer(&slot->detect_timer, jiffies + msecs_to_jiffies(20));
|
atmel-mci: Driver for Atmel on-chip MMC controllers
This is a driver for the MMC controller on the AP7000 chips from
Atmel. It should in theory work on AT91 systems too with some
tweaking, but since the DMA interface is quite different, it's not
entirely clear if it's worth merging this with the at91_mci driver.
This driver has been around for a while in BSPs and kernel sources
provided by Atmel, but this particular version uses the generic DMA
Engine framework (with the slave extensions) instead of an
avr32-only DMA controller framework.
This driver can also use PIO transfers when no DMA channels are
available, and for transfers where using DMA may be difficult or
impractical for some reason (e.g. the DMA setup overhead is usually
not worth it for very short transfers, and badly aligned buffers or
lengths are difficult to handle.)
Currently, the driver only support PIO transfers. DMA support has been
split out to a separate patch to hopefully make it easier to review.
The driver has been tested using mmc-block and ext3fs on several SD,
SDHC and MMC+ cards. Reads and writes work fine, with read transfer
rates up to 3.5 MiB/s on fast cards with debugging disabled.
The driver has also been tested using the mmc_test module on the same
cards. All tests except 7, 9, 15 and 17 succeed. The first two are
unsupported by all the cards I have, so I don't know if the driver
handles this correctly. The last two fail because the hardware flags a
Data CRC Error instead of a Data Timeout error. I'm not sure how to deal
with that.
Documentation for this controller can be found in many data sheets from
Atmel, including the AT32AP7000 data sheet which can be found here:
http://www.atmel.com/dyn/products/datasheets.asp?family_id=682
Signed-off-by: Haavard Skinnemoen <haavard.skinnemoen@atmel.com>
Signed-off-by: Pierre Ossman <drzeus@drzeus.cx>
2008-06-30 10:35:03 -06:00
|
|
|
|
|
|
|
return IRQ_HANDLED;
|
|
|
|
}
|
|
|
|
|
2014-12-01 07:35:07 -07:00
|
|
|
static int atmci_init_slot(struct atmel_mci *host,
|
atmel-mci: support multiple mmc slots
The Atmel MCI controller can drive multiple cards through separate sets
of pins, but only one at a time. This patch adds support for
multiplexing access to the controller so that multiple card slots can be
used as if they were hooked up to separate mmc controllers.
The atmel-mci driver registers each slot as a separate mmc_host. Both
access the same common controller state, but they also have some state
on their own for card detection/write protect handling, and separate
shadows of the MR and SDCR registers.
When one of the slots receives a request from the mmc core, the common
controller state is checked. If it's idle, the request is submitted
immediately. If not, the request is added to a queue. When a request is
done, the queue is checked and if there is a queued request, it is
submitted before the completion callback is called.
This patch also includes a few cleanups and fixes, including a locking
overhaul. I had to change the locking extensively in any case, so I
might as well try to get it right. The driver no longer takes any
irq-safe locks, which may or may not improve the overall system
performance.
This patch also adds a bit of documentation of the internal data
structures.
Signed-off-by: Haavard Skinnemoen <haavard.skinnemoen@atmel.com>
2008-09-17 12:53:55 -06:00
|
|
|
struct mci_slot_pdata *slot_data, unsigned int id,
|
2010-05-26 15:42:01 -06:00
|
|
|
u32 sdc_reg, u32 sdio_irq)
|
atmel-mci: support multiple mmc slots
The Atmel MCI controller can drive multiple cards through separate sets
of pins, but only one at a time. This patch adds support for
multiplexing access to the controller so that multiple card slots can be
used as if they were hooked up to separate mmc controllers.
The atmel-mci driver registers each slot as a separate mmc_host. Both
access the same common controller state, but they also have some state
on their own for card detection/write protect handling, and separate
shadows of the MR and SDCR registers.
When one of the slots receives a request from the mmc core, the common
controller state is checked. If it's idle, the request is submitted
immediately. If not, the request is added to a queue. When a request is
done, the queue is checked and if there is a queued request, it is
submitted before the completion callback is called.
This patch also includes a few cleanups and fixes, including a locking
overhaul. I had to change the locking extensively in any case, so I
might as well try to get it right. The driver no longer takes any
irq-safe locks, which may or may not improve the overall system
performance.
This patch also adds a bit of documentation of the internal data
structures.
Signed-off-by: Haavard Skinnemoen <haavard.skinnemoen@atmel.com>
2008-09-17 12:53:55 -06:00
|
|
|
{
|
|
|
|
struct mmc_host *mmc;
|
|
|
|
struct atmel_mci_slot *slot;
|
|
|
|
|
|
|
|
mmc = mmc_alloc_host(sizeof(struct atmel_mci_slot), &host->pdev->dev);
|
|
|
|
if (!mmc)
|
|
|
|
return -ENOMEM;
|
|
|
|
|
|
|
|
slot = mmc_priv(mmc);
|
|
|
|
slot->mmc = mmc;
|
|
|
|
slot->host = host;
|
|
|
|
slot->detect_pin = slot_data->detect_pin;
|
|
|
|
slot->wp_pin = slot_data->wp_pin;
|
2009-03-31 03:16:48 -06:00
|
|
|
slot->detect_is_active_high = slot_data->detect_is_active_high;
|
atmel-mci: support multiple mmc slots
The Atmel MCI controller can drive multiple cards through separate sets
of pins, but only one at a time. This patch adds support for
multiplexing access to the controller so that multiple card slots can be
used as if they were hooked up to separate mmc controllers.
The atmel-mci driver registers each slot as a separate mmc_host. Both
access the same common controller state, but they also have some state
on their own for card detection/write protect handling, and separate
shadows of the MR and SDCR registers.
When one of the slots receives a request from the mmc core, the common
controller state is checked. If it's idle, the request is submitted
immediately. If not, the request is added to a queue. When a request is
done, the queue is checked and if there is a queued request, it is
submitted before the completion callback is called.
This patch also includes a few cleanups and fixes, including a locking
overhaul. I had to change the locking extensively in any case, so I
might as well try to get it right. The driver no longer takes any
irq-safe locks, which may or may not improve the overall system
performance.
This patch also adds a bit of documentation of the internal data
structures.
Signed-off-by: Haavard Skinnemoen <haavard.skinnemoen@atmel.com>
2008-09-17 12:53:55 -06:00
|
|
|
slot->sdc_reg = sdc_reg;
|
2010-05-26 15:42:01 -06:00
|
|
|
slot->sdio_irq = sdio_irq;
|
atmel-mci: support multiple mmc slots
The Atmel MCI controller can drive multiple cards through separate sets
of pins, but only one at a time. This patch adds support for
multiplexing access to the controller so that multiple card slots can be
used as if they were hooked up to separate mmc controllers.
The atmel-mci driver registers each slot as a separate mmc_host. Both
access the same common controller state, but they also have some state
on their own for card detection/write protect handling, and separate
shadows of the MR and SDCR registers.
When one of the slots receives a request from the mmc core, the common
controller state is checked. If it's idle, the request is submitted
immediately. If not, the request is added to a queue. When a request is
done, the queue is checked and if there is a queued request, it is
submitted before the completion callback is called.
This patch also includes a few cleanups and fixes, including a locking
overhaul. I had to change the locking extensively in any case, so I
might as well try to get it right. The driver no longer takes any
irq-safe locks, which may or may not improve the overall system
performance.
This patch also adds a bit of documentation of the internal data
structures.
Signed-off-by: Haavard Skinnemoen <haavard.skinnemoen@atmel.com>
2008-09-17 12:53:55 -06:00
|
|
|
|
2012-07-24 07:30:03 -06:00
|
|
|
dev_dbg(&mmc->class_dev,
|
|
|
|
"slot[%u]: bus_width=%u, detect_pin=%d, "
|
|
|
|
"detect_is_active_high=%s, wp_pin=%d\n",
|
|
|
|
id, slot_data->bus_width, slot_data->detect_pin,
|
|
|
|
slot_data->detect_is_active_high ? "true" : "false",
|
|
|
|
slot_data->wp_pin);
|
|
|
|
|
atmel-mci: support multiple mmc slots
The Atmel MCI controller can drive multiple cards through separate sets
of pins, but only one at a time. This patch adds support for
multiplexing access to the controller so that multiple card slots can be
used as if they were hooked up to separate mmc controllers.
The atmel-mci driver registers each slot as a separate mmc_host. Both
access the same common controller state, but they also have some state
on their own for card detection/write protect handling, and separate
shadows of the MR and SDCR registers.
When one of the slots receives a request from the mmc core, the common
controller state is checked. If it's idle, the request is submitted
immediately. If not, the request is added to a queue. When a request is
done, the queue is checked and if there is a queued request, it is
submitted before the completion callback is called.
This patch also includes a few cleanups and fixes, including a locking
overhaul. I had to change the locking extensively in any case, so I
might as well try to get it right. The driver no longer takes any
irq-safe locks, which may or may not improve the overall system
performance.
This patch also adds a bit of documentation of the internal data
structures.
Signed-off-by: Haavard Skinnemoen <haavard.skinnemoen@atmel.com>
2008-09-17 12:53:55 -06:00
|
|
|
mmc->ops = &atmci_ops;
|
|
|
|
mmc->f_min = DIV_ROUND_UP(host->bus_hz, 512);
|
|
|
|
mmc->f_max = host->bus_hz / 2;
|
|
|
|
mmc->ocr_avail = MMC_VDD_32_33 | MMC_VDD_33_34;
|
2010-05-26 15:42:01 -06:00
|
|
|
if (sdio_irq)
|
|
|
|
mmc->caps |= MMC_CAP_SDIO_IRQ;
|
2011-08-11 09:25:44 -06:00
|
|
|
if (host->caps.has_highspeed)
|
2010-05-26 15:41:59 -06:00
|
|
|
mmc->caps |= MMC_CAP_SD_HIGHSPEED;
|
2012-05-16 07:25:58 -06:00
|
|
|
/*
|
|
|
|
* Without the read/write proof capability, it is strongly suggested to
|
|
|
|
* use only one bit for data to prevent fifo underruns and overruns
|
|
|
|
* which will corrupt data.
|
|
|
|
*/
|
|
|
|
if ((slot_data->bus_width >= 4) && host->caps.has_rwproof)
|
atmel-mci: support multiple mmc slots
The Atmel MCI controller can drive multiple cards through separate sets
of pins, but only one at a time. This patch adds support for
multiplexing access to the controller so that multiple card slots can be
used as if they were hooked up to separate mmc controllers.
The atmel-mci driver registers each slot as a separate mmc_host. Both
access the same common controller state, but they also have some state
on their own for card detection/write protect handling, and separate
shadows of the MR and SDCR registers.
When one of the slots receives a request from the mmc core, the common
controller state is checked. If it's idle, the request is submitted
immediately. If not, the request is added to a queue. When a request is
done, the queue is checked and if there is a queued request, it is
submitted before the completion callback is called.
This patch also includes a few cleanups and fixes, including a locking
overhaul. I had to change the locking extensively in any case, so I
might as well try to get it right. The driver no longer takes any
irq-safe locks, which may or may not improve the overall system
performance.
This patch also adds a bit of documentation of the internal data
structures.
Signed-off-by: Haavard Skinnemoen <haavard.skinnemoen@atmel.com>
2008-09-17 12:53:55 -06:00
|
|
|
mmc->caps |= MMC_CAP_4_BIT_DATA;
|
|
|
|
|
2012-05-16 07:25:58 -06:00
|
|
|
if (atmci_get_version(host) < 0x200) {
|
|
|
|
mmc->max_segs = 256;
|
|
|
|
mmc->max_blk_size = 4095;
|
|
|
|
mmc->max_blk_count = 256;
|
|
|
|
mmc->max_req_size = mmc->max_blk_size * mmc->max_blk_count;
|
|
|
|
mmc->max_seg_size = mmc->max_blk_size * mmc->max_segs;
|
|
|
|
} else {
|
|
|
|
mmc->max_segs = 64;
|
|
|
|
mmc->max_req_size = 32768 * 512;
|
|
|
|
mmc->max_blk_size = 32768;
|
|
|
|
mmc->max_blk_count = 512;
|
|
|
|
}
|
atmel-mci: support multiple mmc slots
The Atmel MCI controller can drive multiple cards through separate sets
of pins, but only one at a time. This patch adds support for
multiplexing access to the controller so that multiple card slots can be
used as if they were hooked up to separate mmc controllers.
The atmel-mci driver registers each slot as a separate mmc_host. Both
access the same common controller state, but they also have some state
on their own for card detection/write protect handling, and separate
shadows of the MR and SDCR registers.
When one of the slots receives a request from the mmc core, the common
controller state is checked. If it's idle, the request is submitted
immediately. If not, the request is added to a queue. When a request is
done, the queue is checked and if there is a queued request, it is
submitted before the completion callback is called.
This patch also includes a few cleanups and fixes, including a locking
overhaul. I had to change the locking extensively in any case, so I
might as well try to get it right. The driver no longer takes any
irq-safe locks, which may or may not improve the overall system
performance.
This patch also adds a bit of documentation of the internal data
structures.
Signed-off-by: Haavard Skinnemoen <haavard.skinnemoen@atmel.com>
2008-09-17 12:53:55 -06:00
|
|
|
|
|
|
|
/* Assume card is present initially */
|
|
|
|
set_bit(ATMCI_CARD_PRESENT, &slot->flags);
|
|
|
|
if (gpio_is_valid(slot->detect_pin)) {
|
2014-09-23 06:51:48 -06:00
|
|
|
if (devm_gpio_request(&host->pdev->dev, slot->detect_pin,
|
|
|
|
"mmc_detect")) {
|
atmel-mci: support multiple mmc slots
The Atmel MCI controller can drive multiple cards through separate sets
of pins, but only one at a time. This patch adds support for
multiplexing access to the controller so that multiple card slots can be
used as if they were hooked up to separate mmc controllers.
The atmel-mci driver registers each slot as a separate mmc_host. Both
access the same common controller state, but they also have some state
on their own for card detection/write protect handling, and separate
shadows of the MR and SDCR registers.
When one of the slots receives a request from the mmc core, the common
controller state is checked. If it's idle, the request is submitted
immediately. If not, the request is added to a queue. When a request is
done, the queue is checked and if there is a queued request, it is
submitted before the completion callback is called.
This patch also includes a few cleanups and fixes, including a locking
overhaul. I had to change the locking extensively in any case, so I
might as well try to get it right. The driver no longer takes any
irq-safe locks, which may or may not improve the overall system
performance.
This patch also adds a bit of documentation of the internal data
structures.
Signed-off-by: Haavard Skinnemoen <haavard.skinnemoen@atmel.com>
2008-09-17 12:53:55 -06:00
|
|
|
dev_dbg(&mmc->class_dev, "no detect pin available\n");
|
|
|
|
slot->detect_pin = -EBUSY;
|
2009-03-31 03:16:48 -06:00
|
|
|
} else if (gpio_get_value(slot->detect_pin) ^
|
|
|
|
slot->detect_is_active_high) {
|
atmel-mci: support multiple mmc slots
The Atmel MCI controller can drive multiple cards through separate sets
of pins, but only one at a time. This patch adds support for
multiplexing access to the controller so that multiple card slots can be
used as if they were hooked up to separate mmc controllers.
The atmel-mci driver registers each slot as a separate mmc_host. Both
access the same common controller state, but they also have some state
on their own for card detection/write protect handling, and separate
shadows of the MR and SDCR registers.
When one of the slots receives a request from the mmc core, the common
controller state is checked. If it's idle, the request is submitted
immediately. If not, the request is added to a queue. When a request is
done, the queue is checked and if there is a queued request, it is
submitted before the completion callback is called.
This patch also includes a few cleanups and fixes, including a locking
overhaul. I had to change the locking extensively in any case, so I
might as well try to get it right. The driver no longer takes any
irq-safe locks, which may or may not improve the overall system
performance.
This patch also adds a bit of documentation of the internal data
structures.
Signed-off-by: Haavard Skinnemoen <haavard.skinnemoen@atmel.com>
2008-09-17 12:53:55 -06:00
|
|
|
clear_bit(ATMCI_CARD_PRESENT, &slot->flags);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2014-11-03 04:12:59 -07:00
|
|
|
if (!gpio_is_valid(slot->detect_pin)) {
|
|
|
|
if (slot_data->non_removable)
|
|
|
|
mmc->caps |= MMC_CAP_NONREMOVABLE;
|
|
|
|
else
|
|
|
|
mmc->caps |= MMC_CAP_NEEDS_POLL;
|
|
|
|
}
|
atmel-mci: support multiple mmc slots
The Atmel MCI controller can drive multiple cards through separate sets
of pins, but only one at a time. This patch adds support for
multiplexing access to the controller so that multiple card slots can be
used as if they were hooked up to separate mmc controllers.
The atmel-mci driver registers each slot as a separate mmc_host. Both
access the same common controller state, but they also have some state
on their own for card detection/write protect handling, and separate
shadows of the MR and SDCR registers.
When one of the slots receives a request from the mmc core, the common
controller state is checked. If it's idle, the request is submitted
immediately. If not, the request is added to a queue. When a request is
done, the queue is checked and if there is a queued request, it is
submitted before the completion callback is called.
This patch also includes a few cleanups and fixes, including a locking
overhaul. I had to change the locking extensively in any case, so I
might as well try to get it right. The driver no longer takes any
irq-safe locks, which may or may not improve the overall system
performance.
This patch also adds a bit of documentation of the internal data
structures.
Signed-off-by: Haavard Skinnemoen <haavard.skinnemoen@atmel.com>
2008-09-17 12:53:55 -06:00
|
|
|
|
|
|
|
if (gpio_is_valid(slot->wp_pin)) {
|
2014-09-23 06:51:48 -06:00
|
|
|
if (devm_gpio_request(&host->pdev->dev, slot->wp_pin,
|
|
|
|
"mmc_wp")) {
|
atmel-mci: support multiple mmc slots
The Atmel MCI controller can drive multiple cards through separate sets
of pins, but only one at a time. This patch adds support for
multiplexing access to the controller so that multiple card slots can be
used as if they were hooked up to separate mmc controllers.
The atmel-mci driver registers each slot as a separate mmc_host. Both
access the same common controller state, but they also have some state
on their own for card detection/write protect handling, and separate
shadows of the MR and SDCR registers.
When one of the slots receives a request from the mmc core, the common
controller state is checked. If it's idle, the request is submitted
immediately. If not, the request is added to a queue. When a request is
done, the queue is checked and if there is a queued request, it is
submitted before the completion callback is called.
This patch also includes a few cleanups and fixes, including a locking
overhaul. I had to change the locking extensively in any case, so I
might as well try to get it right. The driver no longer takes any
irq-safe locks, which may or may not improve the overall system
performance.
This patch also adds a bit of documentation of the internal data
structures.
Signed-off-by: Haavard Skinnemoen <haavard.skinnemoen@atmel.com>
2008-09-17 12:53:55 -06:00
|
|
|
dev_dbg(&mmc->class_dev, "no WP pin available\n");
|
|
|
|
slot->wp_pin = -EBUSY;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
host->slot[id] = slot;
|
2013-10-17 04:46:48 -06:00
|
|
|
mmc_regulator_get_supply(mmc);
|
atmel-mci: support multiple mmc slots
The Atmel MCI controller can drive multiple cards through separate sets
of pins, but only one at a time. This patch adds support for
multiplexing access to the controller so that multiple card slots can be
used as if they were hooked up to separate mmc controllers.
The atmel-mci driver registers each slot as a separate mmc_host. Both
access the same common controller state, but they also have some state
on their own for card detection/write protect handling, and separate
shadows of the MR and SDCR registers.
When one of the slots receives a request from the mmc core, the common
controller state is checked. If it's idle, the request is submitted
immediately. If not, the request is added to a queue. When a request is
done, the queue is checked and if there is a queued request, it is
submitted before the completion callback is called.
This patch also includes a few cleanups and fixes, including a locking
overhaul. I had to change the locking extensively in any case, so I
might as well try to get it right. The driver no longer takes any
irq-safe locks, which may or may not improve the overall system
performance.
This patch also adds a bit of documentation of the internal data
structures.
Signed-off-by: Haavard Skinnemoen <haavard.skinnemoen@atmel.com>
2008-09-17 12:53:55 -06:00
|
|
|
mmc_add_host(mmc);
|
|
|
|
|
|
|
|
if (gpio_is_valid(slot->detect_pin)) {
|
|
|
|
int ret;
|
|
|
|
|
|
|
|
setup_timer(&slot->detect_timer, atmci_detect_change,
|
|
|
|
(unsigned long)slot);
|
|
|
|
|
|
|
|
ret = request_irq(gpio_to_irq(slot->detect_pin),
|
|
|
|
atmci_detect_interrupt,
|
|
|
|
IRQF_TRIGGER_FALLING | IRQF_TRIGGER_RISING,
|
|
|
|
"mmc-detect", slot);
|
|
|
|
if (ret) {
|
|
|
|
dev_dbg(&mmc->class_dev,
|
|
|
|
"could not request IRQ %d for detect pin\n",
|
|
|
|
gpio_to_irq(slot->detect_pin));
|
|
|
|
slot->detect_pin = -EBUSY;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
atmci_init_debugfs(slot);
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2014-09-26 13:34:58 -06:00
|
|
|
static void atmci_cleanup_slot(struct atmel_mci_slot *slot,
|
atmel-mci: support multiple mmc slots
The Atmel MCI controller can drive multiple cards through separate sets
of pins, but only one at a time. This patch adds support for
multiplexing access to the controller so that multiple card slots can be
used as if they were hooked up to separate mmc controllers.
The atmel-mci driver registers each slot as a separate mmc_host. Both
access the same common controller state, but they also have some state
on their own for card detection/write protect handling, and separate
shadows of the MR and SDCR registers.
When one of the slots receives a request from the mmc core, the common
controller state is checked. If it's idle, the request is submitted
immediately. If not, the request is added to a queue. When a request is
done, the queue is checked and if there is a queued request, it is
submitted before the completion callback is called.
This patch also includes a few cleanups and fixes, including a locking
overhaul. I had to change the locking extensively in any case, so I
might as well try to get it right. The driver no longer takes any
irq-safe locks, which may or may not improve the overall system
performance.
This patch also adds a bit of documentation of the internal data
structures.
Signed-off-by: Haavard Skinnemoen <haavard.skinnemoen@atmel.com>
2008-09-17 12:53:55 -06:00
|
|
|
unsigned int id)
|
|
|
|
{
|
|
|
|
/* Debugfs stuff is cleaned up by mmc core */
|
|
|
|
|
|
|
|
set_bit(ATMCI_SHUTDOWN, &slot->flags);
|
|
|
|
smp_wmb();
|
|
|
|
|
|
|
|
mmc_remove_host(slot->mmc);
|
|
|
|
|
|
|
|
if (gpio_is_valid(slot->detect_pin)) {
|
|
|
|
int pin = slot->detect_pin;
|
|
|
|
|
|
|
|
free_irq(gpio_to_irq(pin), slot);
|
|
|
|
del_timer_sync(&slot->detect_timer);
|
|
|
|
}
|
|
|
|
|
|
|
|
slot->host->slot[id] = NULL;
|
|
|
|
mmc_free_host(slot->mmc);
|
|
|
|
}
|
|
|
|
|
2014-12-01 07:35:09 -07:00
|
|
|
static int atmci_configure_dma(struct atmel_mci *host)
|
2009-12-14 19:01:30 -07:00
|
|
|
{
|
2014-12-01 07:35:09 -07:00
|
|
|
host->dma.chan = dma_request_slave_channel_reason(&host->pdev->dev,
|
|
|
|
"rxtx");
|
2016-01-09 05:45:10 -07:00
|
|
|
|
|
|
|
if (PTR_ERR(host->dma.chan) == -ENODEV) {
|
|
|
|
struct mci_platform_data *pdata = host->pdev->dev.platform_data;
|
|
|
|
dma_cap_mask_t mask;
|
|
|
|
|
2016-03-12 23:25:31 -07:00
|
|
|
if (!pdata || !pdata->dma_filter)
|
2016-01-09 05:45:10 -07:00
|
|
|
return -ENODEV;
|
|
|
|
|
|
|
|
dma_cap_zero(mask);
|
|
|
|
dma_cap_set(DMA_SLAVE, mask);
|
|
|
|
|
|
|
|
host->dma.chan = dma_request_channel(mask, pdata->dma_filter,
|
|
|
|
pdata->dma_slave);
|
|
|
|
if (!host->dma.chan)
|
|
|
|
host->dma.chan = ERR_PTR(-ENODEV);
|
|
|
|
}
|
|
|
|
|
2014-12-01 07:35:09 -07:00
|
|
|
if (IS_ERR(host->dma.chan))
|
|
|
|
return PTR_ERR(host->dma.chan);
|
|
|
|
|
|
|
|
dev_info(&host->pdev->dev, "using %s for DMA transfers\n",
|
|
|
|
dma_chan_name(host->dma.chan));
|
|
|
|
|
|
|
|
host->dma_conf.src_addr = host->mapbase + ATMCI_RDR;
|
|
|
|
host->dma_conf.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
|
|
|
|
host->dma_conf.src_maxburst = 1;
|
|
|
|
host->dma_conf.dst_addr = host->mapbase + ATMCI_TDR;
|
|
|
|
host->dma_conf.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
|
|
|
|
host->dma_conf.dst_maxburst = 1;
|
|
|
|
host->dma_conf.device_fc = false;
|
2009-12-14 19:01:30 -07:00
|
|
|
|
2014-12-01 07:35:09 -07:00
|
|
|
return 0;
|
2009-12-14 19:01:30 -07:00
|
|
|
}
|
2011-08-11 09:25:44 -06:00
|
|
|
|
|
|
|
/*
|
|
|
|
* HSMCI (High Speed MCI) module is not fully compatible with MCI module.
|
|
|
|
* HSMCI provides DMA support and a new config register but no more supports
|
|
|
|
* PDC.
|
|
|
|
*/
|
2014-12-01 07:35:07 -07:00
|
|
|
static void atmci_get_cap(struct atmel_mci *host)
|
2011-08-11 09:25:44 -06:00
|
|
|
{
|
|
|
|
unsigned int version;
|
|
|
|
|
|
|
|
version = atmci_get_version(host);
|
|
|
|
dev_info(&host->pdev->dev,
|
|
|
|
"version: 0x%x\n", version);
|
|
|
|
|
2012-08-30 10:34:38 -06:00
|
|
|
host->caps.has_dma_conf_reg = 0;
|
2012-08-30 10:34:27 -06:00
|
|
|
host->caps.has_pdc = ATMCI_PDC_CONNECTED;
|
2011-08-11 09:25:44 -06:00
|
|
|
host->caps.has_cfg_reg = 0;
|
|
|
|
host->caps.has_cstor_reg = 0;
|
|
|
|
host->caps.has_highspeed = 0;
|
|
|
|
host->caps.has_rwproof = 0;
|
2012-03-21 09:41:23 -06:00
|
|
|
host->caps.has_odd_clk_div = 0;
|
2012-05-16 07:26:00 -06:00
|
|
|
host->caps.has_bad_data_ordering = 1;
|
|
|
|
host->caps.need_reset_after_xfer = 1;
|
|
|
|
host->caps.need_blksz_mul_4 = 1;
|
2012-07-24 03:42:04 -06:00
|
|
|
host->caps.need_notbusy_for_read_ops = 0;
|
2011-08-11 09:25:44 -06:00
|
|
|
|
|
|
|
/* keep only major version number */
|
|
|
|
switch (version & 0xf00) {
|
2014-06-12 01:47:45 -06:00
|
|
|
case 0x600:
|
2011-08-11 09:25:44 -06:00
|
|
|
case 0x500:
|
2012-03-21 09:41:23 -06:00
|
|
|
host->caps.has_odd_clk_div = 1;
|
|
|
|
case 0x400:
|
|
|
|
case 0x300:
|
2012-08-30 10:34:38 -06:00
|
|
|
host->caps.has_dma_conf_reg = 1;
|
2012-03-21 09:41:23 -06:00
|
|
|
host->caps.has_pdc = 0;
|
2011-08-11 09:25:44 -06:00
|
|
|
host->caps.has_cfg_reg = 1;
|
|
|
|
host->caps.has_cstor_reg = 1;
|
|
|
|
host->caps.has_highspeed = 1;
|
2012-03-21 09:41:23 -06:00
|
|
|
case 0x200:
|
2011-08-11 09:25:44 -06:00
|
|
|
host->caps.has_rwproof = 1;
|
2012-05-16 07:26:00 -06:00
|
|
|
host->caps.need_blksz_mul_4 = 0;
|
2012-07-24 03:42:04 -06:00
|
|
|
host->caps.need_notbusy_for_read_ops = 1;
|
2012-03-21 09:41:23 -06:00
|
|
|
case 0x100:
|
2012-05-16 07:26:00 -06:00
|
|
|
host->caps.has_bad_data_ordering = 0;
|
|
|
|
host->caps.need_reset_after_xfer = 0;
|
|
|
|
case 0x0:
|
2011-08-11 09:25:44 -06:00
|
|
|
break;
|
|
|
|
default:
|
2012-03-21 09:41:23 -06:00
|
|
|
host->caps.has_pdc = 0;
|
2011-08-11 09:25:44 -06:00
|
|
|
dev_warn(&host->pdev->dev,
|
|
|
|
"Unmanaged mci version, set minimum capabilities\n");
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
}
|
2009-01-06 11:38:16 -07:00
|
|
|
|
2014-12-01 07:35:07 -07:00
|
|
|
static int atmci_probe(struct platform_device *pdev)
|
atmel-mci: Driver for Atmel on-chip MMC controllers
This is a driver for the MMC controller on the AP7000 chips from
Atmel. It should in theory work on AT91 systems too with some
tweaking, but since the DMA interface is quite different, it's not
entirely clear if it's worth merging this with the at91_mci driver.
This driver has been around for a while in BSPs and kernel sources
provided by Atmel, but this particular version uses the generic DMA
Engine framework (with the slave extensions) instead of an
avr32-only DMA controller framework.
This driver can also use PIO transfers when no DMA channels are
available, and for transfers where using DMA may be difficult or
impractical for some reason (e.g. the DMA setup overhead is usually
not worth it for very short transfers, and badly aligned buffers or
lengths are difficult to handle.)
Currently, the driver only support PIO transfers. DMA support has been
split out to a separate patch to hopefully make it easier to review.
The driver has been tested using mmc-block and ext3fs on several SD,
SDHC and MMC+ cards. Reads and writes work fine, with read transfer
rates up to 3.5 MiB/s on fast cards with debugging disabled.
The driver has also been tested using the mmc_test module on the same
cards. All tests except 7, 9, 15 and 17 succeed. The first two are
unsupported by all the cards I have, so I don't know if the driver
handles this correctly. The last two fail because the hardware flags a
Data CRC Error instead of a Data Timeout error. I'm not sure how to deal
with that.
Documentation for this controller can be found in many data sheets from
Atmel, including the AT32AP7000 data sheet which can be found here:
http://www.atmel.com/dyn/products/datasheets.asp?family_id=682
Signed-off-by: Haavard Skinnemoen <haavard.skinnemoen@atmel.com>
Signed-off-by: Pierre Ossman <drzeus@drzeus.cx>
2008-06-30 10:35:03 -06:00
|
|
|
{
|
|
|
|
struct mci_platform_data *pdata;
|
atmel-mci: support multiple mmc slots
The Atmel MCI controller can drive multiple cards through separate sets
of pins, but only one at a time. This patch adds support for
multiplexing access to the controller so that multiple card slots can be
used as if they were hooked up to separate mmc controllers.
The atmel-mci driver registers each slot as a separate mmc_host. Both
access the same common controller state, but they also have some state
on their own for card detection/write protect handling, and separate
shadows of the MR and SDCR registers.
When one of the slots receives a request from the mmc core, the common
controller state is checked. If it's idle, the request is submitted
immediately. If not, the request is added to a queue. When a request is
done, the queue is checked and if there is a queued request, it is
submitted before the completion callback is called.
This patch also includes a few cleanups and fixes, including a locking
overhaul. I had to change the locking extensively in any case, so I
might as well try to get it right. The driver no longer takes any
irq-safe locks, which may or may not improve the overall system
performance.
This patch also adds a bit of documentation of the internal data
structures.
Signed-off-by: Haavard Skinnemoen <haavard.skinnemoen@atmel.com>
2008-09-17 12:53:55 -06:00
|
|
|
struct atmel_mci *host;
|
|
|
|
struct resource *regs;
|
|
|
|
unsigned int nr_slots;
|
|
|
|
int irq;
|
2014-09-23 04:20:06 -06:00
|
|
|
int ret, i;
|
atmel-mci: Driver for Atmel on-chip MMC controllers
This is a driver for the MMC controller on the AP7000 chips from
Atmel. It should in theory work on AT91 systems too with some
tweaking, but since the DMA interface is quite different, it's not
entirely clear if it's worth merging this with the at91_mci driver.
This driver has been around for a while in BSPs and kernel sources
provided by Atmel, but this particular version uses the generic DMA
Engine framework (with the slave extensions) instead of an
avr32-only DMA controller framework.
This driver can also use PIO transfers when no DMA channels are
available, and for transfers where using DMA may be difficult or
impractical for some reason (e.g. the DMA setup overhead is usually
not worth it for very short transfers, and badly aligned buffers or
lengths are difficult to handle.)
Currently, the driver only support PIO transfers. DMA support has been
split out to a separate patch to hopefully make it easier to review.
The driver has been tested using mmc-block and ext3fs on several SD,
SDHC and MMC+ cards. Reads and writes work fine, with read transfer
rates up to 3.5 MiB/s on fast cards with debugging disabled.
The driver has also been tested using the mmc_test module on the same
cards. All tests except 7, 9, 15 and 17 succeed. The first two are
unsupported by all the cards I have, so I don't know if the driver
handles this correctly. The last two fail because the hardware flags a
Data CRC Error instead of a Data Timeout error. I'm not sure how to deal
with that.
Documentation for this controller can be found in many data sheets from
Atmel, including the AT32AP7000 data sheet which can be found here:
http://www.atmel.com/dyn/products/datasheets.asp?family_id=682
Signed-off-by: Haavard Skinnemoen <haavard.skinnemoen@atmel.com>
Signed-off-by: Pierre Ossman <drzeus@drzeus.cx>
2008-06-30 10:35:03 -06:00
|
|
|
|
|
|
|
regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
|
|
|
|
if (!regs)
|
|
|
|
return -ENXIO;
|
|
|
|
pdata = pdev->dev.platform_data;
|
2012-07-24 07:30:03 -06:00
|
|
|
if (!pdata) {
|
|
|
|
pdata = atmci_of_init(pdev);
|
|
|
|
if (IS_ERR(pdata)) {
|
|
|
|
dev_err(&pdev->dev, "platform data not available\n");
|
|
|
|
return PTR_ERR(pdata);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
atmel-mci: Driver for Atmel on-chip MMC controllers
This is a driver for the MMC controller on the AP7000 chips from
Atmel. It should in theory work on AT91 systems too with some
tweaking, but since the DMA interface is quite different, it's not
entirely clear if it's worth merging this with the at91_mci driver.
This driver has been around for a while in BSPs and kernel sources
provided by Atmel, but this particular version uses the generic DMA
Engine framework (with the slave extensions) instead of an
avr32-only DMA controller framework.
This driver can also use PIO transfers when no DMA channels are
available, and for transfers where using DMA may be difficult or
impractical for some reason (e.g. the DMA setup overhead is usually
not worth it for very short transfers, and badly aligned buffers or
lengths are difficult to handle.)
Currently, the driver only support PIO transfers. DMA support has been
split out to a separate patch to hopefully make it easier to review.
The driver has been tested using mmc-block and ext3fs on several SD,
SDHC and MMC+ cards. Reads and writes work fine, with read transfer
rates up to 3.5 MiB/s on fast cards with debugging disabled.
The driver has also been tested using the mmc_test module on the same
cards. All tests except 7, 9, 15 and 17 succeed. The first two are
unsupported by all the cards I have, so I don't know if the driver
handles this correctly. The last two fail because the hardware flags a
Data CRC Error instead of a Data Timeout error. I'm not sure how to deal
with that.
Documentation for this controller can be found in many data sheets from
Atmel, including the AT32AP7000 data sheet which can be found here:
http://www.atmel.com/dyn/products/datasheets.asp?family_id=682
Signed-off-by: Haavard Skinnemoen <haavard.skinnemoen@atmel.com>
Signed-off-by: Pierre Ossman <drzeus@drzeus.cx>
2008-06-30 10:35:03 -06:00
|
|
|
irq = platform_get_irq(pdev, 0);
|
|
|
|
if (irq < 0)
|
|
|
|
return irq;
|
|
|
|
|
2014-09-23 06:51:48 -06:00
|
|
|
host = devm_kzalloc(&pdev->dev, sizeof(*host), GFP_KERNEL);
|
atmel-mci: support multiple mmc slots
The Atmel MCI controller can drive multiple cards through separate sets
of pins, but only one at a time. This patch adds support for
multiplexing access to the controller so that multiple card slots can be
used as if they were hooked up to separate mmc controllers.
The atmel-mci driver registers each slot as a separate mmc_host. Both
access the same common controller state, but they also have some state
on their own for card detection/write protect handling, and separate
shadows of the MR and SDCR registers.
When one of the slots receives a request from the mmc core, the common
controller state is checked. If it's idle, the request is submitted
immediately. If not, the request is added to a queue. When a request is
done, the queue is checked and if there is a queued request, it is
submitted before the completion callback is called.
This patch also includes a few cleanups and fixes, including a locking
overhaul. I had to change the locking extensively in any case, so I
might as well try to get it right. The driver no longer takes any
irq-safe locks, which may or may not improve the overall system
performance.
This patch also adds a bit of documentation of the internal data
structures.
Signed-off-by: Haavard Skinnemoen <haavard.skinnemoen@atmel.com>
2008-09-17 12:53:55 -06:00
|
|
|
if (!host)
|
atmel-mci: Driver for Atmel on-chip MMC controllers
This is a driver for the MMC controller on the AP7000 chips from
Atmel. It should in theory work on AT91 systems too with some
tweaking, but since the DMA interface is quite different, it's not
entirely clear if it's worth merging this with the at91_mci driver.
This driver has been around for a while in BSPs and kernel sources
provided by Atmel, but this particular version uses the generic DMA
Engine framework (with the slave extensions) instead of an
avr32-only DMA controller framework.
This driver can also use PIO transfers when no DMA channels are
available, and for transfers where using DMA may be difficult or
impractical for some reason (e.g. the DMA setup overhead is usually
not worth it for very short transfers, and badly aligned buffers or
lengths are difficult to handle.)
Currently, the driver only support PIO transfers. DMA support has been
split out to a separate patch to hopefully make it easier to review.
The driver has been tested using mmc-block and ext3fs on several SD,
SDHC and MMC+ cards. Reads and writes work fine, with read transfer
rates up to 3.5 MiB/s on fast cards with debugging disabled.
The driver has also been tested using the mmc_test module on the same
cards. All tests except 7, 9, 15 and 17 succeed. The first two are
unsupported by all the cards I have, so I don't know if the driver
handles this correctly. The last two fail because the hardware flags a
Data CRC Error instead of a Data Timeout error. I'm not sure how to deal
with that.
Documentation for this controller can be found in many data sheets from
Atmel, including the AT32AP7000 data sheet which can be found here:
http://www.atmel.com/dyn/products/datasheets.asp?family_id=682
Signed-off-by: Haavard Skinnemoen <haavard.skinnemoen@atmel.com>
Signed-off-by: Pierre Ossman <drzeus@drzeus.cx>
2008-06-30 10:35:03 -06:00
|
|
|
return -ENOMEM;
|
|
|
|
|
|
|
|
host->pdev = pdev;
|
atmel-mci: support multiple mmc slots
The Atmel MCI controller can drive multiple cards through separate sets
of pins, but only one at a time. This patch adds support for
multiplexing access to the controller so that multiple card slots can be
used as if they were hooked up to separate mmc controllers.
The atmel-mci driver registers each slot as a separate mmc_host. Both
access the same common controller state, but they also have some state
on their own for card detection/write protect handling, and separate
shadows of the MR and SDCR registers.
When one of the slots receives a request from the mmc core, the common
controller state is checked. If it's idle, the request is submitted
immediately. If not, the request is added to a queue. When a request is
done, the queue is checked and if there is a queued request, it is
submitted before the completion callback is called.
This patch also includes a few cleanups and fixes, including a locking
overhaul. I had to change the locking extensively in any case, so I
might as well try to get it right. The driver no longer takes any
irq-safe locks, which may or may not improve the overall system
performance.
This patch also adds a bit of documentation of the internal data
structures.
Signed-off-by: Haavard Skinnemoen <haavard.skinnemoen@atmel.com>
2008-09-17 12:53:55 -06:00
|
|
|
spin_lock_init(&host->lock);
|
|
|
|
INIT_LIST_HEAD(&host->queue);
|
atmel-mci: Driver for Atmel on-chip MMC controllers
This is a driver for the MMC controller on the AP7000 chips from
Atmel. It should in theory work on AT91 systems too with some
tweaking, but since the DMA interface is quite different, it's not
entirely clear if it's worth merging this with the at91_mci driver.
This driver has been around for a while in BSPs and kernel sources
provided by Atmel, but this particular version uses the generic DMA
Engine framework (with the slave extensions) instead of an
avr32-only DMA controller framework.
This driver can also use PIO transfers when no DMA channels are
available, and for transfers where using DMA may be difficult or
impractical for some reason (e.g. the DMA setup overhead is usually
not worth it for very short transfers, and badly aligned buffers or
lengths are difficult to handle.)
Currently, the driver only support PIO transfers. DMA support has been
split out to a separate patch to hopefully make it easier to review.
The driver has been tested using mmc-block and ext3fs on several SD,
SDHC and MMC+ cards. Reads and writes work fine, with read transfer
rates up to 3.5 MiB/s on fast cards with debugging disabled.
The driver has also been tested using the mmc_test module on the same
cards. All tests except 7, 9, 15 and 17 succeed. The first two are
unsupported by all the cards I have, so I don't know if the driver
handles this correctly. The last two fail because the hardware flags a
Data CRC Error instead of a Data Timeout error. I'm not sure how to deal
with that.
Documentation for this controller can be found in many data sheets from
Atmel, including the AT32AP7000 data sheet which can be found here:
http://www.atmel.com/dyn/products/datasheets.asp?family_id=682
Signed-off-by: Haavard Skinnemoen <haavard.skinnemoen@atmel.com>
Signed-off-by: Pierre Ossman <drzeus@drzeus.cx>
2008-06-30 10:35:03 -06:00
|
|
|
|
2014-09-23 06:51:48 -06:00
|
|
|
host->mck = devm_clk_get(&pdev->dev, "mci_clk");
|
|
|
|
if (IS_ERR(host->mck))
|
|
|
|
return PTR_ERR(host->mck);
|
atmel-mci: Driver for Atmel on-chip MMC controllers
This is a driver for the MMC controller on the AP7000 chips from
Atmel. It should in theory work on AT91 systems too with some
tweaking, but since the DMA interface is quite different, it's not
entirely clear if it's worth merging this with the at91_mci driver.
This driver has been around for a while in BSPs and kernel sources
provided by Atmel, but this particular version uses the generic DMA
Engine framework (with the slave extensions) instead of an
avr32-only DMA controller framework.
This driver can also use PIO transfers when no DMA channels are
available, and for transfers where using DMA may be difficult or
impractical for some reason (e.g. the DMA setup overhead is usually
not worth it for very short transfers, and badly aligned buffers or
lengths are difficult to handle.)
Currently, the driver only support PIO transfers. DMA support has been
split out to a separate patch to hopefully make it easier to review.
The driver has been tested using mmc-block and ext3fs on several SD,
SDHC and MMC+ cards. Reads and writes work fine, with read transfer
rates up to 3.5 MiB/s on fast cards with debugging disabled.
The driver has also been tested using the mmc_test module on the same
cards. All tests except 7, 9, 15 and 17 succeed. The first two are
unsupported by all the cards I have, so I don't know if the driver
handles this correctly. The last two fail because the hardware flags a
Data CRC Error instead of a Data Timeout error. I'm not sure how to deal
with that.
Documentation for this controller can be found in many data sheets from
Atmel, including the AT32AP7000 data sheet which can be found here:
http://www.atmel.com/dyn/products/datasheets.asp?family_id=682
Signed-off-by: Haavard Skinnemoen <haavard.skinnemoen@atmel.com>
Signed-off-by: Pierre Ossman <drzeus@drzeus.cx>
2008-06-30 10:35:03 -06:00
|
|
|
|
2014-09-23 06:51:48 -06:00
|
|
|
host->regs = devm_ioremap(&pdev->dev, regs->start, resource_size(regs));
|
atmel-mci: Driver for Atmel on-chip MMC controllers
This is a driver for the MMC controller on the AP7000 chips from
Atmel. It should in theory work on AT91 systems too with some
tweaking, but since the DMA interface is quite different, it's not
entirely clear if it's worth merging this with the at91_mci driver.
This driver has been around for a while in BSPs and kernel sources
provided by Atmel, but this particular version uses the generic DMA
Engine framework (with the slave extensions) instead of an
avr32-only DMA controller framework.
This driver can also use PIO transfers when no DMA channels are
available, and for transfers where using DMA may be difficult or
impractical for some reason (e.g. the DMA setup overhead is usually
not worth it for very short transfers, and badly aligned buffers or
lengths are difficult to handle.)
Currently, the driver only support PIO transfers. DMA support has been
split out to a separate patch to hopefully make it easier to review.
The driver has been tested using mmc-block and ext3fs on several SD,
SDHC and MMC+ cards. Reads and writes work fine, with read transfer
rates up to 3.5 MiB/s on fast cards with debugging disabled.
The driver has also been tested using the mmc_test module on the same
cards. All tests except 7, 9, 15 and 17 succeed. The first two are
unsupported by all the cards I have, so I don't know if the driver
handles this correctly. The last two fail because the hardware flags a
Data CRC Error instead of a Data Timeout error. I'm not sure how to deal
with that.
Documentation for this controller can be found in many data sheets from
Atmel, including the AT32AP7000 data sheet which can be found here:
http://www.atmel.com/dyn/products/datasheets.asp?family_id=682
Signed-off-by: Haavard Skinnemoen <haavard.skinnemoen@atmel.com>
Signed-off-by: Pierre Ossman <drzeus@drzeus.cx>
2008-06-30 10:35:03 -06:00
|
|
|
if (!host->regs)
|
2014-09-23 06:51:48 -06:00
|
|
|
return -ENOMEM;
|
atmel-mci: Driver for Atmel on-chip MMC controllers
This is a driver for the MMC controller on the AP7000 chips from
Atmel. It should in theory work on AT91 systems too with some
tweaking, but since the DMA interface is quite different, it's not
entirely clear if it's worth merging this with the at91_mci driver.
This driver has been around for a while in BSPs and kernel sources
provided by Atmel, but this particular version uses the generic DMA
Engine framework (with the slave extensions) instead of an
avr32-only DMA controller framework.
This driver can also use PIO transfers when no DMA channels are
available, and for transfers where using DMA may be difficult or
impractical for some reason (e.g. the DMA setup overhead is usually
not worth it for very short transfers, and badly aligned buffers or
lengths are difficult to handle.)
Currently, the driver only support PIO transfers. DMA support has been
split out to a separate patch to hopefully make it easier to review.
The driver has been tested using mmc-block and ext3fs on several SD,
SDHC and MMC+ cards. Reads and writes work fine, with read transfer
rates up to 3.5 MiB/s on fast cards with debugging disabled.
The driver has also been tested using the mmc_test module on the same
cards. All tests except 7, 9, 15 and 17 succeed. The first two are
unsupported by all the cards I have, so I don't know if the driver
handles this correctly. The last two fail because the hardware flags a
Data CRC Error instead of a Data Timeout error. I'm not sure how to deal
with that.
Documentation for this controller can be found in many data sheets from
Atmel, including the AT32AP7000 data sheet which can be found here:
http://www.atmel.com/dyn/products/datasheets.asp?family_id=682
Signed-off-by: Haavard Skinnemoen <haavard.skinnemoen@atmel.com>
Signed-off-by: Pierre Ossman <drzeus@drzeus.cx>
2008-06-30 10:35:03 -06:00
|
|
|
|
2013-07-18 01:38:52 -06:00
|
|
|
ret = clk_prepare_enable(host->mck);
|
|
|
|
if (ret)
|
2014-09-23 06:51:48 -06:00
|
|
|
return ret;
|
|
|
|
|
2011-08-11 09:25:42 -06:00
|
|
|
atmci_writel(host, ATMCI_CR, ATMCI_CR_SWRST);
|
atmel-mci: Driver for Atmel on-chip MMC controllers
This is a driver for the MMC controller on the AP7000 chips from
Atmel. It should in theory work on AT91 systems too with some
tweaking, but since the DMA interface is quite different, it's not
entirely clear if it's worth merging this with the at91_mci driver.
This driver has been around for a while in BSPs and kernel sources
provided by Atmel, but this particular version uses the generic DMA
Engine framework (with the slave extensions) instead of an
avr32-only DMA controller framework.
This driver can also use PIO transfers when no DMA channels are
available, and for transfers where using DMA may be difficult or
impractical for some reason (e.g. the DMA setup overhead is usually
not worth it for very short transfers, and badly aligned buffers or
lengths are difficult to handle.)
Currently, the driver only support PIO transfers. DMA support has been
split out to a separate patch to hopefully make it easier to review.
The driver has been tested using mmc-block and ext3fs on several SD,
SDHC and MMC+ cards. Reads and writes work fine, with read transfer
rates up to 3.5 MiB/s on fast cards with debugging disabled.
The driver has also been tested using the mmc_test module on the same
cards. All tests except 7, 9, 15 and 17 succeed. The first two are
unsupported by all the cards I have, so I don't know if the driver
handles this correctly. The last two fail because the hardware flags a
Data CRC Error instead of a Data Timeout error. I'm not sure how to deal
with that.
Documentation for this controller can be found in many data sheets from
Atmel, including the AT32AP7000 data sheet which can be found here:
http://www.atmel.com/dyn/products/datasheets.asp?family_id=682
Signed-off-by: Haavard Skinnemoen <haavard.skinnemoen@atmel.com>
Signed-off-by: Pierre Ossman <drzeus@drzeus.cx>
2008-06-30 10:35:03 -06:00
|
|
|
host->bus_hz = clk_get_rate(host->mck);
|
|
|
|
|
|
|
|
host->mapbase = regs->start;
|
|
|
|
|
atmel-mci: support multiple mmc slots
The Atmel MCI controller can drive multiple cards through separate sets
of pins, but only one at a time. This patch adds support for
multiplexing access to the controller so that multiple card slots can be
used as if they were hooked up to separate mmc controllers.
The atmel-mci driver registers each slot as a separate mmc_host. Both
access the same common controller state, but they also have some state
on their own for card detection/write protect handling, and separate
shadows of the MR and SDCR registers.
When one of the slots receives a request from the mmc core, the common
controller state is checked. If it's idle, the request is submitted
immediately. If not, the request is added to a queue. When a request is
done, the queue is checked and if there is a queued request, it is
submitted before the completion callback is called.
This patch also includes a few cleanups and fixes, including a locking
overhaul. I had to change the locking extensively in any case, so I
might as well try to get it right. The driver no longer takes any
irq-safe locks, which may or may not improve the overall system
performance.
This patch also adds a bit of documentation of the internal data
structures.
Signed-off-by: Haavard Skinnemoen <haavard.skinnemoen@atmel.com>
2008-09-17 12:53:55 -06:00
|
|
|
tasklet_init(&host->tasklet, atmci_tasklet_func, (unsigned long)host);
|
atmel-mci: Driver for Atmel on-chip MMC controllers
This is a driver for the MMC controller on the AP7000 chips from
Atmel. It should in theory work on AT91 systems too with some
tweaking, but since the DMA interface is quite different, it's not
entirely clear if it's worth merging this with the at91_mci driver.
This driver has been around for a while in BSPs and kernel sources
provided by Atmel, but this particular version uses the generic DMA
Engine framework (with the slave extensions) instead of an
avr32-only DMA controller framework.
This driver can also use PIO transfers when no DMA channels are
available, and for transfers where using DMA may be difficult or
impractical for some reason (e.g. the DMA setup overhead is usually
not worth it for very short transfers, and badly aligned buffers or
lengths are difficult to handle.)
Currently, the driver only support PIO transfers. DMA support has been
split out to a separate patch to hopefully make it easier to review.
The driver has been tested using mmc-block and ext3fs on several SD,
SDHC and MMC+ cards. Reads and writes work fine, with read transfer
rates up to 3.5 MiB/s on fast cards with debugging disabled.
The driver has also been tested using the mmc_test module on the same
cards. All tests except 7, 9, 15 and 17 succeed. The first two are
unsupported by all the cards I have, so I don't know if the driver
handles this correctly. The last two fail because the hardware flags a
Data CRC Error instead of a Data Timeout error. I'm not sure how to deal
with that.
Documentation for this controller can be found in many data sheets from
Atmel, including the AT32AP7000 data sheet which can be found here:
http://www.atmel.com/dyn/products/datasheets.asp?family_id=682
Signed-off-by: Haavard Skinnemoen <haavard.skinnemoen@atmel.com>
Signed-off-by: Pierre Ossman <drzeus@drzeus.cx>
2008-06-30 10:35:03 -06:00
|
|
|
|
2009-02-02 13:08:30 -07:00
|
|
|
ret = request_irq(irq, atmci_interrupt, 0, dev_name(&pdev->dev), host);
|
2014-10-29 22:00:41 -06:00
|
|
|
if (ret) {
|
|
|
|
clk_disable_unprepare(host->mck);
|
2014-09-23 06:51:48 -06:00
|
|
|
return ret;
|
2014-10-29 22:00:41 -06:00
|
|
|
}
|
atmel-mci: Driver for Atmel on-chip MMC controllers
This is a driver for the MMC controller on the AP7000 chips from
Atmel. It should in theory work on AT91 systems too with some
tweaking, but since the DMA interface is quite different, it's not
entirely clear if it's worth merging this with the at91_mci driver.
This driver has been around for a while in BSPs and kernel sources
provided by Atmel, but this particular version uses the generic DMA
Engine framework (with the slave extensions) instead of an
avr32-only DMA controller framework.
This driver can also use PIO transfers when no DMA channels are
available, and for transfers where using DMA may be difficult or
impractical for some reason (e.g. the DMA setup overhead is usually
not worth it for very short transfers, and badly aligned buffers or
lengths are difficult to handle.)
Currently, the driver only support PIO transfers. DMA support has been
split out to a separate patch to hopefully make it easier to review.
The driver has been tested using mmc-block and ext3fs on several SD,
SDHC and MMC+ cards. Reads and writes work fine, with read transfer
rates up to 3.5 MiB/s on fast cards with debugging disabled.
The driver has also been tested using the mmc_test module on the same
cards. All tests except 7, 9, 15 and 17 succeed. The first two are
unsupported by all the cards I have, so I don't know if the driver
handles this correctly. The last two fail because the hardware flags a
Data CRC Error instead of a Data Timeout error. I'm not sure how to deal
with that.
Documentation for this controller can be found in many data sheets from
Atmel, including the AT32AP7000 data sheet which can be found here:
http://www.atmel.com/dyn/products/datasheets.asp?family_id=682
Signed-off-by: Haavard Skinnemoen <haavard.skinnemoen@atmel.com>
Signed-off-by: Pierre Ossman <drzeus@drzeus.cx>
2008-06-30 10:35:03 -06:00
|
|
|
|
2011-08-11 09:25:44 -06:00
|
|
|
/* Get MCI capabilities and set operations according to it */
|
|
|
|
atmci_get_cap(host);
|
2014-12-01 07:35:09 -07:00
|
|
|
ret = atmci_configure_dma(host);
|
|
|
|
if (ret == -EPROBE_DEFER)
|
|
|
|
goto err_dma_probe_defer;
|
|
|
|
if (ret == 0) {
|
2011-08-11 09:25:44 -06:00
|
|
|
host->prepare_data = &atmci_prepare_data_dma;
|
|
|
|
host->submit_data = &atmci_submit_data_dma;
|
|
|
|
host->stop_transfer = &atmci_stop_transfer_dma;
|
|
|
|
} else if (host->caps.has_pdc) {
|
|
|
|
dev_info(&pdev->dev, "using PDC\n");
|
|
|
|
host->prepare_data = &atmci_prepare_data_pdc;
|
|
|
|
host->submit_data = &atmci_submit_data_pdc;
|
|
|
|
host->stop_transfer = &atmci_stop_transfer_pdc;
|
|
|
|
} else {
|
2012-02-09 08:33:53 -07:00
|
|
|
dev_info(&pdev->dev, "using PIO\n");
|
2011-08-11 09:25:44 -06:00
|
|
|
host->prepare_data = &atmci_prepare_data;
|
|
|
|
host->submit_data = &atmci_submit_data;
|
|
|
|
host->stop_transfer = &atmci_stop_transfer;
|
|
|
|
}
|
|
|
|
|
atmel-mci: Driver for Atmel on-chip MMC controllers
This is a driver for the MMC controller on the AP7000 chips from
Atmel. It should in theory work on AT91 systems too with some
tweaking, but since the DMA interface is quite different, it's not
entirely clear if it's worth merging this with the at91_mci driver.
This driver has been around for a while in BSPs and kernel sources
provided by Atmel, but this particular version uses the generic DMA
Engine framework (with the slave extensions) instead of an
avr32-only DMA controller framework.
This driver can also use PIO transfers when no DMA channels are
available, and for transfers where using DMA may be difficult or
impractical for some reason (e.g. the DMA setup overhead is usually
not worth it for very short transfers, and badly aligned buffers or
lengths are difficult to handle.)
Currently, the driver only support PIO transfers. DMA support has been
split out to a separate patch to hopefully make it easier to review.
The driver has been tested using mmc-block and ext3fs on several SD,
SDHC and MMC+ cards. Reads and writes work fine, with read transfer
rates up to 3.5 MiB/s on fast cards with debugging disabled.
The driver has also been tested using the mmc_test module on the same
cards. All tests except 7, 9, 15 and 17 succeed. The first two are
unsupported by all the cards I have, so I don't know if the driver
handles this correctly. The last two fail because the hardware flags a
Data CRC Error instead of a Data Timeout error. I'm not sure how to deal
with that.
Documentation for this controller can be found in many data sheets from
Atmel, including the AT32AP7000 data sheet which can be found here:
http://www.atmel.com/dyn/products/datasheets.asp?family_id=682
Signed-off-by: Haavard Skinnemoen <haavard.skinnemoen@atmel.com>
Signed-off-by: Pierre Ossman <drzeus@drzeus.cx>
2008-06-30 10:35:03 -06:00
|
|
|
platform_set_drvdata(pdev, host);
|
|
|
|
|
2012-05-23 07:52:15 -06:00
|
|
|
setup_timer(&host->timer, atmci_timeout_timer, (unsigned long)host);
|
|
|
|
|
2014-10-29 22:00:41 -06:00
|
|
|
pm_runtime_get_noresume(&pdev->dev);
|
|
|
|
pm_runtime_set_active(&pdev->dev);
|
|
|
|
pm_runtime_set_autosuspend_delay(&pdev->dev, AUTOSUSPEND_DELAY);
|
|
|
|
pm_runtime_use_autosuspend(&pdev->dev);
|
|
|
|
pm_runtime_enable(&pdev->dev);
|
|
|
|
|
atmel-mci: support multiple mmc slots
The Atmel MCI controller can drive multiple cards through separate sets
of pins, but only one at a time. This patch adds support for
multiplexing access to the controller so that multiple card slots can be
used as if they were hooked up to separate mmc controllers.
The atmel-mci driver registers each slot as a separate mmc_host. Both
access the same common controller state, but they also have some state
on their own for card detection/write protect handling, and separate
shadows of the MR and SDCR registers.
When one of the slots receives a request from the mmc core, the common
controller state is checked. If it's idle, the request is submitted
immediately. If not, the request is added to a queue. When a request is
done, the queue is checked and if there is a queued request, it is
submitted before the completion callback is called.
This patch also includes a few cleanups and fixes, including a locking
overhaul. I had to change the locking extensively in any case, so I
might as well try to get it right. The driver no longer takes any
irq-safe locks, which may or may not improve the overall system
performance.
This patch also adds a bit of documentation of the internal data
structures.
Signed-off-by: Haavard Skinnemoen <haavard.skinnemoen@atmel.com>
2008-09-17 12:53:55 -06:00
|
|
|
/* We need at least one slot to succeed */
|
|
|
|
nr_slots = 0;
|
|
|
|
ret = -ENODEV;
|
|
|
|
if (pdata->slot[0].bus_width) {
|
|
|
|
ret = atmci_init_slot(host, &pdata->slot[0],
|
2011-08-11 09:25:41 -06:00
|
|
|
0, ATMCI_SDCSEL_SLOT_A, ATMCI_SDIOIRQA);
|
2012-05-16 07:25:58 -06:00
|
|
|
if (!ret) {
|
atmel-mci: support multiple mmc slots
The Atmel MCI controller can drive multiple cards through separate sets
of pins, but only one at a time. This patch adds support for
multiplexing access to the controller so that multiple card slots can be
used as if they were hooked up to separate mmc controllers.
The atmel-mci driver registers each slot as a separate mmc_host. Both
access the same common controller state, but they also have some state
on their own for card detection/write protect handling, and separate
shadows of the MR and SDCR registers.
When one of the slots receives a request from the mmc core, the common
controller state is checked. If it's idle, the request is submitted
immediately. If not, the request is added to a queue. When a request is
done, the queue is checked and if there is a queued request, it is
submitted before the completion callback is called.
This patch also includes a few cleanups and fixes, including a locking
overhaul. I had to change the locking extensively in any case, so I
might as well try to get it right. The driver no longer takes any
irq-safe locks, which may or may not improve the overall system
performance.
This patch also adds a bit of documentation of the internal data
structures.
Signed-off-by: Haavard Skinnemoen <haavard.skinnemoen@atmel.com>
2008-09-17 12:53:55 -06:00
|
|
|
nr_slots++;
|
2012-05-16 07:25:58 -06:00
|
|
|
host->buf_size = host->slot[0]->mmc->max_req_size;
|
|
|
|
}
|
atmel-mci: support multiple mmc slots
The Atmel MCI controller can drive multiple cards through separate sets
of pins, but only one at a time. This patch adds support for
multiplexing access to the controller so that multiple card slots can be
used as if they were hooked up to separate mmc controllers.
The atmel-mci driver registers each slot as a separate mmc_host. Both
access the same common controller state, but they also have some state
on their own for card detection/write protect handling, and separate
shadows of the MR and SDCR registers.
When one of the slots receives a request from the mmc core, the common
controller state is checked. If it's idle, the request is submitted
immediately. If not, the request is added to a queue. When a request is
done, the queue is checked and if there is a queued request, it is
submitted before the completion callback is called.
This patch also includes a few cleanups and fixes, including a locking
overhaul. I had to change the locking extensively in any case, so I
might as well try to get it right. The driver no longer takes any
irq-safe locks, which may or may not improve the overall system
performance.
This patch also adds a bit of documentation of the internal data
structures.
Signed-off-by: Haavard Skinnemoen <haavard.skinnemoen@atmel.com>
2008-09-17 12:53:55 -06:00
|
|
|
}
|
|
|
|
if (pdata->slot[1].bus_width) {
|
|
|
|
ret = atmci_init_slot(host, &pdata->slot[1],
|
2011-08-11 09:25:41 -06:00
|
|
|
1, ATMCI_SDCSEL_SLOT_B, ATMCI_SDIOIRQB);
|
2012-05-16 07:25:58 -06:00
|
|
|
if (!ret) {
|
atmel-mci: support multiple mmc slots
The Atmel MCI controller can drive multiple cards through separate sets
of pins, but only one at a time. This patch adds support for
multiplexing access to the controller so that multiple card slots can be
used as if they were hooked up to separate mmc controllers.
The atmel-mci driver registers each slot as a separate mmc_host. Both
access the same common controller state, but they also have some state
on their own for card detection/write protect handling, and separate
shadows of the MR and SDCR registers.
When one of the slots receives a request from the mmc core, the common
controller state is checked. If it's idle, the request is submitted
immediately. If not, the request is added to a queue. When a request is
done, the queue is checked and if there is a queued request, it is
submitted before the completion callback is called.
This patch also includes a few cleanups and fixes, including a locking
overhaul. I had to change the locking extensively in any case, so I
might as well try to get it right. The driver no longer takes any
irq-safe locks, which may or may not improve the overall system
performance.
This patch also adds a bit of documentation of the internal data
structures.
Signed-off-by: Haavard Skinnemoen <haavard.skinnemoen@atmel.com>
2008-09-17 12:53:55 -06:00
|
|
|
nr_slots++;
|
2012-05-16 07:25:58 -06:00
|
|
|
if (host->slot[1]->mmc->max_req_size > host->buf_size)
|
|
|
|
host->buf_size =
|
|
|
|
host->slot[1]->mmc->max_req_size;
|
|
|
|
}
|
atmel-mci: Driver for Atmel on-chip MMC controllers
This is a driver for the MMC controller on the AP7000 chips from
Atmel. It should in theory work on AT91 systems too with some
tweaking, but since the DMA interface is quite different, it's not
entirely clear if it's worth merging this with the at91_mci driver.
This driver has been around for a while in BSPs and kernel sources
provided by Atmel, but this particular version uses the generic DMA
Engine framework (with the slave extensions) instead of an
avr32-only DMA controller framework.
This driver can also use PIO transfers when no DMA channels are
available, and for transfers where using DMA may be difficult or
impractical for some reason (e.g. the DMA setup overhead is usually
not worth it for very short transfers, and badly aligned buffers or
lengths are difficult to handle.)
Currently, the driver only support PIO transfers. DMA support has been
split out to a separate patch to hopefully make it easier to review.
The driver has been tested using mmc-block and ext3fs on several SD,
SDHC and MMC+ cards. Reads and writes work fine, with read transfer
rates up to 3.5 MiB/s on fast cards with debugging disabled.
The driver has also been tested using the mmc_test module on the same
cards. All tests except 7, 9, 15 and 17 succeed. The first two are
unsupported by all the cards I have, so I don't know if the driver
handles this correctly. The last two fail because the hardware flags a
Data CRC Error instead of a Data Timeout error. I'm not sure how to deal
with that.
Documentation for this controller can be found in many data sheets from
Atmel, including the AT32AP7000 data sheet which can be found here:
http://www.atmel.com/dyn/products/datasheets.asp?family_id=682
Signed-off-by: Haavard Skinnemoen <haavard.skinnemoen@atmel.com>
Signed-off-by: Pierre Ossman <drzeus@drzeus.cx>
2008-06-30 10:35:03 -06:00
|
|
|
}
|
|
|
|
|
2009-09-22 17:45:19 -06:00
|
|
|
if (!nr_slots) {
|
|
|
|
dev_err(&pdev->dev, "init failed: no slot defined\n");
|
atmel-mci: support multiple mmc slots
The Atmel MCI controller can drive multiple cards through separate sets
of pins, but only one at a time. This patch adds support for
multiplexing access to the controller so that multiple card slots can be
used as if they were hooked up to separate mmc controllers.
The atmel-mci driver registers each slot as a separate mmc_host. Both
access the same common controller state, but they also have some state
on their own for card detection/write protect handling, and separate
shadows of the MR and SDCR registers.
When one of the slots receives a request from the mmc core, the common
controller state is checked. If it's idle, the request is submitted
immediately. If not, the request is added to a queue. When a request is
done, the queue is checked and if there is a queued request, it is
submitted before the completion callback is called.
This patch also includes a few cleanups and fixes, including a locking
overhaul. I had to change the locking extensively in any case, so I
might as well try to get it right. The driver no longer takes any
irq-safe locks, which may or may not improve the overall system
performance.
This patch also adds a bit of documentation of the internal data
structures.
Signed-off-by: Haavard Skinnemoen <haavard.skinnemoen@atmel.com>
2008-09-17 12:53:55 -06:00
|
|
|
goto err_init_slot;
|
2009-09-22 17:45:19 -06:00
|
|
|
}
|
atmel-mci: Driver for Atmel on-chip MMC controllers
This is a driver for the MMC controller on the AP7000 chips from
Atmel. It should in theory work on AT91 systems too with some
tweaking, but since the DMA interface is quite different, it's not
entirely clear if it's worth merging this with the at91_mci driver.
This driver has been around for a while in BSPs and kernel sources
provided by Atmel, but this particular version uses the generic DMA
Engine framework (with the slave extensions) instead of an
avr32-only DMA controller framework.
This driver can also use PIO transfers when no DMA channels are
available, and for transfers where using DMA may be difficult or
impractical for some reason (e.g. the DMA setup overhead is usually
not worth it for very short transfers, and badly aligned buffers or
lengths are difficult to handle.)
Currently, the driver only support PIO transfers. DMA support has been
split out to a separate patch to hopefully make it easier to review.
The driver has been tested using mmc-block and ext3fs on several SD,
SDHC and MMC+ cards. Reads and writes work fine, with read transfer
rates up to 3.5 MiB/s on fast cards with debugging disabled.
The driver has also been tested using the mmc_test module on the same
cards. All tests except 7, 9, 15 and 17 succeed. The first two are
unsupported by all the cards I have, so I don't know if the driver
handles this correctly. The last two fail because the hardware flags a
Data CRC Error instead of a Data Timeout error. I'm not sure how to deal
with that.
Documentation for this controller can be found in many data sheets from
Atmel, including the AT32AP7000 data sheet which can be found here:
http://www.atmel.com/dyn/products/datasheets.asp?family_id=682
Signed-off-by: Haavard Skinnemoen <haavard.skinnemoen@atmel.com>
Signed-off-by: Pierre Ossman <drzeus@drzeus.cx>
2008-06-30 10:35:03 -06:00
|
|
|
|
2012-05-16 07:25:58 -06:00
|
|
|
if (!host->caps.has_rwproof) {
|
|
|
|
host->buffer = dma_alloc_coherent(&pdev->dev, host->buf_size,
|
|
|
|
&host->buf_phys_addr,
|
|
|
|
GFP_KERNEL);
|
|
|
|
if (!host->buffer) {
|
|
|
|
ret = -ENOMEM;
|
|
|
|
dev_err(&pdev->dev, "buffer allocation failed\n");
|
2014-09-23 04:20:06 -06:00
|
|
|
goto err_dma_alloc;
|
2012-05-16 07:25:58 -06:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
atmel-mci: support multiple mmc slots
The Atmel MCI controller can drive multiple cards through separate sets
of pins, but only one at a time. This patch adds support for
multiplexing access to the controller so that multiple card slots can be
used as if they were hooked up to separate mmc controllers.
The atmel-mci driver registers each slot as a separate mmc_host. Both
access the same common controller state, but they also have some state
on their own for card detection/write protect handling, and separate
shadows of the MR and SDCR registers.
When one of the slots receives a request from the mmc core, the common
controller state is checked. If it's idle, the request is submitted
immediately. If not, the request is added to a queue. When a request is
done, the queue is checked and if there is a queued request, it is
submitted before the completion callback is called.
This patch also includes a few cleanups and fixes, including a locking
overhaul. I had to change the locking extensively in any case, so I
might as well try to get it right. The driver no longer takes any
irq-safe locks, which may or may not improve the overall system
performance.
This patch also adds a bit of documentation of the internal data
structures.
Signed-off-by: Haavard Skinnemoen <haavard.skinnemoen@atmel.com>
2008-09-17 12:53:55 -06:00
|
|
|
dev_info(&pdev->dev,
|
|
|
|
"Atmel MCI controller at 0x%08lx irq %d, %u slots\n",
|
|
|
|
host->mapbase, irq, nr_slots);
|
2008-07-24 06:18:59 -06:00
|
|
|
|
2014-10-29 22:00:41 -06:00
|
|
|
pm_runtime_mark_last_busy(&host->pdev->dev);
|
|
|
|
pm_runtime_put_autosuspend(&pdev->dev);
|
|
|
|
|
atmel-mci: Driver for Atmel on-chip MMC controllers
This is a driver for the MMC controller on the AP7000 chips from
Atmel. It should in theory work on AT91 systems too with some
tweaking, but since the DMA interface is quite different, it's not
entirely clear if it's worth merging this with the at91_mci driver.
This driver has been around for a while in BSPs and kernel sources
provided by Atmel, but this particular version uses the generic DMA
Engine framework (with the slave extensions) instead of an
avr32-only DMA controller framework.
This driver can also use PIO transfers when no DMA channels are
available, and for transfers where using DMA may be difficult or
impractical for some reason (e.g. the DMA setup overhead is usually
not worth it for very short transfers, and badly aligned buffers or
lengths are difficult to handle.)
Currently, the driver only support PIO transfers. DMA support has been
split out to a separate patch to hopefully make it easier to review.
The driver has been tested using mmc-block and ext3fs on several SD,
SDHC and MMC+ cards. Reads and writes work fine, with read transfer
rates up to 3.5 MiB/s on fast cards with debugging disabled.
The driver has also been tested using the mmc_test module on the same
cards. All tests except 7, 9, 15 and 17 succeed. The first two are
unsupported by all the cards I have, so I don't know if the driver
handles this correctly. The last two fail because the hardware flags a
Data CRC Error instead of a Data Timeout error. I'm not sure how to deal
with that.
Documentation for this controller can be found in many data sheets from
Atmel, including the AT32AP7000 data sheet which can be found here:
http://www.atmel.com/dyn/products/datasheets.asp?family_id=682
Signed-off-by: Haavard Skinnemoen <haavard.skinnemoen@atmel.com>
Signed-off-by: Pierre Ossman <drzeus@drzeus.cx>
2008-06-30 10:35:03 -06:00
|
|
|
return 0;
|
|
|
|
|
2014-09-23 04:20:06 -06:00
|
|
|
err_dma_alloc:
|
|
|
|
for (i = 0; i < ATMCI_MAX_NR_SLOTS; i++) {
|
|
|
|
if (host->slot[i])
|
|
|
|
atmci_cleanup_slot(host->slot[i], i);
|
|
|
|
}
|
atmel-mci: support multiple mmc slots
The Atmel MCI controller can drive multiple cards through separate sets
of pins, but only one at a time. This patch adds support for
multiplexing access to the controller so that multiple card slots can be
used as if they were hooked up to separate mmc controllers.
The atmel-mci driver registers each slot as a separate mmc_host. Both
access the same common controller state, but they also have some state
on their own for card detection/write protect handling, and separate
shadows of the MR and SDCR registers.
When one of the slots receives a request from the mmc core, the common
controller state is checked. If it's idle, the request is submitted
immediately. If not, the request is added to a queue. When a request is
done, the queue is checked and if there is a queued request, it is
submitted before the completion callback is called.
This patch also includes a few cleanups and fixes, including a locking
overhaul. I had to change the locking extensively in any case, so I
might as well try to get it right. The driver no longer takes any
irq-safe locks, which may or may not improve the overall system
performance.
This patch also adds a bit of documentation of the internal data
structures.
Signed-off-by: Haavard Skinnemoen <haavard.skinnemoen@atmel.com>
2008-09-17 12:53:55 -06:00
|
|
|
err_init_slot:
|
2014-10-29 22:00:41 -06:00
|
|
|
clk_disable_unprepare(host->mck);
|
|
|
|
|
|
|
|
pm_runtime_disable(&pdev->dev);
|
|
|
|
pm_runtime_put_noidle(&pdev->dev);
|
|
|
|
|
2014-09-23 04:20:06 -06:00
|
|
|
del_timer_sync(&host->timer);
|
2014-12-01 07:35:09 -07:00
|
|
|
if (!IS_ERR(host->dma.chan))
|
2009-01-06 11:38:16 -07:00
|
|
|
dma_release_channel(host->dma.chan);
|
2014-12-01 07:35:09 -07:00
|
|
|
err_dma_probe_defer:
|
atmel-mci: support multiple mmc slots
The Atmel MCI controller can drive multiple cards through separate sets
of pins, but only one at a time. This patch adds support for
multiplexing access to the controller so that multiple card slots can be
used as if they were hooked up to separate mmc controllers.
The atmel-mci driver registers each slot as a separate mmc_host. Both
access the same common controller state, but they also have some state
on their own for card detection/write protect handling, and separate
shadows of the MR and SDCR registers.
When one of the slots receives a request from the mmc core, the common
controller state is checked. If it's idle, the request is submitted
immediately. If not, the request is added to a queue. When a request is
done, the queue is checked and if there is a queued request, it is
submitted before the completion callback is called.
This patch also includes a few cleanups and fixes, including a locking
overhaul. I had to change the locking extensively in any case, so I
might as well try to get it right. The driver no longer takes any
irq-safe locks, which may or may not improve the overall system
performance.
This patch also adds a bit of documentation of the internal data
structures.
Signed-off-by: Haavard Skinnemoen <haavard.skinnemoen@atmel.com>
2008-09-17 12:53:55 -06:00
|
|
|
free_irq(irq, host);
|
atmel-mci: Driver for Atmel on-chip MMC controllers
This is a driver for the MMC controller on the AP7000 chips from
Atmel. It should in theory work on AT91 systems too with some
tweaking, but since the DMA interface is quite different, it's not
entirely clear if it's worth merging this with the at91_mci driver.
This driver has been around for a while in BSPs and kernel sources
provided by Atmel, but this particular version uses the generic DMA
Engine framework (with the slave extensions) instead of an
avr32-only DMA controller framework.
This driver can also use PIO transfers when no DMA channels are
available, and for transfers where using DMA may be difficult or
impractical for some reason (e.g. the DMA setup overhead is usually
not worth it for very short transfers, and badly aligned buffers or
lengths are difficult to handle.)
Currently, the driver only support PIO transfers. DMA support has been
split out to a separate patch to hopefully make it easier to review.
The driver has been tested using mmc-block and ext3fs on several SD,
SDHC and MMC+ cards. Reads and writes work fine, with read transfer
rates up to 3.5 MiB/s on fast cards with debugging disabled.
The driver has also been tested using the mmc_test module on the same
cards. All tests except 7, 9, 15 and 17 succeed. The first two are
unsupported by all the cards I have, so I don't know if the driver
handles this correctly. The last two fail because the hardware flags a
Data CRC Error instead of a Data Timeout error. I'm not sure how to deal
with that.
Documentation for this controller can be found in many data sheets from
Atmel, including the AT32AP7000 data sheet which can be found here:
http://www.atmel.com/dyn/products/datasheets.asp?family_id=682
Signed-off-by: Haavard Skinnemoen <haavard.skinnemoen@atmel.com>
Signed-off-by: Pierre Ossman <drzeus@drzeus.cx>
2008-06-30 10:35:03 -06:00
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
2014-12-01 07:35:07 -07:00
|
|
|
static int atmci_remove(struct platform_device *pdev)
|
atmel-mci: Driver for Atmel on-chip MMC controllers
This is a driver for the MMC controller on the AP7000 chips from
Atmel. It should in theory work on AT91 systems too with some
tweaking, but since the DMA interface is quite different, it's not
entirely clear if it's worth merging this with the at91_mci driver.
This driver has been around for a while in BSPs and kernel sources
provided by Atmel, but this particular version uses the generic DMA
Engine framework (with the slave extensions) instead of an
avr32-only DMA controller framework.
This driver can also use PIO transfers when no DMA channels are
available, and for transfers where using DMA may be difficult or
impractical for some reason (e.g. the DMA setup overhead is usually
not worth it for very short transfers, and badly aligned buffers or
lengths are difficult to handle.)
Currently, the driver only support PIO transfers. DMA support has been
split out to a separate patch to hopefully make it easier to review.
The driver has been tested using mmc-block and ext3fs on several SD,
SDHC and MMC+ cards. Reads and writes work fine, with read transfer
rates up to 3.5 MiB/s on fast cards with debugging disabled.
The driver has also been tested using the mmc_test module on the same
cards. All tests except 7, 9, 15 and 17 succeed. The first two are
unsupported by all the cards I have, so I don't know if the driver
handles this correctly. The last two fail because the hardware flags a
Data CRC Error instead of a Data Timeout error. I'm not sure how to deal
with that.
Documentation for this controller can be found in many data sheets from
Atmel, including the AT32AP7000 data sheet which can be found here:
http://www.atmel.com/dyn/products/datasheets.asp?family_id=682
Signed-off-by: Haavard Skinnemoen <haavard.skinnemoen@atmel.com>
Signed-off-by: Pierre Ossman <drzeus@drzeus.cx>
2008-06-30 10:35:03 -06:00
|
|
|
{
|
atmel-mci: support multiple mmc slots
The Atmel MCI controller can drive multiple cards through separate sets
of pins, but only one at a time. This patch adds support for
multiplexing access to the controller so that multiple card slots can be
used as if they were hooked up to separate mmc controllers.
The atmel-mci driver registers each slot as a separate mmc_host. Both
access the same common controller state, but they also have some state
on their own for card detection/write protect handling, and separate
shadows of the MR and SDCR registers.
When one of the slots receives a request from the mmc core, the common
controller state is checked. If it's idle, the request is submitted
immediately. If not, the request is added to a queue. When a request is
done, the queue is checked and if there is a queued request, it is
submitted before the completion callback is called.
This patch also includes a few cleanups and fixes, including a locking
overhaul. I had to change the locking extensively in any case, so I
might as well try to get it right. The driver no longer takes any
irq-safe locks, which may or may not improve the overall system
performance.
This patch also adds a bit of documentation of the internal data
structures.
Signed-off-by: Haavard Skinnemoen <haavard.skinnemoen@atmel.com>
2008-09-17 12:53:55 -06:00
|
|
|
struct atmel_mci *host = platform_get_drvdata(pdev);
|
|
|
|
unsigned int i;
|
atmel-mci: Driver for Atmel on-chip MMC controllers
This is a driver for the MMC controller on the AP7000 chips from
Atmel. It should in theory work on AT91 systems too with some
tweaking, but since the DMA interface is quite different, it's not
entirely clear if it's worth merging this with the at91_mci driver.
This driver has been around for a while in BSPs and kernel sources
provided by Atmel, but this particular version uses the generic DMA
Engine framework (with the slave extensions) instead of an
avr32-only DMA controller framework.
This driver can also use PIO transfers when no DMA channels are
available, and for transfers where using DMA may be difficult or
impractical for some reason (e.g. the DMA setup overhead is usually
not worth it for very short transfers, and badly aligned buffers or
lengths are difficult to handle.)
Currently, the driver only support PIO transfers. DMA support has been
split out to a separate patch to hopefully make it easier to review.
The driver has been tested using mmc-block and ext3fs on several SD,
SDHC and MMC+ cards. Reads and writes work fine, with read transfer
rates up to 3.5 MiB/s on fast cards with debugging disabled.
The driver has also been tested using the mmc_test module on the same
cards. All tests except 7, 9, 15 and 17 succeed. The first two are
unsupported by all the cards I have, so I don't know if the driver
handles this correctly. The last two fail because the hardware flags a
Data CRC Error instead of a Data Timeout error. I'm not sure how to deal
with that.
Documentation for this controller can be found in many data sheets from
Atmel, including the AT32AP7000 data sheet which can be found here:
http://www.atmel.com/dyn/products/datasheets.asp?family_id=682
Signed-off-by: Haavard Skinnemoen <haavard.skinnemoen@atmel.com>
Signed-off-by: Pierre Ossman <drzeus@drzeus.cx>
2008-06-30 10:35:03 -06:00
|
|
|
|
2014-10-29 22:00:41 -06:00
|
|
|
pm_runtime_get_sync(&pdev->dev);
|
|
|
|
|
2012-05-16 07:25:58 -06:00
|
|
|
if (host->buffer)
|
|
|
|
dma_free_coherent(&pdev->dev, host->buf_size,
|
|
|
|
host->buffer, host->buf_phys_addr);
|
|
|
|
|
2011-08-11 09:25:41 -06:00
|
|
|
for (i = 0; i < ATMCI_MAX_NR_SLOTS; i++) {
|
atmel-mci: support multiple mmc slots
The Atmel MCI controller can drive multiple cards through separate sets
of pins, but only one at a time. This patch adds support for
multiplexing access to the controller so that multiple card slots can be
used as if they were hooked up to separate mmc controllers.
The atmel-mci driver registers each slot as a separate mmc_host. Both
access the same common controller state, but they also have some state
on their own for card detection/write protect handling, and separate
shadows of the MR and SDCR registers.
When one of the slots receives a request from the mmc core, the common
controller state is checked. If it's idle, the request is submitted
immediately. If not, the request is added to a queue. When a request is
done, the queue is checked and if there is a queued request, it is
submitted before the completion callback is called.
This patch also includes a few cleanups and fixes, including a locking
overhaul. I had to change the locking extensively in any case, so I
might as well try to get it right. The driver no longer takes any
irq-safe locks, which may or may not improve the overall system
performance.
This patch also adds a bit of documentation of the internal data
structures.
Signed-off-by: Haavard Skinnemoen <haavard.skinnemoen@atmel.com>
2008-09-17 12:53:55 -06:00
|
|
|
if (host->slot[i])
|
|
|
|
atmci_cleanup_slot(host->slot[i], i);
|
|
|
|
}
|
atmel-mci: Driver for Atmel on-chip MMC controllers
This is a driver for the MMC controller on the AP7000 chips from
Atmel. It should in theory work on AT91 systems too with some
tweaking, but since the DMA interface is quite different, it's not
entirely clear if it's worth merging this with the at91_mci driver.
This driver has been around for a while in BSPs and kernel sources
provided by Atmel, but this particular version uses the generic DMA
Engine framework (with the slave extensions) instead of an
avr32-only DMA controller framework.
This driver can also use PIO transfers when no DMA channels are
available, and for transfers where using DMA may be difficult or
impractical for some reason (e.g. the DMA setup overhead is usually
not worth it for very short transfers, and badly aligned buffers or
lengths are difficult to handle.)
Currently, the driver only support PIO transfers. DMA support has been
split out to a separate patch to hopefully make it easier to review.
The driver has been tested using mmc-block and ext3fs on several SD,
SDHC and MMC+ cards. Reads and writes work fine, with read transfer
rates up to 3.5 MiB/s on fast cards with debugging disabled.
The driver has also been tested using the mmc_test module on the same
cards. All tests except 7, 9, 15 and 17 succeed. The first two are
unsupported by all the cards I have, so I don't know if the driver
handles this correctly. The last two fail because the hardware flags a
Data CRC Error instead of a Data Timeout error. I'm not sure how to deal
with that.
Documentation for this controller can be found in many data sheets from
Atmel, including the AT32AP7000 data sheet which can be found here:
http://www.atmel.com/dyn/products/datasheets.asp?family_id=682
Signed-off-by: Haavard Skinnemoen <haavard.skinnemoen@atmel.com>
Signed-off-by: Pierre Ossman <drzeus@drzeus.cx>
2008-06-30 10:35:03 -06:00
|
|
|
|
2011-08-11 09:25:42 -06:00
|
|
|
atmci_writel(host, ATMCI_IDR, ~0UL);
|
|
|
|
atmci_writel(host, ATMCI_CR, ATMCI_CR_MCIDIS);
|
|
|
|
atmci_readl(host, ATMCI_SR);
|
atmel-mci: Driver for Atmel on-chip MMC controllers
This is a driver for the MMC controller on the AP7000 chips from
Atmel. It should in theory work on AT91 systems too with some
tweaking, but since the DMA interface is quite different, it's not
entirely clear if it's worth merging this with the at91_mci driver.
This driver has been around for a while in BSPs and kernel sources
provided by Atmel, but this particular version uses the generic DMA
Engine framework (with the slave extensions) instead of an
avr32-only DMA controller framework.
This driver can also use PIO transfers when no DMA channels are
available, and for transfers where using DMA may be difficult or
impractical for some reason (e.g. the DMA setup overhead is usually
not worth it for very short transfers, and badly aligned buffers or
lengths are difficult to handle.)
Currently, the driver only support PIO transfers. DMA support has been
split out to a separate patch to hopefully make it easier to review.
The driver has been tested using mmc-block and ext3fs on several SD,
SDHC and MMC+ cards. Reads and writes work fine, with read transfer
rates up to 3.5 MiB/s on fast cards with debugging disabled.
The driver has also been tested using the mmc_test module on the same
cards. All tests except 7, 9, 15 and 17 succeed. The first two are
unsupported by all the cards I have, so I don't know if the driver
handles this correctly. The last two fail because the hardware flags a
Data CRC Error instead of a Data Timeout error. I'm not sure how to deal
with that.
Documentation for this controller can be found in many data sheets from
Atmel, including the AT32AP7000 data sheet which can be found here:
http://www.atmel.com/dyn/products/datasheets.asp?family_id=682
Signed-off-by: Haavard Skinnemoen <haavard.skinnemoen@atmel.com>
Signed-off-by: Pierre Ossman <drzeus@drzeus.cx>
2008-06-30 10:35:03 -06:00
|
|
|
|
2014-09-23 04:20:06 -06:00
|
|
|
del_timer_sync(&host->timer);
|
2014-12-01 07:35:09 -07:00
|
|
|
if (!IS_ERR(host->dma.chan))
|
2009-01-06 11:38:16 -07:00
|
|
|
dma_release_channel(host->dma.chan);
|
2008-07-30 12:29:03 -06:00
|
|
|
|
atmel-mci: support multiple mmc slots
The Atmel MCI controller can drive multiple cards through separate sets
of pins, but only one at a time. This patch adds support for
multiplexing access to the controller so that multiple card slots can be
used as if they were hooked up to separate mmc controllers.
The atmel-mci driver registers each slot as a separate mmc_host. Both
access the same common controller state, but they also have some state
on their own for card detection/write protect handling, and separate
shadows of the MR and SDCR registers.
When one of the slots receives a request from the mmc core, the common
controller state is checked. If it's idle, the request is submitted
immediately. If not, the request is added to a queue. When a request is
done, the queue is checked and if there is a queued request, it is
submitted before the completion callback is called.
This patch also includes a few cleanups and fixes, including a locking
overhaul. I had to change the locking extensively in any case, so I
might as well try to get it right. The driver no longer takes any
irq-safe locks, which may or may not improve the overall system
performance.
This patch also adds a bit of documentation of the internal data
structures.
Signed-off-by: Haavard Skinnemoen <haavard.skinnemoen@atmel.com>
2008-09-17 12:53:55 -06:00
|
|
|
free_irq(platform_get_irq(pdev, 0), host);
|
atmel-mci: Driver for Atmel on-chip MMC controllers
This is a driver for the MMC controller on the AP7000 chips from
Atmel. It should in theory work on AT91 systems too with some
tweaking, but since the DMA interface is quite different, it's not
entirely clear if it's worth merging this with the at91_mci driver.
This driver has been around for a while in BSPs and kernel sources
provided by Atmel, but this particular version uses the generic DMA
Engine framework (with the slave extensions) instead of an
avr32-only DMA controller framework.
This driver can also use PIO transfers when no DMA channels are
available, and for transfers where using DMA may be difficult or
impractical for some reason (e.g. the DMA setup overhead is usually
not worth it for very short transfers, and badly aligned buffers or
lengths are difficult to handle.)
Currently, the driver only support PIO transfers. DMA support has been
split out to a separate patch to hopefully make it easier to review.
The driver has been tested using mmc-block and ext3fs on several SD,
SDHC and MMC+ cards. Reads and writes work fine, with read transfer
rates up to 3.5 MiB/s on fast cards with debugging disabled.
The driver has also been tested using the mmc_test module on the same
cards. All tests except 7, 9, 15 and 17 succeed. The first two are
unsupported by all the cards I have, so I don't know if the driver
handles this correctly. The last two fail because the hardware flags a
Data CRC Error instead of a Data Timeout error. I'm not sure how to deal
with that.
Documentation for this controller can be found in many data sheets from
Atmel, including the AT32AP7000 data sheet which can be found here:
http://www.atmel.com/dyn/products/datasheets.asp?family_id=682
Signed-off-by: Haavard Skinnemoen <haavard.skinnemoen@atmel.com>
Signed-off-by: Pierre Ossman <drzeus@drzeus.cx>
2008-06-30 10:35:03 -06:00
|
|
|
|
2014-10-29 22:00:41 -06:00
|
|
|
clk_disable_unprepare(host->mck);
|
|
|
|
|
|
|
|
pm_runtime_disable(&pdev->dev);
|
|
|
|
pm_runtime_put_noidle(&pdev->dev);
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
#ifdef CONFIG_PM
|
|
|
|
static int atmci_runtime_suspend(struct device *dev)
|
|
|
|
{
|
|
|
|
struct atmel_mci *host = dev_get_drvdata(dev);
|
|
|
|
|
|
|
|
clk_disable_unprepare(host->mck);
|
|
|
|
|
2014-11-06 17:48:13 -07:00
|
|
|
pinctrl_pm_select_sleep_state(dev);
|
|
|
|
|
atmel-mci: Driver for Atmel on-chip MMC controllers
This is a driver for the MMC controller on the AP7000 chips from
Atmel. It should in theory work on AT91 systems too with some
tweaking, but since the DMA interface is quite different, it's not
entirely clear if it's worth merging this with the at91_mci driver.
This driver has been around for a while in BSPs and kernel sources
provided by Atmel, but this particular version uses the generic DMA
Engine framework (with the slave extensions) instead of an
avr32-only DMA controller framework.
This driver can also use PIO transfers when no DMA channels are
available, and for transfers where using DMA may be difficult or
impractical for some reason (e.g. the DMA setup overhead is usually
not worth it for very short transfers, and badly aligned buffers or
lengths are difficult to handle.)
Currently, the driver only support PIO transfers. DMA support has been
split out to a separate patch to hopefully make it easier to review.
The driver has been tested using mmc-block and ext3fs on several SD,
SDHC and MMC+ cards. Reads and writes work fine, with read transfer
rates up to 3.5 MiB/s on fast cards with debugging disabled.
The driver has also been tested using the mmc_test module on the same
cards. All tests except 7, 9, 15 and 17 succeed. The first two are
unsupported by all the cards I have, so I don't know if the driver
handles this correctly. The last two fail because the hardware flags a
Data CRC Error instead of a Data Timeout error. I'm not sure how to deal
with that.
Documentation for this controller can be found in many data sheets from
Atmel, including the AT32AP7000 data sheet which can be found here:
http://www.atmel.com/dyn/products/datasheets.asp?family_id=682
Signed-off-by: Haavard Skinnemoen <haavard.skinnemoen@atmel.com>
Signed-off-by: Pierre Ossman <drzeus@drzeus.cx>
2008-06-30 10:35:03 -06:00
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2014-10-29 22:00:41 -06:00
|
|
|
static int atmci_runtime_resume(struct device *dev)
|
|
|
|
{
|
|
|
|
struct atmel_mci *host = dev_get_drvdata(dev);
|
|
|
|
|
2014-11-06 17:48:13 -07:00
|
|
|
pinctrl_pm_select_default_state(dev);
|
|
|
|
|
2014-10-29 22:00:41 -06:00
|
|
|
return clk_prepare_enable(host->mck);
|
|
|
|
}
|
|
|
|
#endif
|
|
|
|
|
|
|
|
static const struct dev_pm_ops atmci_dev_pm_ops = {
|
|
|
|
SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
|
|
|
|
pm_runtime_force_resume)
|
2014-12-12 16:44:11 -07:00
|
|
|
SET_RUNTIME_PM_OPS(atmci_runtime_suspend, atmci_runtime_resume, NULL)
|
2014-10-29 22:00:41 -06:00
|
|
|
};
|
|
|
|
|
atmel-mci: Driver for Atmel on-chip MMC controllers
This is a driver for the MMC controller on the AP7000 chips from
Atmel. It should in theory work on AT91 systems too with some
tweaking, but since the DMA interface is quite different, it's not
entirely clear if it's worth merging this with the at91_mci driver.
This driver has been around for a while in BSPs and kernel sources
provided by Atmel, but this particular version uses the generic DMA
Engine framework (with the slave extensions) instead of an
avr32-only DMA controller framework.
This driver can also use PIO transfers when no DMA channels are
available, and for transfers where using DMA may be difficult or
impractical for some reason (e.g. the DMA setup overhead is usually
not worth it for very short transfers, and badly aligned buffers or
lengths are difficult to handle.)
Currently, the driver only support PIO transfers. DMA support has been
split out to a separate patch to hopefully make it easier to review.
The driver has been tested using mmc-block and ext3fs on several SD,
SDHC and MMC+ cards. Reads and writes work fine, with read transfer
rates up to 3.5 MiB/s on fast cards with debugging disabled.
The driver has also been tested using the mmc_test module on the same
cards. All tests except 7, 9, 15 and 17 succeed. The first two are
unsupported by all the cards I have, so I don't know if the driver
handles this correctly. The last two fail because the hardware flags a
Data CRC Error instead of a Data Timeout error. I'm not sure how to deal
with that.
Documentation for this controller can be found in many data sheets from
Atmel, including the AT32AP7000 data sheet which can be found here:
http://www.atmel.com/dyn/products/datasheets.asp?family_id=682
Signed-off-by: Haavard Skinnemoen <haavard.skinnemoen@atmel.com>
Signed-off-by: Pierre Ossman <drzeus@drzeus.cx>
2008-06-30 10:35:03 -06:00
|
|
|
static struct platform_driver atmci_driver = {
|
2014-12-01 07:35:08 -07:00
|
|
|
.probe = atmci_probe,
|
2014-12-01 07:35:07 -07:00
|
|
|
.remove = atmci_remove,
|
atmel-mci: Driver for Atmel on-chip MMC controllers
This is a driver for the MMC controller on the AP7000 chips from
Atmel. It should in theory work on AT91 systems too with some
tweaking, but since the DMA interface is quite different, it's not
entirely clear if it's worth merging this with the at91_mci driver.
This driver has been around for a while in BSPs and kernel sources
provided by Atmel, but this particular version uses the generic DMA
Engine framework (with the slave extensions) instead of an
avr32-only DMA controller framework.
This driver can also use PIO transfers when no DMA channels are
available, and for transfers where using DMA may be difficult or
impractical for some reason (e.g. the DMA setup overhead is usually
not worth it for very short transfers, and badly aligned buffers or
lengths are difficult to handle.)
Currently, the driver only support PIO transfers. DMA support has been
split out to a separate patch to hopefully make it easier to review.
The driver has been tested using mmc-block and ext3fs on several SD,
SDHC and MMC+ cards. Reads and writes work fine, with read transfer
rates up to 3.5 MiB/s on fast cards with debugging disabled.
The driver has also been tested using the mmc_test module on the same
cards. All tests except 7, 9, 15 and 17 succeed. The first two are
unsupported by all the cards I have, so I don't know if the driver
handles this correctly. The last two fail because the hardware flags a
Data CRC Error instead of a Data Timeout error. I'm not sure how to deal
with that.
Documentation for this controller can be found in many data sheets from
Atmel, including the AT32AP7000 data sheet which can be found here:
http://www.atmel.com/dyn/products/datasheets.asp?family_id=682
Signed-off-by: Haavard Skinnemoen <haavard.skinnemoen@atmel.com>
Signed-off-by: Pierre Ossman <drzeus@drzeus.cx>
2008-06-30 10:35:03 -06:00
|
|
|
.driver = {
|
|
|
|
.name = "atmel_mci",
|
2012-07-24 07:30:03 -06:00
|
|
|
.of_match_table = of_match_ptr(atmci_dt_ids),
|
2014-10-29 22:00:41 -06:00
|
|
|
.pm = &atmci_dev_pm_ops,
|
atmel-mci: Driver for Atmel on-chip MMC controllers
This is a driver for the MMC controller on the AP7000 chips from
Atmel. It should in theory work on AT91 systems too with some
tweaking, but since the DMA interface is quite different, it's not
entirely clear if it's worth merging this with the at91_mci driver.
This driver has been around for a while in BSPs and kernel sources
provided by Atmel, but this particular version uses the generic DMA
Engine framework (with the slave extensions) instead of an
avr32-only DMA controller framework.
This driver can also use PIO transfers when no DMA channels are
available, and for transfers where using DMA may be difficult or
impractical for some reason (e.g. the DMA setup overhead is usually
not worth it for very short transfers, and badly aligned buffers or
lengths are difficult to handle.)
Currently, the driver only support PIO transfers. DMA support has been
split out to a separate patch to hopefully make it easier to review.
The driver has been tested using mmc-block and ext3fs on several SD,
SDHC and MMC+ cards. Reads and writes work fine, with read transfer
rates up to 3.5 MiB/s on fast cards with debugging disabled.
The driver has also been tested using the mmc_test module on the same
cards. All tests except 7, 9, 15 and 17 succeed. The first two are
unsupported by all the cards I have, so I don't know if the driver
handles this correctly. The last two fail because the hardware flags a
Data CRC Error instead of a Data Timeout error. I'm not sure how to deal
with that.
Documentation for this controller can be found in many data sheets from
Atmel, including the AT32AP7000 data sheet which can be found here:
http://www.atmel.com/dyn/products/datasheets.asp?family_id=682
Signed-off-by: Haavard Skinnemoen <haavard.skinnemoen@atmel.com>
Signed-off-by: Pierre Ossman <drzeus@drzeus.cx>
2008-06-30 10:35:03 -06:00
|
|
|
},
|
|
|
|
};
|
2014-12-01 07:35:08 -07:00
|
|
|
module_platform_driver(atmci_driver);
|
atmel-mci: Driver for Atmel on-chip MMC controllers
This is a driver for the MMC controller on the AP7000 chips from
Atmel. It should in theory work on AT91 systems too with some
tweaking, but since the DMA interface is quite different, it's not
entirely clear if it's worth merging this with the at91_mci driver.
This driver has been around for a while in BSPs and kernel sources
provided by Atmel, but this particular version uses the generic DMA
Engine framework (with the slave extensions) instead of an
avr32-only DMA controller framework.
This driver can also use PIO transfers when no DMA channels are
available, and for transfers where using DMA may be difficult or
impractical for some reason (e.g. the DMA setup overhead is usually
not worth it for very short transfers, and badly aligned buffers or
lengths are difficult to handle.)
Currently, the driver only support PIO transfers. DMA support has been
split out to a separate patch to hopefully make it easier to review.
The driver has been tested using mmc-block and ext3fs on several SD,
SDHC and MMC+ cards. Reads and writes work fine, with read transfer
rates up to 3.5 MiB/s on fast cards with debugging disabled.
The driver has also been tested using the mmc_test module on the same
cards. All tests except 7, 9, 15 and 17 succeed. The first two are
unsupported by all the cards I have, so I don't know if the driver
handles this correctly. The last two fail because the hardware flags a
Data CRC Error instead of a Data Timeout error. I'm not sure how to deal
with that.
Documentation for this controller can be found in many data sheets from
Atmel, including the AT32AP7000 data sheet which can be found here:
http://www.atmel.com/dyn/products/datasheets.asp?family_id=682
Signed-off-by: Haavard Skinnemoen <haavard.skinnemoen@atmel.com>
Signed-off-by: Pierre Ossman <drzeus@drzeus.cx>
2008-06-30 10:35:03 -06:00
|
|
|
|
|
|
|
MODULE_DESCRIPTION("Atmel Multimedia Card Interface driver");
|
2011-05-18 08:49:24 -06:00
|
|
|
MODULE_AUTHOR("Haavard Skinnemoen (Atmel)");
|
atmel-mci: Driver for Atmel on-chip MMC controllers
This is a driver for the MMC controller on the AP7000 chips from
Atmel. It should in theory work on AT91 systems too with some
tweaking, but since the DMA interface is quite different, it's not
entirely clear if it's worth merging this with the at91_mci driver.
This driver has been around for a while in BSPs and kernel sources
provided by Atmel, but this particular version uses the generic DMA
Engine framework (with the slave extensions) instead of an
avr32-only DMA controller framework.
This driver can also use PIO transfers when no DMA channels are
available, and for transfers where using DMA may be difficult or
impractical for some reason (e.g. the DMA setup overhead is usually
not worth it for very short transfers, and badly aligned buffers or
lengths are difficult to handle.)
Currently, the driver only support PIO transfers. DMA support has been
split out to a separate patch to hopefully make it easier to review.
The driver has been tested using mmc-block and ext3fs on several SD,
SDHC and MMC+ cards. Reads and writes work fine, with read transfer
rates up to 3.5 MiB/s on fast cards with debugging disabled.
The driver has also been tested using the mmc_test module on the same
cards. All tests except 7, 9, 15 and 17 succeed. The first two are
unsupported by all the cards I have, so I don't know if the driver
handles this correctly. The last two fail because the hardware flags a
Data CRC Error instead of a Data Timeout error. I'm not sure how to deal
with that.
Documentation for this controller can be found in many data sheets from
Atmel, including the AT32AP7000 data sheet which can be found here:
http://www.atmel.com/dyn/products/datasheets.asp?family_id=682
Signed-off-by: Haavard Skinnemoen <haavard.skinnemoen@atmel.com>
Signed-off-by: Pierre Ossman <drzeus@drzeus.cx>
2008-06-30 10:35:03 -06:00
|
|
|
MODULE_LICENSE("GPL v2");
|