2007-09-23 08:59:52 -06:00
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/*
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* linux/include/arm/hardware/it8152.h
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*
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* Copyright Compulab Ltd., 2006,2007
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* Mike Rapoport <mike@compulab.co.il>
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*
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* ITE 8152 companion chip register definitions
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*/
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#ifndef __ASM_HARDWARE_IT8152_H
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#define __ASM_HARDWARE_IT8152_H
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extern unsigned long it8152_base_address;
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#define IT8152_IO_BASE (it8152_base_address + 0x03e00000)
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#define IT8152_CFGREG_BASE (it8152_base_address + 0x03f00000)
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#define __REG_IT8152(x) (it8152_base_address + (x))
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#define IT8152_PCI_CFG_ADDR __REG_IT8152(0x3f00800)
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#define IT8152_PCI_CFG_DATA __REG_IT8152(0x3f00804)
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#define IT8152_INTC_LDCNIRR __REG_IT8152(0x3f00300)
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#define IT8152_INTC_LDPNIRR __REG_IT8152(0x3f00304)
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#define IT8152_INTC_LDCNIMR __REG_IT8152(0x3f00308)
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#define IT8152_INTC_LDPNIMR __REG_IT8152(0x3f0030C)
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#define IT8152_INTC_LDNITR __REG_IT8152(0x3f00310)
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#define IT8152_INTC_LDNIAR __REG_IT8152(0x3f00314)
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#define IT8152_INTC_LPCNIRR __REG_IT8152(0x3f00320)
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#define IT8152_INTC_LPPNIRR __REG_IT8152(0x3f00324)
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#define IT8152_INTC_LPCNIMR __REG_IT8152(0x3f00328)
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#define IT8152_INTC_LPPNIMR __REG_IT8152(0x3f0032C)
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#define IT8152_INTC_LPNITR __REG_IT8152(0x3f00330)
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#define IT8152_INTC_LPNIAR __REG_IT8152(0x3f00334)
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#define IT8152_INTC_PDCNIRR __REG_IT8152(0x3f00340)
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#define IT8152_INTC_PDPNIRR __REG_IT8152(0x3f00344)
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#define IT8152_INTC_PDCNIMR __REG_IT8152(0x3f00348)
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#define IT8152_INTC_PDPNIMR __REG_IT8152(0x3f0034C)
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#define IT8152_INTC_PDNITR __REG_IT8152(0x3f00350)
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#define IT8152_INTC_PDNIAR __REG_IT8152(0x3f00354)
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#define IT8152_INTC_INTC_TYPER __REG_IT8152(0x3f003FC)
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#define IT8152_GPIO_GPDR __REG_IT8152(0x3f00500)
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/*
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2008-02-03 07:50:59 -07:00
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Interrupt controller per register summary:
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2007-09-23 08:59:52 -06:00
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---------------------------------------
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LCDNIRR:
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IT8152_LD_IRQ(8) PCICLK stop
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IT8152_LD_IRQ(7) MCLK ready
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IT8152_LD_IRQ(6) s/w
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IT8152_LD_IRQ(5) UART
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IT8152_LD_IRQ(4) GPIO
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IT8152_LD_IRQ(3) TIMER 4
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IT8152_LD_IRQ(2) TIMER 3
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IT8152_LD_IRQ(1) TIMER 2
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IT8152_LD_IRQ(0) TIMER 1
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LPCNIRR:
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IT8152_LP_IRQ(x) serial IRQ x
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PCIDNIRR:
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IT8152_PD_IRQ(14) PCISERR
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IT8152_PD_IRQ(13) CPU/PCI bridge target abort (h2pTADR)
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IT8152_PD_IRQ(12) CPU/PCI bridge master abort (h2pMADR)
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IT8152_PD_IRQ(11) PCI INTD
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IT8152_PD_IRQ(10) PCI INTC
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IT8152_PD_IRQ(9) PCI INTB
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IT8152_PD_IRQ(8) PCI INTA
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IT8152_PD_IRQ(7) serial INTD
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IT8152_PD_IRQ(6) serial INTC
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IT8152_PD_IRQ(5) serial INTB
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IT8152_PD_IRQ(4) serial INTA
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IT8152_PD_IRQ(3) serial IRQ IOCHK (IOCHKR)
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IT8152_PD_IRQ(2) chaining DMA (CDMAR)
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IT8152_PD_IRQ(1) USB (USBR)
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IT8152_PD_IRQ(0) Audio controller (ACR)
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*/
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/* frequently used interrupts */
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#define IT8152_PCISERR IT8152_PD_IRQ(14)
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#define IT8152_H2PTADR IT8152_PD_IRQ(13)
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#define IT8152_H2PMAR IT8152_PD_IRQ(12)
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#define IT8152_PCI_INTD IT8152_PD_IRQ(11)
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#define IT8152_PCI_INTC IT8152_PD_IRQ(10)
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#define IT8152_PCI_INTB IT8152_PD_IRQ(9)
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#define IT8152_PCI_INTA IT8152_PD_IRQ(8)
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#define IT8152_CDMA_INT IT8152_PD_IRQ(2)
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#define IT8152_USB_INT IT8152_PD_IRQ(1)
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#define IT8152_AUDIO_INT IT8152_PD_IRQ(0)
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struct pci_dev;
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struct pci_sys_data;
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extern void it8152_irq_demux(unsigned int irq, struct irq_desc *desc);
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extern void it8152_init_irq(void);
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extern int it8152_pci_map_irq(struct pci_dev *dev, u8 slot, u8 pin);
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extern int it8152_pci_setup(int nr, struct pci_sys_data *sys);
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extern struct pci_bus *it8152_pci_scan_bus(int nr, struct pci_sys_data *sys);
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#endif /* __ASM_HARDWARE_IT8152_H */
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