2006-09-27 01:20:22 -06:00
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/*
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* Copyright (c) 2006 Andriy Skulysh <askulsyh@gmail.com>
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*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*
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*/
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#include <linux/linkage.h>
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2008-07-28 17:09:44 -06:00
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#include <cpu/mmu_context.h>
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2006-09-27 01:20:22 -06:00
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#define k0 r0
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#define k1 r1
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#define k2 r2
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#define k3 r3
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#define k4 r4
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/*
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* Kernel mode register usage:
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* k0 scratch
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* k1 scratch
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* k2 scratch (Exception code)
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* k3 scratch (Return address)
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* k4 scratch
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* k5 reserved
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* k6 Global Interrupt Mask (0--15 << 4)
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* k7 CURRENT_THREAD_INFO (pointer to current thread info)
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*/
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ENTRY(wakeup_start)
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! clear STBY bit
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mov #-126, k2
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and #127, k0
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mov.b k0, @k2
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! enable refresh
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mov.l 5f, k1
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mov.w 6f, k0
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mov.w k0, @k1
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! jump to handler
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mov.l 2f, k2
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mov.l 3f, k3
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mov.l @k2, k2
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mov.l 4f, k1
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jmp @k1
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nop
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.align 2
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1: .long EXPEVT
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2: .long INTEVT
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3: .long ret_from_irq
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4: .long handle_exception
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5: .long 0xffffff68
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6: .word 0x0524
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ENTRY(wakeup_end)
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nop
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