2008-03-18 02:02:50 -06:00
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#ifndef __ARCH_ARM_MACH_OMAP2_PRM_REGBITS_24XX_H
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#define __ARCH_ARM_MACH_OMAP2_PRM_REGBITS_24XX_H
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/*
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* OMAP24XX Power/Reset Management register bits
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*
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* Copyright (C) 2007 Texas Instruments, Inc.
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* Copyright (C) 2007 Nokia Corporation
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*
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* Written by Paul Walmsley
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include "prm.h"
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/* Bits shared between registers */
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/* PRCM_IRQSTATUS_MPU, PM_IRQSTATUS_DSP, PRCM_IRQSTATUS_IVA shared bits */
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#define OMAP24XX_VOLTTRANS_ST (1 << 2)
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#define OMAP24XX_WKUP2_ST (1 << 1)
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#define OMAP24XX_WKUP1_ST (1 << 0)
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/* PRCM_IRQENABLE_MPU, PM_IRQENABLE_DSP, PRCM_IRQENABLE_IVA shared bits */
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#define OMAP24XX_VOLTTRANS_EN (1 << 2)
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#define OMAP24XX_WKUP2_EN (1 << 1)
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#define OMAP24XX_WKUP1_EN (1 << 0)
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/* PM_WKDEP_GFX, PM_WKDEP_MPU, PM_WKDEP_DSP, PM_WKDEP_MDM shared bits */
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2008-08-19 02:08:42 -06:00
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#define OMAP24XX_EN_MPU_SHIFT 1
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#define OMAP24XX_EN_MPU_MASK (1 << 1)
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#define OMAP24XX_EN_CORE_SHIFT 0
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#define OMAP24XX_EN_CORE_MASK (1 << 0)
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2008-03-18 02:02:50 -06:00
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/*
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* PM_PWSTCTRL_MPU, PM_PWSTCTRL_GFX, PM_PWSTCTRL_DSP, PM_PWSTCTRL_MDM
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* shared bits
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*/
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#define OMAP24XX_MEMONSTATE_SHIFT 10
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#define OMAP24XX_MEMONSTATE_MASK (0x3 << 10)
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#define OMAP24XX_MEMRETSTATE (1 << 3)
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/* PM_PWSTCTRL_GFX, PM_PWSTCTRL_DSP, PM_PWSTCTRL_MDM shared bits */
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#define OMAP24XX_FORCESTATE (1 << 18)
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/*
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* PM_PWSTST_CORE, PM_PWSTST_GFX, PM_PWSTST_MPU, PM_PWSTST_DSP,
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* PM_PWSTST_MDM shared bits
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*/
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#define OMAP24XX_CLKACTIVITY (1 << 19)
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/* PM_PWSTST_MPU, PM_PWSTST_CORE, PM_PWSTST_DSP shared bits */
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#define OMAP24XX_LASTSTATEENTERED_SHIFT 4
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#define OMAP24XX_LASTSTATEENTERED_MASK (0x3 << 4)
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/* PM_PWSTST_MPU and PM_PWSTST_DSP shared bits */
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#define OMAP2430_MEMSTATEST_SHIFT 10
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#define OMAP2430_MEMSTATEST_MASK (0x3 << 10)
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/* PM_PWSTST_GFX, PM_PWSTST_DSP, PM_PWSTST_MDM shared bits */
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#define OMAP24XX_POWERSTATEST_SHIFT 0
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#define OMAP24XX_POWERSTATEST_MASK (0x3 << 0)
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/* Bits specific to each register */
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/* PRCM_REVISION */
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#define OMAP24XX_REV_SHIFT 0
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#define OMAP24XX_REV_MASK (0xff << 0)
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/* PRCM_SYSCONFIG */
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#define OMAP24XX_AUTOIDLE (1 << 0)
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/* PRCM_IRQSTATUS_MPU specific bits */
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#define OMAP2430_DPLL_RECAL_ST (1 << 6)
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#define OMAP24XX_TRANSITION_ST (1 << 5)
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#define OMAP24XX_EVGENOFF_ST (1 << 4)
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#define OMAP24XX_EVGENON_ST (1 << 3)
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/* PRCM_IRQENABLE_MPU specific bits */
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#define OMAP2430_DPLL_RECAL_EN (1 << 6)
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#define OMAP24XX_TRANSITION_EN (1 << 5)
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#define OMAP24XX_EVGENOFF_EN (1 << 4)
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#define OMAP24XX_EVGENON_EN (1 << 3)
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/* PRCM_VOLTCTRL */
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#define OMAP24XX_AUTO_EXTVOLT (1 << 15)
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#define OMAP24XX_FORCE_EXTVOLT (1 << 14)
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#define OMAP24XX_SETOFF_LEVEL_SHIFT 12
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#define OMAP24XX_SETOFF_LEVEL_MASK (0x3 << 12)
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#define OMAP24XX_MEMRETCTRL (1 << 8)
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#define OMAP24XX_SETRET_LEVEL_SHIFT 6
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#define OMAP24XX_SETRET_LEVEL_MASK (0x3 << 6)
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#define OMAP24XX_VOLT_LEVEL_SHIFT 0
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#define OMAP24XX_VOLT_LEVEL_MASK (0x3 << 0)
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/* PRCM_VOLTST */
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#define OMAP24XX_ST_VOLTLEVEL_SHIFT 0
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#define OMAP24XX_ST_VOLTLEVEL_MASK (0x3 << 0)
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/* PRCM_CLKSRC_CTRL specific bits */
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/* PRCM_CLKOUT_CTRL */
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#define OMAP2420_CLKOUT2_EN_SHIFT 15
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#define OMAP2420_CLKOUT2_EN (1 << 15)
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#define OMAP2420_CLKOUT2_DIV_SHIFT 11
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#define OMAP2420_CLKOUT2_DIV_MASK (0x7 << 11)
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#define OMAP2420_CLKOUT2_SOURCE_SHIFT 8
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#define OMAP2420_CLKOUT2_SOURCE_MASK (0x3 << 8)
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#define OMAP24XX_CLKOUT_EN_SHIFT 7
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#define OMAP24XX_CLKOUT_EN (1 << 7)
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#define OMAP24XX_CLKOUT_DIV_SHIFT 3
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#define OMAP24XX_CLKOUT_DIV_MASK (0x7 << 3)
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#define OMAP24XX_CLKOUT_SOURCE_SHIFT 0
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#define OMAP24XX_CLKOUT_SOURCE_MASK (0x3 << 0)
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/* PRCM_CLKEMUL_CTRL */
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#define OMAP24XX_EMULATION_EN_SHIFT 0
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#define OMAP24XX_EMULATION_EN (1 << 0)
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/* PRCM_CLKCFG_CTRL */
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#define OMAP24XX_VALID_CONFIG (1 << 0)
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/* PRCM_CLKCFG_STATUS */
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#define OMAP24XX_CONFIG_STATUS (1 << 0)
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/* PRCM_VOLTSETUP specific bits */
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/* PRCM_CLKSSETUP specific bits */
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/* PRCM_POLCTRL */
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#define OMAP2420_CLKOUT2_POL (1 << 10)
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#define OMAP24XX_CLKOUT_POL (1 << 9)
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#define OMAP24XX_CLKREQ_POL (1 << 8)
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#define OMAP2430_USE_POWEROK (1 << 2)
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#define OMAP2430_POWEROK_POL (1 << 1)
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#define OMAP24XX_EXTVOL_POL (1 << 0)
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/* RM_RSTST_MPU specific bits */
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/* 2430 calls GLOBALWMPU_RST "GLOBALWARM_RST" instead */
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/* PM_WKDEP_MPU specific bits */
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2008-08-19 02:08:42 -06:00
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#define OMAP2430_PM_WKDEP_MPU_EN_MDM_SHIFT 5
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#define OMAP2430_PM_WKDEP_MPU_EN_MDM_MASK (1 << 5)
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#define OMAP24XX_PM_WKDEP_MPU_EN_DSP_SHIFT 2
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#define OMAP24XX_PM_WKDEP_MPU_EN_DSP_MASK (1 << 2)
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2008-03-18 02:02:50 -06:00
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/* PM_EVGENCTRL_MPU specific bits */
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/* PM_EVEGENONTIM_MPU specific bits */
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/* PM_EVEGENOFFTIM_MPU specific bits */
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/* PM_PWSTCTRL_MPU specific bits */
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#define OMAP2430_FORCESTATE (1 << 18)
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/* PM_PWSTST_MPU specific bits */
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/* INTRANSITION, CLKACTIVITY, POWERSTATE, MEMSTATEST are 2430 only */
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/* PM_WKEN1_CORE specific bits */
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/* PM_WKEN2_CORE specific bits */
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/* PM_WKST1_CORE specific bits*/
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/* PM_WKST2_CORE specific bits */
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/* PM_WKDEP_CORE specific bits*/
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#define OMAP2430_PM_WKDEP_CORE_EN_MDM (1 << 5)
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#define OMAP24XX_PM_WKDEP_CORE_EN_GFX (1 << 3)
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#define OMAP24XX_PM_WKDEP_CORE_EN_DSP (1 << 2)
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/* PM_PWSTCTRL_CORE specific bits */
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#define OMAP24XX_MEMORYCHANGE (1 << 20)
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#define OMAP24XX_MEM3ONSTATE_SHIFT 14
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#define OMAP24XX_MEM3ONSTATE_MASK (0x3 << 14)
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#define OMAP24XX_MEM2ONSTATE_SHIFT 12
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#define OMAP24XX_MEM2ONSTATE_MASK (0x3 << 12)
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#define OMAP24XX_MEM1ONSTATE_SHIFT 10
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#define OMAP24XX_MEM1ONSTATE_MASK (0x3 << 10)
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#define OMAP24XX_MEM3RETSTATE (1 << 5)
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#define OMAP24XX_MEM2RETSTATE (1 << 4)
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#define OMAP24XX_MEM1RETSTATE (1 << 3)
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/* PM_PWSTST_CORE specific bits */
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#define OMAP24XX_MEM3STATEST_SHIFT 14
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#define OMAP24XX_MEM3STATEST_MASK (0x3 << 14)
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#define OMAP24XX_MEM2STATEST_SHIFT 12
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#define OMAP24XX_MEM2STATEST_MASK (0x3 << 12)
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#define OMAP24XX_MEM1STATEST_SHIFT 10
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#define OMAP24XX_MEM1STATEST_MASK (0x3 << 10)
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/* RM_RSTCTRL_GFX */
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#define OMAP24XX_GFX_RST (1 << 0)
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/* RM_RSTST_GFX specific bits */
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#define OMAP24XX_GFX_SW_RST (1 << 4)
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/* PM_PWSTCTRL_GFX specific bits */
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/* PM_WKDEP_GFX specific bits */
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/* 2430 often calls EN_WAKEUP "EN_WKUP" */
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/* RM_RSTCTRL_WKUP specific bits */
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/* RM_RSTTIME_WKUP specific bits */
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/* RM_RSTST_WKUP specific bits */
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/* 2430 calls EXTWMPU_RST "EXTWARM_RST" and GLOBALWMPU_RST "GLOBALWARM_RST" */
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#define OMAP24XX_EXTWMPU_RST (1 << 6)
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#define OMAP24XX_SECU_WD_RST (1 << 5)
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#define OMAP24XX_MPU_WD_RST (1 << 4)
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#define OMAP24XX_SECU_VIOL_RST (1 << 3)
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/* PM_WKEN_WKUP specific bits */
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/* PM_WKST_WKUP specific bits */
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/* RM_RSTCTRL_DSP */
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#define OMAP2420_RST_IVA (1 << 8)
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#define OMAP24XX_RST2_DSP (1 << 1)
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#define OMAP24XX_RST1_DSP (1 << 0)
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/* RM_RSTST_DSP specific bits */
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/* 2430 calls GLOBALWMPU_RST "GLOBALWARM_RST" */
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#define OMAP2420_IVA_SW_RST (1 << 8)
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#define OMAP24XX_DSP_SW_RST2 (1 << 5)
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#define OMAP24XX_DSP_SW_RST1 (1 << 4)
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/* PM_WKDEP_DSP specific bits */
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/* PM_PWSTCTRL_DSP specific bits */
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/* 2430 only: MEMONSTATE, MEMRETSTATE */
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#define OMAP2420_MEMIONSTATE_SHIFT 12
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#define OMAP2420_MEMIONSTATE_MASK (0x3 << 12)
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#define OMAP2420_MEMIRETSTATE (1 << 4)
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/* PM_PWSTST_DSP specific bits */
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/* MEMSTATEST is 2430 only */
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#define OMAP2420_MEMISTATEST_SHIFT 12
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#define OMAP2420_MEMISTATEST_MASK (0x3 << 12)
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/* PRCM_IRQSTATUS_DSP specific bits */
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/* PRCM_IRQENABLE_DSP specific bits */
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/* RM_RSTCTRL_MDM */
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/* 2430 only */
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#define OMAP2430_PWRON1_MDM (1 << 1)
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#define OMAP2430_RST1_MDM (1 << 0)
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/* RM_RSTST_MDM specific bits */
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/* 2430 only */
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#define OMAP2430_MDM_SECU_VIOL (1 << 6)
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#define OMAP2430_MDM_SW_PWRON1 (1 << 5)
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#define OMAP2430_MDM_SW_RST1 (1 << 4)
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/* PM_WKEN_MDM */
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/* 2430 only */
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#define OMAP2430_PM_WKEN_MDM_EN_MDM (1 << 0)
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/* PM_WKST_MDM specific bits */
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/* 2430 only */
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/* PM_WKDEP_MDM specific bits */
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/* 2430 only */
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/* PM_PWSTCTRL_MDM specific bits */
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/* 2430 only */
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#define OMAP2430_KILLDOMAINWKUP (1 << 19)
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/* PM_PWSTST_MDM specific bits */
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/* 2430 only */
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/* PRCM_IRQSTATUS_IVA */
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/* 2420 only */
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/* PRCM_IRQENABLE_IVA */
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/* 2420 only */
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#endif
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