407 lines
20 KiB
C
407 lines
20 KiB
C
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/* $Id: esp.h,v 1.29 2001/12/11 04:55:47 davem Exp $
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* esp.h: Defines and structures for the Sparc ESP (Enhanced SCSI
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* Processor) driver under Linux.
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*
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* Copyright (C) 1995 David S. Miller (davem@caip.rutgers.edu)
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*/
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#ifndef _SPARC_ESP_H
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#define _SPARC_ESP_H
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/* For dvma controller register definitions. */
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#include <asm/dma.h>
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/* The ESP SCSI controllers have their register sets in three
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* "classes":
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*
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* 1) Registers which are both read and write.
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* 2) Registers which are read only.
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* 3) Registers which are write only.
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*
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* Yet, they all live within the same IO space.
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*/
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/* All the ESP registers are one byte each and are accessed longwords
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* apart with a big-endian ordering to the bytes.
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*/
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/* Access Description Offset */
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#define ESP_TCLOW 0x00UL /* rw Low bits of the transfer count 0x00 */
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#define ESP_TCMED 0x04UL /* rw Mid bits of the transfer count 0x04 */
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#define ESP_FDATA 0x08UL /* rw FIFO data bits 0x08 */
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#define ESP_CMD 0x0cUL /* rw SCSI command bits 0x0c */
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#define ESP_STATUS 0x10UL /* ro ESP status register 0x10 */
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#define ESP_BUSID ESP_STATUS /* wo Bus ID for select/reselect 0x10 */
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#define ESP_INTRPT 0x14UL /* ro Kind of interrupt 0x14 */
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#define ESP_TIMEO ESP_INTRPT /* wo Timeout value for select/resel 0x14 */
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#define ESP_SSTEP 0x18UL /* ro Sequence step register 0x18 */
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#define ESP_STP ESP_SSTEP /* wo Transfer period per sync 0x18 */
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#define ESP_FFLAGS 0x1cUL /* ro Bits of current FIFO info 0x1c */
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#define ESP_SOFF ESP_FFLAGS /* wo Sync offset 0x1c */
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#define ESP_CFG1 0x20UL /* rw First configuration register 0x20 */
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#define ESP_CFACT 0x24UL /* wo Clock conversion factor 0x24 */
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#define ESP_STATUS2 ESP_CFACT /* ro HME status2 register 0x24 */
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#define ESP_CTEST 0x28UL /* wo Chip test register 0x28 */
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#define ESP_CFG2 0x2cUL /* rw Second configuration register 0x2c */
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#define ESP_CFG3 0x30UL /* rw Third configuration register 0x30 */
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#define ESP_TCHI 0x38UL /* rw High bits of transfer count 0x38 */
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#define ESP_UID ESP_TCHI /* ro Unique ID code 0x38 */
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#define FAS_RLO ESP_TCHI /* rw HME extended counter 0x38 */
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#define ESP_FGRND 0x3cUL /* rw Data base for fifo 0x3c */
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#define FAS_RHI ESP_FGRND /* rw HME extended counter 0x3c */
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#define ESP_REG_SIZE 0x40UL
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/* Various revisions of the ESP board. */
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enum esp_rev {
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esp100 = 0x00, /* NCR53C90 - very broken */
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esp100a = 0x01, /* NCR53C90A */
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esp236 = 0x02,
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fas236 = 0x03,
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fas100a = 0x04,
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fast = 0x05,
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fashme = 0x06,
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espunknown = 0x07
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};
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/* We allocate one of these for each scsi device and attach it to
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* SDptr->hostdata for use in the driver
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*/
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struct esp_device {
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unsigned char sync_min_period;
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unsigned char sync_max_offset;
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unsigned sync:1;
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unsigned wide:1;
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unsigned disconnect:1;
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};
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struct scsi_cmnd;
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/* We get one of these for each ESP probed. */
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struct esp {
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void __iomem *eregs; /* ESP controller registers */
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void __iomem *dregs; /* DMA controller registers */
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struct sbus_dma *dma; /* DMA controller sw state */
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struct Scsi_Host *ehost; /* Backpointer to SCSI Host */
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struct sbus_dev *sdev; /* Pointer to SBus entry */
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/* ESP Configuration Registers */
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u8 config1; /* Copy of the 1st config register */
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u8 config2; /* Copy of the 2nd config register */
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u8 config3[16]; /* Copy of the 3rd config register */
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/* The current command we are sending to the ESP chip. This esp_command
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* ptr needs to be mapped in DVMA area so we can send commands and read
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* from the ESP fifo without burning precious CPU cycles. Programmed I/O
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* sucks when we have the DVMA to do it for us. The ESP is stupid and will
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* only send out 6, 10, and 12 byte SCSI commands, others we need to send
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* one byte at a time. esp_slowcmd being set says that we are doing one
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* of the command types ESP doesn't understand, esp_scmdp keeps track of
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* which byte we are sending, esp_scmdleft says how many bytes to go.
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*/
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volatile u8 *esp_command; /* Location of command (CPU view) */
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__u32 esp_command_dvma;/* Location of command (DVMA view) */
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unsigned char esp_clen; /* Length of this command */
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unsigned char esp_slowcmd;
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unsigned char *esp_scmdp;
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unsigned char esp_scmdleft;
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/* The following are used to determine the cause of an IRQ. Upon every
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* IRQ entry we synchronize these with the hardware registers.
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*/
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u8 ireg; /* Copy of ESP interrupt register */
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u8 sreg; /* Copy of ESP status register */
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u8 seqreg; /* Copy of ESP sequence step register */
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u8 sreg2; /* Copy of HME status2 register */
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/* To save register writes to the ESP, which can be expensive, we
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* keep track of the previous value that various registers had for
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* the last target we connected to. If they are the same for the
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* current target, we skip the register writes as they are not needed.
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*/
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u8 prev_soff, prev_stp;
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u8 prev_cfg3, __cache_pad;
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/* We also keep a cache of the previous FAS/HME DMA CSR register value. */
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u32 prev_hme_dmacsr;
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/* The HME is the biggest piece of shit I have ever seen. */
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u8 hme_fifo_workaround_buffer[16 * 2];
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u8 hme_fifo_workaround_count;
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/* For each target we keep track of save/restore data
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* pointer information. This needs to be updated majorly
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* when we add support for tagged queueing. -DaveM
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*/
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struct esp_pointers {
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char *saved_ptr;
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struct scatterlist *saved_buffer;
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int saved_this_residual;
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int saved_buffers_residual;
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} data_pointers[16] /*XXX [MAX_TAGS_PER_TARGET]*/;
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/* Clock periods, frequencies, synchronization, etc. */
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unsigned int cfreq; /* Clock frequency in HZ */
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unsigned int cfact; /* Clock conversion factor */
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unsigned int raw_cfact; /* Raw copy from probing */
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unsigned int ccycle; /* One ESP clock cycle */
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unsigned int ctick; /* One ESP clock time */
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unsigned int radelay; /* FAST chip req/ack delay */
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unsigned int neg_defp; /* Default negotiation period */
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unsigned int sync_defp; /* Default sync transfer period */
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unsigned int max_period; /* longest our period can be */
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unsigned int min_period; /* shortest period we can withstand */
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struct esp *next; /* Next ESP we probed or NULL */
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char prom_name[64]; /* Name of ESP device from prom */
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int prom_node; /* Prom node where ESP found */
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int esp_id; /* Unique per-ESP ID number */
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/* For slow to medium speed input clock rates we shoot for 5mb/s,
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* but for high input clock rates we try to do 10mb/s although I
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* don't think a transfer can even run that fast with an ESP even
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* with DMA2 scatter gather pipelining.
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*/
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#define SYNC_DEFP_SLOW 0x32 /* 5mb/s */
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#define SYNC_DEFP_FAST 0x19 /* 10mb/s */
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unsigned int snip; /* Sync. negotiation in progress */
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unsigned int wnip; /* WIDE negotiation in progress */
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unsigned int targets_present;/* targets spoken to before */
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int current_transfer_size; /* Set at beginning of data dma */
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u8 espcmdlog[32]; /* Log of current esp cmds sent. */
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u8 espcmdent; /* Current entry in esp cmd log. */
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/* Misc. info about this ESP */
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enum esp_rev erev; /* ESP revision */
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int irq; /* SBus IRQ for this ESP */
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int scsi_id; /* Who am I as initiator? */
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int scsi_id_mask; /* Bitmask of 'me'. */
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int diff; /* Differential SCSI bus? */
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int bursts; /* Burst sizes our DVMA supports */
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/* Our command queues, only one cmd lives in the current_SC queue. */
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struct scsi_cmnd *issue_SC; /* Commands to be issued */
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struct scsi_cmnd *current_SC; /* Who is currently working the bus */
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struct scsi_cmnd *disconnected_SC;/* Commands disconnected from the bus */
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/* Message goo */
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u8 cur_msgout[16];
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u8 cur_msgin[16];
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u8 prevmsgout, prevmsgin;
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u8 msgout_len, msgin_len;
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u8 msgout_ctr, msgin_ctr;
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/* States that we cannot keep in the per cmd structure because they
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* cannot be assosciated with any specific command.
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*/
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u8 resetting_bus;
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wait_queue_head_t reset_queue;
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};
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/* Bitfield meanings for the above registers. */
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/* ESP config reg 1, read-write, found on all ESP chips */
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#define ESP_CONFIG1_ID 0x07 /* My BUS ID bits */
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#define ESP_CONFIG1_CHTEST 0x08 /* Enable ESP chip tests */
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#define ESP_CONFIG1_PENABLE 0x10 /* Enable parity checks */
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#define ESP_CONFIG1_PARTEST 0x20 /* Parity test mode enabled? */
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#define ESP_CONFIG1_SRRDISAB 0x40 /* Disable SCSI reset reports */
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#define ESP_CONFIG1_SLCABLE 0x80 /* Enable slow cable mode */
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/* ESP config reg 2, read-write, found only on esp100a+esp200+esp236 chips */
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#define ESP_CONFIG2_DMAPARITY 0x01 /* enable DMA Parity (200,236) */
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#define ESP_CONFIG2_REGPARITY 0x02 /* enable reg Parity (200,236) */
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#define ESP_CONFIG2_BADPARITY 0x04 /* Bad parity target abort */
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#define ESP_CONFIG2_SCSI2ENAB 0x08 /* Enable SCSI-2 features (tmode only) */
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#define ESP_CONFIG2_HI 0x10 /* High Impedance DREQ ??? */
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#define ESP_CONFIG2_HMEFENAB 0x10 /* HME features enable */
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#define ESP_CONFIG2_BCM 0x20 /* Enable byte-ctrl (236) */
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#define ESP_CONFIG2_DISPINT 0x20 /* Disable pause irq (hme) */
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#define ESP_CONFIG2_FENAB 0x40 /* Enable features (fas100,esp216) */
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#define ESP_CONFIG2_SPL 0x40 /* Enable status-phase latch (esp236) */
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#define ESP_CONFIG2_MKDONE 0x40 /* HME magic feature */
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#define ESP_CONFIG2_HME32 0x80 /* HME 32 extended */
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#define ESP_CONFIG2_MAGIC 0xe0 /* Invalid bits... */
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/* ESP config register 3 read-write, found only esp236+fas236+fas100a+hme chips */
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#define ESP_CONFIG3_FCLOCK 0x01 /* FAST SCSI clock rate (esp100a/hme) */
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#define ESP_CONFIG3_TEM 0x01 /* Enable thresh-8 mode (esp/fas236) */
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#define ESP_CONFIG3_FAST 0x02 /* Enable FAST SCSI (esp100a/hme) */
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#define ESP_CONFIG3_ADMA 0x02 /* Enable alternate-dma (esp/fas236) */
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#define ESP_CONFIG3_TENB 0x04 /* group2 SCSI2 support (esp100a/hme) */
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#define ESP_CONFIG3_SRB 0x04 /* Save residual byte (esp/fas236) */
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#define ESP_CONFIG3_TMS 0x08 /* Three-byte msg's ok (esp100a/hme) */
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#define ESP_CONFIG3_FCLK 0x08 /* Fast SCSI clock rate (esp/fas236) */
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#define ESP_CONFIG3_IDMSG 0x10 /* ID message checking (esp100a/hme) */
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#define ESP_CONFIG3_FSCSI 0x10 /* Enable FAST SCSI (esp/fas236) */
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#define ESP_CONFIG3_GTM 0x20 /* group2 SCSI2 support (esp/fas236) */
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#define ESP_CONFIG3_IDBIT3 0x20 /* Bit 3 of HME SCSI-ID (hme) */
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#define ESP_CONFIG3_TBMS 0x40 /* Three-byte msg's ok (esp/fas236) */
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#define ESP_CONFIG3_EWIDE 0x40 /* Enable Wide-SCSI (hme) */
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#define ESP_CONFIG3_IMS 0x80 /* ID msg chk'ng (esp/fas236) */
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#define ESP_CONFIG3_OBPUSH 0x80 /* Push odd-byte to dma (hme) */
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/* ESP command register read-write */
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/* Group 1 commands: These may be sent at any point in time to the ESP
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* chip. None of them can generate interrupts 'cept
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* the "SCSI bus reset" command if you have not disabled
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* SCSI reset interrupts in the config1 ESP register.
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*/
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#define ESP_CMD_NULL 0x00 /* Null command, ie. a nop */
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#define ESP_CMD_FLUSH 0x01 /* FIFO Flush */
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#define ESP_CMD_RC 0x02 /* Chip reset */
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#define ESP_CMD_RS 0x03 /* SCSI bus reset */
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/* Group 2 commands: ESP must be an initiator and connected to a target
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* for these commands to work.
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*/
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#define ESP_CMD_TI 0x10 /* Transfer Information */
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#define ESP_CMD_ICCSEQ 0x11 /* Initiator cmd complete sequence */
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#define ESP_CMD_MOK 0x12 /* Message okie-dokie */
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#define ESP_CMD_TPAD 0x18 /* Transfer Pad */
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#define ESP_CMD_SATN 0x1a /* Set ATN */
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#define ESP_CMD_RATN 0x1b /* De-assert ATN */
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/* Group 3 commands: ESP must be in the MSGOUT or MSGIN state and be connected
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* to a target as the initiator for these commands to work.
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*/
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#define ESP_CMD_SMSG 0x20 /* Send message */
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#define ESP_CMD_SSTAT 0x21 /* Send status */
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#define ESP_CMD_SDATA 0x22 /* Send data */
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#define ESP_CMD_DSEQ 0x23 /* Discontinue Sequence */
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#define ESP_CMD_TSEQ 0x24 /* Terminate Sequence */
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#define ESP_CMD_TCCSEQ 0x25 /* Target cmd cmplt sequence */
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#define ESP_CMD_DCNCT 0x27 /* Disconnect */
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#define ESP_CMD_RMSG 0x28 /* Receive Message */
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#define ESP_CMD_RCMD 0x29 /* Receive Command */
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#define ESP_CMD_RDATA 0x2a /* Receive Data */
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#define ESP_CMD_RCSEQ 0x2b /* Receive cmd sequence */
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/* Group 4 commands: The ESP must be in the disconnected state and must
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* not be connected to any targets as initiator for
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* these commands to work.
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*/
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#define ESP_CMD_RSEL 0x40 /* Reselect */
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#define ESP_CMD_SEL 0x41 /* Select w/o ATN */
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#define ESP_CMD_SELA 0x42 /* Select w/ATN */
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#define ESP_CMD_SELAS 0x43 /* Select w/ATN & STOP */
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#define ESP_CMD_ESEL 0x44 /* Enable selection */
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#define ESP_CMD_DSEL 0x45 /* Disable selections */
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#define ESP_CMD_SA3 0x46 /* Select w/ATN3 */
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#define ESP_CMD_RSEL3 0x47 /* Reselect3 */
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/* This bit enables the ESP's DMA on the SBus */
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#define ESP_CMD_DMA 0x80 /* Do DMA? */
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/* ESP status register read-only */
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#define ESP_STAT_PIO 0x01 /* IO phase bit */
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#define ESP_STAT_PCD 0x02 /* CD phase bit */
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#define ESP_STAT_PMSG 0x04 /* MSG phase bit */
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#define ESP_STAT_PMASK 0x07 /* Mask of phase bits */
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#define ESP_STAT_TDONE 0x08 /* Transfer Completed */
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#define ESP_STAT_TCNT 0x10 /* Transfer Counter Is Zero */
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#define ESP_STAT_PERR 0x20 /* Parity error */
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#define ESP_STAT_SPAM 0x40 /* Real bad error */
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/* This indicates the 'interrupt pending' condition on esp236, it is a reserved
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* bit on other revs of the ESP.
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*/
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#define ESP_STAT_INTR 0x80 /* Interrupt */
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/* HME only: status 2 register */
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#define ESP_STAT2_SCHBIT 0x01 /* Upper bits 3-7 of sstep enabled */
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#define ESP_STAT2_FFLAGS 0x02 /* The fifo flags are now latched */
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#define ESP_STAT2_XCNT 0x04 /* The transfer counter is latched */
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#define ESP_STAT2_CREGA 0x08 /* The command reg is active now */
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#define ESP_STAT2_WIDE 0x10 /* Interface on this adapter is wide */
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#define ESP_STAT2_F1BYTE 0x20 /* There is one byte at top of fifo */
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#define ESP_STAT2_FMSB 0x40 /* Next byte in fifo is most significant */
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#define ESP_STAT2_FEMPTY 0x80 /* FIFO is empty */
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/* The status register can be masked with ESP_STAT_PMASK and compared
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* with the following values to determine the current phase the ESP
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* (at least thinks it) is in. For our purposes we also add our own
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* software 'done' bit for our phase management engine.
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*/
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#define ESP_DOP (0) /* Data Out */
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#define ESP_DIP (ESP_STAT_PIO) /* Data In */
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#define ESP_CMDP (ESP_STAT_PCD) /* Command */
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#define ESP_STATP (ESP_STAT_PCD|ESP_STAT_PIO) /* Status */
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#define ESP_MOP (ESP_STAT_PMSG|ESP_STAT_PCD) /* Message Out */
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#define ESP_MIP (ESP_STAT_PMSG|ESP_STAT_PCD|ESP_STAT_PIO) /* Message In */
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/* ESP interrupt register read-only */
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#define ESP_INTR_S 0x01 /* Select w/o ATN */
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#define ESP_INTR_SATN 0x02 /* Select w/ATN */
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#define ESP_INTR_RSEL 0x04 /* Reselected */
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#define ESP_INTR_FDONE 0x08 /* Function done */
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#define ESP_INTR_BSERV 0x10 /* Bus service */
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#define ESP_INTR_DC 0x20 /* Disconnect */
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||
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#define ESP_INTR_IC 0x40 /* Illegal command given */
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#define ESP_INTR_SR 0x80 /* SCSI bus reset detected */
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||
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||
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/* Interrupt status macros */
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||
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#define ESP_SRESET_IRQ(esp) ((esp)->intreg & (ESP_INTR_SR))
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||
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#define ESP_ILLCMD_IRQ(esp) ((esp)->intreg & (ESP_INTR_IC))
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||
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#define ESP_SELECT_WITH_ATN_IRQ(esp) ((esp)->intreg & (ESP_INTR_SATN))
|
||
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|
#define ESP_SELECT_WITHOUT_ATN_IRQ(esp) ((esp)->intreg & (ESP_INTR_S))
|
||
|
|
#define ESP_SELECTION_IRQ(esp) ((ESP_SELECT_WITH_ATN_IRQ(esp)) || \
|
||
|
|
(ESP_SELECT_WITHOUT_ATN_IRQ(esp)))
|
||
|
|
#define ESP_RESELECTION_IRQ(esp) ((esp)->intreg & (ESP_INTR_RSEL))
|
||
|
|
|
||
|
|
/* ESP sequence step register read-only */
|
||
|
|
#define ESP_STEP_VBITS 0x07 /* Valid bits */
|
||
|
|
#define ESP_STEP_ASEL 0x00 /* Selection&Arbitrate cmplt */
|
||
|
|
#define ESP_STEP_SID 0x01 /* One msg byte sent */
|
||
|
|
#define ESP_STEP_NCMD 0x02 /* Was not in command phase */
|
||
|
|
#define ESP_STEP_PPC 0x03 /* Early phase chg caused cmnd
|
||
|
|
* bytes to be lost
|
||
|
|
*/
|
||
|
|
#define ESP_STEP_FINI4 0x04 /* Command was sent ok */
|
||
|
|
|
||
|
|
/* Ho hum, some ESP's set the step register to this as well... */
|
||
|
|
#define ESP_STEP_FINI5 0x05
|
||
|
|
#define ESP_STEP_FINI6 0x06
|
||
|
|
#define ESP_STEP_FINI7 0x07
|
||
|
|
|
||
|
|
/* ESP chip-test register read-write */
|
||
|
|
#define ESP_TEST_TARG 0x01 /* Target test mode */
|
||
|
|
#define ESP_TEST_INI 0x02 /* Initiator test mode */
|
||
|
|
#define ESP_TEST_TS 0x04 /* Tristate test mode */
|
||
|
|
|
||
|
|
/* ESP unique ID register read-only, found on fas236+fas100a only */
|
||
|
|
#define ESP_UID_F100A 0x00 /* ESP FAS100A */
|
||
|
|
#define ESP_UID_F236 0x02 /* ESP FAS236 */
|
||
|
|
#define ESP_UID_REV 0x07 /* ESP revision */
|
||
|
|
#define ESP_UID_FAM 0xf8 /* ESP family */
|
||
|
|
|
||
|
|
/* ESP fifo flags register read-only */
|
||
|
|
/* Note that the following implies a 16 byte FIFO on the ESP. */
|
||
|
|
#define ESP_FF_FBYTES 0x1f /* Num bytes in FIFO */
|
||
|
|
#define ESP_FF_ONOTZERO 0x20 /* offset ctr not zero (esp100) */
|
||
|
|
#define ESP_FF_SSTEP 0xe0 /* Sequence step */
|
||
|
|
|
||
|
|
/* ESP clock conversion factor register write-only */
|
||
|
|
#define ESP_CCF_F0 0x00 /* 35.01MHz - 40MHz */
|
||
|
|
#define ESP_CCF_NEVER 0x01 /* Set it to this and die */
|
||
|
|
#define ESP_CCF_F2 0x02 /* 10MHz */
|
||
|
|
#define ESP_CCF_F3 0x03 /* 10.01MHz - 15MHz */
|
||
|
|
#define ESP_CCF_F4 0x04 /* 15.01MHz - 20MHz */
|
||
|
|
#define ESP_CCF_F5 0x05 /* 20.01MHz - 25MHz */
|
||
|
|
#define ESP_CCF_F6 0x06 /* 25.01MHz - 30MHz */
|
||
|
|
#define ESP_CCF_F7 0x07 /* 30.01MHz - 35MHz */
|
||
|
|
|
||
|
|
/* HME only... */
|
||
|
|
#define ESP_BUSID_RESELID 0x10
|
||
|
|
#define ESP_BUSID_CTR32BIT 0x40
|
||
|
|
|
||
|
|
#define ESP_BUS_TIMEOUT 275 /* In milli-seconds */
|
||
|
|
#define ESP_TIMEO_CONST 8192
|
||
|
|
#define ESP_NEG_DEFP(mhz, cfact) \
|
||
|
|
((ESP_BUS_TIMEOUT * ((mhz) / 1000)) / (8192 * (cfact)))
|
||
|
|
#define ESP_MHZ_TO_CYCLE(mhertz) ((1000000000) / ((mhertz) / 1000))
|
||
|
|
#define ESP_TICK(ccf, cycle) ((7682 * (ccf) * (cycle) / 1000))
|
||
|
|
|
||
|
|
#endif /* !(_SPARC_ESP_H) */
|