413 lines
7.6 KiB
ArmAsm
413 lines
7.6 KiB
ArmAsm
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#include <asm/reg.h>
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#include <asm/ppc_asm.h>
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#include <asm/processor.h>
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#include <asm/cache.h>
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#define SDRAM_CTRL 0x104
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#define SC_MODE_EN (1<<31)
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#define SC_CKE (1<<30)
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#define SC_REF_EN (1<<28)
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#define SC_SOFT_PRE (1<<1)
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#define GPIOW_GPIOE 0xc00
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#define GPIOW_DDR 0xc08
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#define GPIOW_DVO 0xc0c
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#define CDM_CE 0x214
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#define CDM_SDRAM (1<<3)
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/* helpers... beware: r10 and r4 are overwritten */
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#define SAVE_SPRN(reg, addr) \
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mfspr r10, SPRN_##reg; \
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stw r10, ((addr)*4)(r4);
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#define LOAD_SPRN(reg, addr) \
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lwz r10, ((addr)*4)(r4); \
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mtspr SPRN_##reg, r10; \
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sync; \
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isync;
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.data
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registers:
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.space 0x5c*4
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.text
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/* ---------------------------------------------------------------------- */
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/* low-power mode with help of M68HLC908QT1 */
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.globl lite5200_low_power
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lite5200_low_power:
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mr r7, r3 /* save SRAM va */
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mr r8, r4 /* save MBAR va */
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/* setup wakeup address for u-boot at physical location 0x0 */
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lis r3, CONFIG_KERNEL_START@h
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lis r4, lite5200_wakeup@h
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ori r4, r4, lite5200_wakeup@l
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sub r4, r4, r3
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stw r4, 0(r3)
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/*
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* save stuff BDI overwrites
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* 0xf0 (0xe0->0x100 gets overwritten when BDI connected;
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* even when CONFIG_BDI* is disabled and MMU XLAT commented; heisenbug?))
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* WARNING: self-refresh doesn't seem to work when BDI2000 is connected,
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* possibly because BDI sets SDRAM registers before wakeup code does
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*/
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lis r4, registers@h
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ori r4, r4, registers@l
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lwz r10, 0xf0(r3)
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stw r10, (0x1d*4)(r4)
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/* save registers to r4 [destroys r10] */
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SAVE_SPRN(LR, 0x1c)
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bl save_regs
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/* flush caches [destroys r3, r4] */
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bl flush_data_cache
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/* copy code to sram */
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mr r4, r7
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li r3, (sram_code_end - sram_code)/4
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mtctr r3
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lis r3, sram_code@h
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ori r3, r3, sram_code@l
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1:
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lwz r5, 0(r3)
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stw r5, 0(r4)
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addi r3, r3, 4
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addi r4, r4, 4
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bdnz 1b
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/* get tb_ticks_per_usec */
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lis r3, tb_ticks_per_usec@h
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lwz r11, tb_ticks_per_usec@l(r3)
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/* disable I and D caches */
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mfspr r3, SPRN_HID0
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ori r3, r3, HID0_ICE | HID0_DCE
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xori r3, r3, HID0_ICE | HID0_DCE
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sync; isync;
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mtspr SPRN_HID0, r3
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sync; isync;
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/* jump to sram */
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mtlr r7
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blrl
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/* doesn't return */
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sram_code:
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/* self refresh */
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lwz r4, SDRAM_CTRL(r8)
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/* send NOP (precharge) */
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oris r4, r4, SC_MODE_EN@h /* mode_en */
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stw r4, SDRAM_CTRL(r8)
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sync
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ori r4, r4, SC_SOFT_PRE /* soft_pre */
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stw r4, SDRAM_CTRL(r8)
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sync
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xori r4, r4, SC_SOFT_PRE
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xoris r4, r4, SC_MODE_EN@h /* !mode_en */
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stw r4, SDRAM_CTRL(r8)
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sync
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/* delay (for NOP to finish) */
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li r12, 1
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bl udelay
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/*
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* mode_en must not be set when enabling self-refresh
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* send AR with CKE low (self-refresh)
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*/
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oris r4, r4, (SC_REF_EN | SC_CKE)@h
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xoris r4, r4, (SC_CKE)@h /* ref_en !cke */
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stw r4, SDRAM_CTRL(r8)
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sync
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/* delay (after !CKE there should be two cycles) */
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li r12, 1
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bl udelay
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/* disable clock */
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lwz r4, CDM_CE(r8)
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ori r4, r4, CDM_SDRAM
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xori r4, r4, CDM_SDRAM
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stw r4, CDM_CE(r8)
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sync
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/* delay a bit */
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li r12, 1
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bl udelay
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/* turn off with QT chip */
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li r4, 0x02
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stb r4, GPIOW_GPIOE(r8) /* enable gpio_wkup1 */
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sync
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stb r4, GPIOW_DVO(r8) /* "output" high */
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sync
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stb r4, GPIOW_DDR(r8) /* output */
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sync
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stb r4, GPIOW_DVO(r8) /* output high */
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sync
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/* 10uS delay */
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li r12, 10
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bl udelay
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/* turn off */
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li r4, 0
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stb r4, GPIOW_DVO(r8) /* output low */
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sync
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/* wait until we're offline */
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1:
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b 1b
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/* local udelay in sram is needed */
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udelay: /* r11 - tb_ticks_per_usec, r12 - usecs, overwrites r13 */
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mullw r12, r12, r11
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mftb r13 /* start */
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addi r12, r13, r12 /* end */
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1:
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mftb r13 /* current */
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cmp cr0, r13, r12
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blt 1b
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blr
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sram_code_end:
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/* uboot jumps here on resume */
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lite5200_wakeup:
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bl restore_regs
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/* HIDs, MSR */
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LOAD_SPRN(HID1, 0x19)
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LOAD_SPRN(HID2, 0x1a)
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/* address translation is tricky (see turn_on_mmu) */
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mfmsr r10
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ori r10, r10, MSR_DR | MSR_IR
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mtspr SPRN_SRR1, r10
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lis r10, mmu_on@h
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ori r10, r10, mmu_on@l
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mtspr SPRN_SRR0, r10
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sync
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rfi
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mmu_on:
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/* kernel offset (r4 is still set from restore_registers) */
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addis r4, r4, CONFIG_KERNEL_START@h
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/* restore MSR */
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lwz r10, (4*0x1b)(r4)
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mtmsr r10
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sync; isync;
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/* invalidate caches */
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mfspr r10, SPRN_HID0
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ori r5, r10, HID0_ICFI | HID0_DCI
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mtspr SPRN_HID0, r5 /* invalidate caches */
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sync; isync;
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mtspr SPRN_HID0, r10
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sync; isync;
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/* enable caches */
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lwz r10, (4*0x18)(r4)
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mtspr SPRN_HID0, r10 /* restore (enable caches, DPM) */
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/* ^ this has to be after address translation set in MSR */
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sync
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isync
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/* restore 0xf0 (BDI2000) */
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lis r3, CONFIG_KERNEL_START@h
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lwz r10, (0x1d*4)(r4)
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stw r10, 0xf0(r3)
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LOAD_SPRN(LR, 0x1c)
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blr
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/* ---------------------------------------------------------------------- */
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/* boring code: helpers */
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/* save registers */
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#define SAVE_BAT(n, addr) \
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SAVE_SPRN(DBAT##n##L, addr); \
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SAVE_SPRN(DBAT##n##U, addr+1); \
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SAVE_SPRN(IBAT##n##L, addr+2); \
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SAVE_SPRN(IBAT##n##U, addr+3);
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#define SAVE_SR(n, addr) \
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mfsr r10, n; \
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stw r10, ((addr)*4)(r4);
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#define SAVE_4SR(n, addr) \
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SAVE_SR(n, addr); \
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SAVE_SR(n+1, addr+1); \
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SAVE_SR(n+2, addr+2); \
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SAVE_SR(n+3, addr+3);
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save_regs:
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stw r0, 0(r4)
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stw r1, 0x4(r4)
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stw r2, 0x8(r4)
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stmw r11, 0xc(r4) /* 0xc -> 0x5f, (0x18*4-1) */
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SAVE_SPRN(HID0, 0x18)
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SAVE_SPRN(HID1, 0x19)
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SAVE_SPRN(HID2, 0x1a)
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mfmsr r10
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stw r10, (4*0x1b)(r4)
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/*SAVE_SPRN(LR, 0x1c) have to save it before the call */
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/* 0x1d reserved by 0xf0 */
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SAVE_SPRN(RPA, 0x1e)
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SAVE_SPRN(SDR1, 0x1f)
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/* save MMU regs */
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SAVE_BAT(0, 0x20)
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SAVE_BAT(1, 0x24)
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SAVE_BAT(2, 0x28)
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SAVE_BAT(3, 0x2c)
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SAVE_BAT(4, 0x30)
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SAVE_BAT(5, 0x34)
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SAVE_BAT(6, 0x38)
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SAVE_BAT(7, 0x3c)
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SAVE_4SR(0, 0x40)
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SAVE_4SR(4, 0x44)
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SAVE_4SR(8, 0x48)
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SAVE_4SR(12, 0x4c)
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SAVE_SPRN(SPRG0, 0x50)
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SAVE_SPRN(SPRG1, 0x51)
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SAVE_SPRN(SPRG2, 0x52)
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SAVE_SPRN(SPRG3, 0x53)
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SAVE_SPRN(SPRG4, 0x54)
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SAVE_SPRN(SPRG5, 0x55)
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SAVE_SPRN(SPRG6, 0x56)
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SAVE_SPRN(SPRG7, 0x57)
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SAVE_SPRN(IABR, 0x58)
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SAVE_SPRN(DABR, 0x59)
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SAVE_SPRN(TBRL, 0x5a)
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SAVE_SPRN(TBRU, 0x5b)
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blr
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/* restore registers */
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#define LOAD_BAT(n, addr) \
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LOAD_SPRN(DBAT##n##L, addr); \
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LOAD_SPRN(DBAT##n##U, addr+1); \
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LOAD_SPRN(IBAT##n##L, addr+2); \
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LOAD_SPRN(IBAT##n##U, addr+3);
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#define LOAD_SR(n, addr) \
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lwz r10, ((addr)*4)(r4); \
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mtsr n, r10;
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#define LOAD_4SR(n, addr) \
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LOAD_SR(n, addr); \
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LOAD_SR(n+1, addr+1); \
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LOAD_SR(n+2, addr+2); \
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LOAD_SR(n+3, addr+3);
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restore_regs:
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lis r4, registers@h
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ori r4, r4, registers@l
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/* MMU is not up yet */
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subis r4, r4, CONFIG_KERNEL_START@h
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lwz r0, 0(r4)
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lwz r1, 0x4(r4)
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lwz r2, 0x8(r4)
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lmw r11, 0xc(r4)
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/*
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* these are a bit tricky
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*
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* 0x18 - HID0
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* 0x19 - HID1
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* 0x1a - HID2
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* 0x1b - MSR
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* 0x1c - LR
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* 0x1d - reserved by 0xf0 (BDI2000)
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*/
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LOAD_SPRN(RPA, 0x1e);
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LOAD_SPRN(SDR1, 0x1f);
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/* restore MMU regs */
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LOAD_BAT(0, 0x20)
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LOAD_BAT(1, 0x24)
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LOAD_BAT(2, 0x28)
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LOAD_BAT(3, 0x2c)
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LOAD_BAT(4, 0x30)
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LOAD_BAT(5, 0x34)
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LOAD_BAT(6, 0x38)
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LOAD_BAT(7, 0x3c)
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LOAD_4SR(0, 0x40)
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LOAD_4SR(4, 0x44)
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LOAD_4SR(8, 0x48)
|
||
|
|
LOAD_4SR(12, 0x4c)
|
||
|
|
|
||
|
|
/* rest of regs */
|
||
|
|
LOAD_SPRN(SPRG0, 0x50);
|
||
|
|
LOAD_SPRN(SPRG1, 0x51);
|
||
|
|
LOAD_SPRN(SPRG2, 0x52);
|
||
|
|
LOAD_SPRN(SPRG3, 0x53);
|
||
|
|
LOAD_SPRN(SPRG4, 0x54);
|
||
|
|
LOAD_SPRN(SPRG5, 0x55);
|
||
|
|
LOAD_SPRN(SPRG6, 0x56);
|
||
|
|
LOAD_SPRN(SPRG7, 0x57);
|
||
|
|
|
||
|
|
LOAD_SPRN(IABR, 0x58);
|
||
|
|
LOAD_SPRN(DABR, 0x59);
|
||
|
|
LOAD_SPRN(TBWL, 0x5a); /* these two have separate R/W regs */
|
||
|
|
LOAD_SPRN(TBWU, 0x5b);
|
||
|
|
|
||
|
|
blr
|
||
|
|
|
||
|
|
|
||
|
|
|
||
|
|
/* cache flushing code. copied from arch/ppc/boot/util.S */
|
||
|
|
#define NUM_CACHE_LINES (128*8)
|
||
|
|
|
||
|
|
/*
|
||
|
|
* Flush data cache
|
||
|
|
* Do this by just reading lots of stuff into the cache.
|
||
|
|
*/
|
||
|
|
flush_data_cache:
|
||
|
|
lis r3,CONFIG_KERNEL_START@h
|
||
|
|
ori r3,r3,CONFIG_KERNEL_START@l
|
||
|
|
li r4,NUM_CACHE_LINES
|
||
|
|
mtctr r4
|
||
|
|
1:
|
||
|
|
lwz r4,0(r3)
|
||
|
|
addi r3,r3,L1_CACHE_BYTES /* Next line, please */
|
||
|
|
bdnz 1b
|
||
|
|
blr
|