2011-06-28 18:17:58 -06:00
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/*
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* Copyright (C) 2009. SUSE Linux Products GmbH. All rights reserved.
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*
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* Authors:
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* Alexander Graf <agraf@suse.de>
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* Kevin Wolf <mail@kevin-wolf.de>
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* Paul Mackerras <paulus@samba.org>
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*
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* Description:
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* Functions relating to running KVM on Book 3S processors where
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* we don't have access to hypervisor mode, and we run the guest
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* in problem state (user mode).
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*
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* This file is derived from arch/powerpc/kvm/44x.c,
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* by Hollis Blanchard <hollisb@us.ibm.com>.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License, version 2, as
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* published by the Free Software Foundation.
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*/
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#include <linux/kvm_host.h>
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2011-07-29 00:19:31 -06:00
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#include <linux/export.h>
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2011-06-28 18:17:58 -06:00
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#include <linux/err.h>
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#include <linux/slab.h>
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#include <asm/reg.h>
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#include <asm/cputable.h>
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#include <asm/cacheflush.h>
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#include <asm/tlbflush.h>
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#include <asm/uaccess.h>
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#include <asm/io.h>
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#include <asm/kvm_ppc.h>
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#include <asm/kvm_book3s.h>
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#include <asm/mmu_context.h>
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2012-04-01 11:35:53 -06:00
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#include <asm/switch_to.h>
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2011-06-28 18:17:58 -06:00
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#include <linux/gfp.h>
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#include <linux/sched.h>
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#include <linux/vmalloc.h>
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#include <linux/highmem.h>
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#include "trace.h"
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/* #define EXIT_DEBUG */
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/* #define DEBUG_EXT */
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static int kvmppc_handle_ext(struct kvm_vcpu *vcpu, unsigned int exit_nr,
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ulong msr);
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/* Some compatibility defines */
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#ifdef CONFIG_PPC_BOOK3S_32
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#define MSR_USER32 MSR_USER
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#define MSR_USER64 MSR_USER
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#define HW_PAGE_SIZE PAGE_SIZE
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#endif
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void kvmppc_core_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
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{
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#ifdef CONFIG_PPC_BOOK3S_64
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2011-12-09 06:44:13 -07:00
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struct kvmppc_book3s_shadow_vcpu *svcpu = svcpu_get(vcpu);
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memcpy(svcpu->slb, to_book3s(vcpu)->slb_shadow, sizeof(svcpu->slb));
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2011-06-28 18:17:58 -06:00
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memcpy(&get_paca()->shadow_vcpu, to_book3s(vcpu)->shadow_vcpu,
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sizeof(get_paca()->shadow_vcpu));
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2011-12-09 06:44:13 -07:00
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svcpu->slb_max = to_book3s(vcpu)->slb_shadow_max;
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svcpu_put(svcpu);
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2011-06-28 18:17:58 -06:00
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#endif
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2012-09-20 13:35:51 -06:00
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vcpu->cpu = smp_processor_id();
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2011-06-28 18:17:58 -06:00
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#ifdef CONFIG_PPC_BOOK3S_32
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current->thread.kvm_shadow_vcpu = to_book3s(vcpu)->shadow_vcpu;
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#endif
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}
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void kvmppc_core_vcpu_put(struct kvm_vcpu *vcpu)
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{
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#ifdef CONFIG_PPC_BOOK3S_64
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2011-12-09 06:44:13 -07:00
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struct kvmppc_book3s_shadow_vcpu *svcpu = svcpu_get(vcpu);
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memcpy(to_book3s(vcpu)->slb_shadow, svcpu->slb, sizeof(svcpu->slb));
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2011-06-28 18:17:58 -06:00
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memcpy(to_book3s(vcpu)->shadow_vcpu, &get_paca()->shadow_vcpu,
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sizeof(get_paca()->shadow_vcpu));
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2011-12-09 06:44:13 -07:00
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to_book3s(vcpu)->slb_shadow_max = svcpu->slb_max;
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svcpu_put(svcpu);
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2011-06-28 18:17:58 -06:00
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#endif
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KVM: PPC: Book3S PR: Fix VSX handling
This fixes various issues in how we were handling the VSX registers
that exist on POWER7 machines. First, we were running off the end
of the current->thread.fpr[] array. Ultimately this was because the
vcpu->arch.vsr[] array is sized to be able to store both the FP
registers and the extra VSX registers (i.e. 64 entries), but PR KVM
only uses it for the extra VSX registers (i.e. 32 entries).
Secondly, calling load_up_vsx() from C code is a really bad idea,
because it jumps to fast_exception_return at the end, rather than
returning with a blr instruction. This was causing it to jump off
to a random location with random register contents, since it was using
the largely uninitialized stack frame created by kvmppc_load_up_vsx.
In fact, it isn't necessary to call either __giveup_vsx or load_up_vsx,
since giveup_fpu and load_up_fpu handle the extra VSX registers as well
as the standard FP registers on machines with VSX. Also, since VSX
instructions can access the VMX registers and the FP registers as well
as the extra VSX registers, we have to load up the FP and VMX registers
before we can turn on the MSR_VSX bit for the guest. Conversely, if
we save away any of the VSX or FP registers, we have to turn off MSR_VSX
for the guest.
To handle all this, it is more convenient for a single call to
kvmppc_giveup_ext() to handle all the state saving that needs to be done,
so we make it take a set of MSR bits rather than just one, and the switch
statement becomes a series of if statements. Similarly kvmppc_handle_ext
needs to be able to load up more than one set of registers.
Signed-off-by: Paul Mackerras <paulus@samba.org>
Signed-off-by: Alexander Graf <agraf@suse.de>
2012-11-04 11:16:46 -07:00
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kvmppc_giveup_ext(vcpu, MSR_FP | MSR_VEC | MSR_VSX);
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2012-09-20 13:35:51 -06:00
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vcpu->cpu = -1;
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2011-06-28 18:17:58 -06:00
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}
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2012-08-13 04:50:35 -06:00
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int kvmppc_core_check_requests(struct kvm_vcpu *vcpu)
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2012-08-10 04:28:50 -06:00
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{
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2012-08-13 04:50:35 -06:00
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int r = 1; /* Indicate we want to get back into the guest */
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2012-08-10 05:23:55 -06:00
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/* We misuse TLB_FLUSH to indicate that we want to clear
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all shadow cache entries */
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if (kvm_check_request(KVM_REQ_TLB_FLUSH, vcpu))
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kvmppc_mmu_pte_flush(vcpu, 0, 0);
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2012-08-13 04:50:35 -06:00
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return r;
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2012-08-10 04:28:50 -06:00
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}
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2012-08-10 05:23:55 -06:00
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/************* MMU Notifiers *************/
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int kvm_unmap_hva(struct kvm *kvm, unsigned long hva)
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{
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trace_kvm_unmap_hva(hva);
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/*
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* Flush all shadow tlb entries everywhere. This is slow, but
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* we are 100% sure that we catch the to be unmapped page
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*/
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kvm_flush_remote_tlbs(kvm);
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return 0;
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}
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int kvm_unmap_hva_range(struct kvm *kvm, unsigned long start, unsigned long end)
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{
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/* kvm_unmap_hva flushes everything anyways */
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kvm_unmap_hva(kvm, start);
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return 0;
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}
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int kvm_age_hva(struct kvm *kvm, unsigned long hva)
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{
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/* XXX could be more clever ;) */
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return 0;
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}
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int kvm_test_age_hva(struct kvm *kvm, unsigned long hva)
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{
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/* XXX could be more clever ;) */
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return 0;
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}
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void kvm_set_spte_hva(struct kvm *kvm, unsigned long hva, pte_t pte)
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{
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/* The page will get remapped properly on its next fault */
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kvm_unmap_hva(kvm, hva);
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}
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/*****************************************/
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2011-06-28 18:17:58 -06:00
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static void kvmppc_recalc_shadow_msr(struct kvm_vcpu *vcpu)
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{
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ulong smsr = vcpu->arch.shared->msr;
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/* Guest MSR values */
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2012-11-04 11:17:28 -07:00
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smsr &= MSR_FE0 | MSR_FE1 | MSR_SF | MSR_SE | MSR_BE;
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2011-06-28 18:17:58 -06:00
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/* Process MSR values */
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smsr |= MSR_ME | MSR_RI | MSR_IR | MSR_DR | MSR_PR | MSR_EE;
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/* External providers the guest reserved */
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smsr |= (vcpu->arch.shared->msr & vcpu->arch.guest_owned_ext);
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/* 64-bit Process MSR values */
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#ifdef CONFIG_PPC_BOOK3S_64
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smsr |= MSR_ISF | MSR_HV;
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#endif
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vcpu->arch.shadow_msr = smsr;
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}
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void kvmppc_set_msr(struct kvm_vcpu *vcpu, u64 msr)
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{
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ulong old_msr = vcpu->arch.shared->msr;
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#ifdef EXIT_DEBUG
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printk(KERN_INFO "KVM: Set MSR to 0x%llx\n", msr);
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#endif
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msr &= to_book3s(vcpu)->msr_mask;
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vcpu->arch.shared->msr = msr;
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kvmppc_recalc_shadow_msr(vcpu);
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if (msr & MSR_POW) {
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if (!vcpu->arch.pending_exceptions) {
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kvm_vcpu_block(vcpu);
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2012-03-14 09:55:08 -06:00
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clear_bit(KVM_REQ_UNHALT, &vcpu->requests);
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2011-06-28 18:17:58 -06:00
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vcpu->stat.halt_wakeup++;
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/* Unset POW bit after we woke up */
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msr &= ~MSR_POW;
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vcpu->arch.shared->msr = msr;
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}
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}
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if ((vcpu->arch.shared->msr & (MSR_PR|MSR_IR|MSR_DR)) !=
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(old_msr & (MSR_PR|MSR_IR|MSR_DR))) {
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kvmppc_mmu_flush_segments(vcpu);
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kvmppc_mmu_map_segment(vcpu, kvmppc_get_pc(vcpu));
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/* Preload magic page segment when in kernel mode */
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if (!(msr & MSR_PR) && vcpu->arch.magic_page_pa) {
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struct kvm_vcpu_arch *a = &vcpu->arch;
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if (msr & MSR_DR)
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kvmppc_mmu_map_segment(vcpu, a->magic_page_ea);
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else
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kvmppc_mmu_map_segment(vcpu, a->magic_page_pa);
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}
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}
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2012-03-13 15:52:44 -06:00
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/*
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* When switching from 32 to 64-bit, we may have a stale 32-bit
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* magic page around, we need to flush it. Typically 32-bit magic
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* page will be instanciated when calling into RTAS. Note: We
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* assume that such transition only happens while in kernel mode,
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* ie, we never transition from user 32-bit to kernel 64-bit with
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* a 32-bit magic page around.
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*/
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if (vcpu->arch.magic_page_pa &&
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!(old_msr & MSR_PR) && !(old_msr & MSR_SF) && (msr & MSR_SF)) {
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/* going from RTAS to normal kernel code */
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kvmppc_mmu_pte_flush(vcpu, (uint32_t)vcpu->arch.magic_page_pa,
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~0xFFFUL);
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}
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2011-06-28 18:17:58 -06:00
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/* Preload FPU if it's enabled */
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if (vcpu->arch.shared->msr & MSR_FP)
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kvmppc_handle_ext(vcpu, BOOK3S_INTERRUPT_FP_UNAVAIL, MSR_FP);
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}
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void kvmppc_set_pvr(struct kvm_vcpu *vcpu, u32 pvr)
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{
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u32 host_pvr;
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vcpu->arch.hflags &= ~BOOK3S_HFLAG_SLB;
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vcpu->arch.pvr = pvr;
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#ifdef CONFIG_PPC_BOOK3S_64
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if ((pvr >= 0x330000) && (pvr < 0x70330000)) {
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kvmppc_mmu_book3s_64_init(vcpu);
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2011-09-14 13:45:23 -06:00
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if (!to_book3s(vcpu)->hior_explicit)
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to_book3s(vcpu)->hior = 0xfff00000;
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2011-06-28 18:17:58 -06:00
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to_book3s(vcpu)->msr_mask = 0xffffffffffffffffULL;
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2011-08-10 05:57:08 -06:00
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vcpu->arch.cpu_type = KVM_CPU_3S_64;
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2011-06-28 18:17:58 -06:00
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} else
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#endif
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{
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kvmppc_mmu_book3s_32_init(vcpu);
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2011-09-14 13:45:23 -06:00
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if (!to_book3s(vcpu)->hior_explicit)
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to_book3s(vcpu)->hior = 0;
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2011-06-28 18:17:58 -06:00
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to_book3s(vcpu)->msr_mask = 0xffffffffULL;
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2011-08-10 05:57:08 -06:00
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vcpu->arch.cpu_type = KVM_CPU_3S_32;
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2011-06-28 18:17:58 -06:00
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}
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2011-08-10 05:57:08 -06:00
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kvmppc_sanity_check(vcpu);
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2011-06-28 18:17:58 -06:00
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/* If we are in hypervisor level on 970, we can tell the CPU to
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* treat DCBZ as 32 bytes store */
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vcpu->arch.hflags &= ~BOOK3S_HFLAG_DCBZ32;
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if (vcpu->arch.mmu.is_dcbz32(vcpu) && (mfmsr() & MSR_HV) &&
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!strcmp(cur_cpu_spec->platform, "ppc970"))
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vcpu->arch.hflags |= BOOK3S_HFLAG_DCBZ32;
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/* Cell performs badly if MSR_FEx are set. So let's hope nobody
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really needs them in a VM on Cell and force disable them. */
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if (!strcmp(cur_cpu_spec->platform, "ppc-cell-be"))
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to_book3s(vcpu)->msr_mask &= ~(MSR_FE0 | MSR_FE1);
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#ifdef CONFIG_PPC_BOOK3S_32
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/* 32 bit Book3S always has 32 byte dcbz */
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vcpu->arch.hflags |= BOOK3S_HFLAG_DCBZ32;
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#endif
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/* On some CPUs we can execute paired single operations natively */
|
|
|
|
|
asm ( "mfpvr %0" : "=r"(host_pvr));
|
|
|
|
|
switch (host_pvr) {
|
|
|
|
|
case 0x00080200: /* lonestar 2.0 */
|
|
|
|
|
case 0x00088202: /* lonestar 2.2 */
|
|
|
|
|
case 0x70000100: /* gekko 1.0 */
|
|
|
|
|
case 0x00080100: /* gekko 2.0 */
|
|
|
|
|
case 0x00083203: /* gekko 2.3a */
|
|
|
|
|
case 0x00083213: /* gekko 2.3b */
|
|
|
|
|
case 0x00083204: /* gekko 2.4 */
|
|
|
|
|
case 0x00083214: /* gekko 2.4e (8SE) - retail HW2 */
|
|
|
|
|
case 0x00087200: /* broadway */
|
|
|
|
|
vcpu->arch.hflags |= BOOK3S_HFLAG_NATIVE_PS;
|
|
|
|
|
/* Enable HID2.PSE - in case we need it later */
|
|
|
|
|
mtspr(SPRN_HID2_GEKKO, mfspr(SPRN_HID2_GEKKO) | (1 << 29));
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
/* Book3s_32 CPUs always have 32 bytes cache line size, which Linux assumes. To
|
|
|
|
|
* make Book3s_32 Linux work on Book3s_64, we have to make sure we trap dcbz to
|
|
|
|
|
* emulate 32 bytes dcbz length.
|
|
|
|
|
*
|
|
|
|
|
* The Book3s_64 inventors also realized this case and implemented a special bit
|
|
|
|
|
* in the HID5 register, which is a hypervisor ressource. Thus we can't use it.
|
|
|
|
|
*
|
|
|
|
|
* My approach here is to patch the dcbz instruction on executing pages.
|
|
|
|
|
*/
|
|
|
|
|
static void kvmppc_patch_dcbz(struct kvm_vcpu *vcpu, struct kvmppc_pte *pte)
|
|
|
|
|
{
|
|
|
|
|
struct page *hpage;
|
|
|
|
|
u64 hpage_offset;
|
|
|
|
|
u32 *page;
|
|
|
|
|
int i;
|
|
|
|
|
|
|
|
|
|
hpage = gfn_to_page(vcpu->kvm, pte->raddr >> PAGE_SHIFT);
|
2012-08-03 01:42:52 -06:00
|
|
|
if (is_error_page(hpage))
|
2011-06-28 18:17:58 -06:00
|
|
|
return;
|
|
|
|
|
|
|
|
|
|
hpage_offset = pte->raddr & ~PAGE_MASK;
|
|
|
|
|
hpage_offset &= ~0xFFFULL;
|
|
|
|
|
hpage_offset /= 4;
|
|
|
|
|
|
|
|
|
|
get_page(hpage);
|
2011-11-25 08:14:16 -07:00
|
|
|
page = kmap_atomic(hpage);
|
2011-06-28 18:17:58 -06:00
|
|
|
|
|
|
|
|
/* patch dcbz into reserved instruction, so we trap */
|
|
|
|
|
for (i=hpage_offset; i < hpage_offset + (HW_PAGE_SIZE / 4); i++)
|
|
|
|
|
if ((page[i] & 0xff0007ff) == INS_DCBZ)
|
|
|
|
|
page[i] &= 0xfffffff7;
|
|
|
|
|
|
2011-11-25 08:14:16 -07:00
|
|
|
kunmap_atomic(page);
|
2011-06-28 18:17:58 -06:00
|
|
|
put_page(hpage);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static int kvmppc_visible_gfn(struct kvm_vcpu *vcpu, gfn_t gfn)
|
|
|
|
|
{
|
|
|
|
|
ulong mp_pa = vcpu->arch.magic_page_pa;
|
|
|
|
|
|
2012-03-13 15:52:44 -06:00
|
|
|
if (!(vcpu->arch.shared->msr & MSR_SF))
|
|
|
|
|
mp_pa = (uint32_t)mp_pa;
|
|
|
|
|
|
2011-06-28 18:17:58 -06:00
|
|
|
if (unlikely(mp_pa) &&
|
|
|
|
|
unlikely((mp_pa & KVM_PAM) >> PAGE_SHIFT == gfn)) {
|
|
|
|
|
return 1;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
return kvm_is_visible_gfn(vcpu->kvm, gfn);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
int kvmppc_handle_pagefault(struct kvm_run *run, struct kvm_vcpu *vcpu,
|
|
|
|
|
ulong eaddr, int vec)
|
|
|
|
|
{
|
|
|
|
|
bool data = (vec == BOOK3S_INTERRUPT_DATA_STORAGE);
|
|
|
|
|
int r = RESUME_GUEST;
|
|
|
|
|
int relocated;
|
|
|
|
|
int page_found = 0;
|
|
|
|
|
struct kvmppc_pte pte;
|
|
|
|
|
bool is_mmio = false;
|
|
|
|
|
bool dr = (vcpu->arch.shared->msr & MSR_DR) ? true : false;
|
|
|
|
|
bool ir = (vcpu->arch.shared->msr & MSR_IR) ? true : false;
|
|
|
|
|
u64 vsid;
|
|
|
|
|
|
|
|
|
|
relocated = data ? dr : ir;
|
|
|
|
|
|
|
|
|
|
/* Resolve real address if translation turned on */
|
|
|
|
|
if (relocated) {
|
|
|
|
|
page_found = vcpu->arch.mmu.xlate(vcpu, eaddr, &pte, data);
|
|
|
|
|
} else {
|
|
|
|
|
pte.may_execute = true;
|
|
|
|
|
pte.may_read = true;
|
|
|
|
|
pte.may_write = true;
|
|
|
|
|
pte.raddr = eaddr & KVM_PAM;
|
|
|
|
|
pte.eaddr = eaddr;
|
|
|
|
|
pte.vpage = eaddr >> 12;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
switch (vcpu->arch.shared->msr & (MSR_DR|MSR_IR)) {
|
|
|
|
|
case 0:
|
|
|
|
|
pte.vpage |= ((u64)VSID_REAL << (SID_SHIFT - 12));
|
|
|
|
|
break;
|
|
|
|
|
case MSR_DR:
|
|
|
|
|
case MSR_IR:
|
|
|
|
|
vcpu->arch.mmu.esid_to_vsid(vcpu, eaddr >> SID_SHIFT, &vsid);
|
|
|
|
|
|
|
|
|
|
if ((vcpu->arch.shared->msr & (MSR_DR|MSR_IR)) == MSR_DR)
|
|
|
|
|
pte.vpage |= ((u64)VSID_REAL_DR << (SID_SHIFT - 12));
|
|
|
|
|
else
|
|
|
|
|
pte.vpage |= ((u64)VSID_REAL_IR << (SID_SHIFT - 12));
|
|
|
|
|
pte.vpage |= vsid;
|
|
|
|
|
|
|
|
|
|
if (vsid == -1)
|
|
|
|
|
page_found = -EINVAL;
|
|
|
|
|
break;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
if (vcpu->arch.mmu.is_dcbz32(vcpu) &&
|
|
|
|
|
(!(vcpu->arch.hflags & BOOK3S_HFLAG_DCBZ32))) {
|
|
|
|
|
/*
|
|
|
|
|
* If we do the dcbz hack, we have to NX on every execution,
|
|
|
|
|
* so we can patch the executing code. This renders our guest
|
|
|
|
|
* NX-less.
|
|
|
|
|
*/
|
|
|
|
|
pte.may_execute = !data;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
if (page_found == -ENOENT) {
|
|
|
|
|
/* Page not found in guest PTE entries */
|
2011-12-09 06:44:13 -07:00
|
|
|
struct kvmppc_book3s_shadow_vcpu *svcpu = svcpu_get(vcpu);
|
2011-06-28 18:17:58 -06:00
|
|
|
vcpu->arch.shared->dar = kvmppc_get_fault_dar(vcpu);
|
2011-12-09 06:44:13 -07:00
|
|
|
vcpu->arch.shared->dsisr = svcpu->fault_dsisr;
|
2011-06-28 18:17:58 -06:00
|
|
|
vcpu->arch.shared->msr |=
|
2011-12-09 06:44:13 -07:00
|
|
|
(svcpu->shadow_srr1 & 0x00000000f8000000ULL);
|
|
|
|
|
svcpu_put(svcpu);
|
2011-06-28 18:17:58 -06:00
|
|
|
kvmppc_book3s_queue_irqprio(vcpu, vec);
|
|
|
|
|
} else if (page_found == -EPERM) {
|
|
|
|
|
/* Storage protection */
|
2011-12-09 06:44:13 -07:00
|
|
|
struct kvmppc_book3s_shadow_vcpu *svcpu = svcpu_get(vcpu);
|
2011-06-28 18:17:58 -06:00
|
|
|
vcpu->arch.shared->dar = kvmppc_get_fault_dar(vcpu);
|
2011-12-09 06:44:13 -07:00
|
|
|
vcpu->arch.shared->dsisr = svcpu->fault_dsisr & ~DSISR_NOHPTE;
|
2011-06-28 18:17:58 -06:00
|
|
|
vcpu->arch.shared->dsisr |= DSISR_PROTFAULT;
|
|
|
|
|
vcpu->arch.shared->msr |=
|
2011-12-09 06:44:13 -07:00
|
|
|
svcpu->shadow_srr1 & 0x00000000f8000000ULL;
|
|
|
|
|
svcpu_put(svcpu);
|
2011-06-28 18:17:58 -06:00
|
|
|
kvmppc_book3s_queue_irqprio(vcpu, vec);
|
|
|
|
|
} else if (page_found == -EINVAL) {
|
|
|
|
|
/* Page not found in guest SLB */
|
|
|
|
|
vcpu->arch.shared->dar = kvmppc_get_fault_dar(vcpu);
|
|
|
|
|
kvmppc_book3s_queue_irqprio(vcpu, vec + 0x80);
|
|
|
|
|
} else if (!is_mmio &&
|
|
|
|
|
kvmppc_visible_gfn(vcpu, pte.raddr >> PAGE_SHIFT)) {
|
|
|
|
|
/* The guest's PTE is not mapped yet. Map on the host */
|
|
|
|
|
kvmppc_mmu_map_page(vcpu, &pte);
|
|
|
|
|
if (data)
|
|
|
|
|
vcpu->stat.sp_storage++;
|
|
|
|
|
else if (vcpu->arch.mmu.is_dcbz32(vcpu) &&
|
|
|
|
|
(!(vcpu->arch.hflags & BOOK3S_HFLAG_DCBZ32)))
|
|
|
|
|
kvmppc_patch_dcbz(vcpu, &pte);
|
|
|
|
|
} else {
|
|
|
|
|
/* MMIO */
|
|
|
|
|
vcpu->stat.mmio_exits++;
|
|
|
|
|
vcpu->arch.paddr_accessed = pte.raddr;
|
2012-03-11 19:26:30 -06:00
|
|
|
vcpu->arch.vaddr_accessed = pte.eaddr;
|
2011-06-28 18:17:58 -06:00
|
|
|
r = kvmppc_emulate_mmio(run, vcpu);
|
|
|
|
|
if ( r == RESUME_HOST_NV )
|
|
|
|
|
r = RESUME_HOST;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
return r;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static inline int get_fpr_index(int i)
|
|
|
|
|
{
|
KVM: PPC: Book3S PR: Fix VSX handling
This fixes various issues in how we were handling the VSX registers
that exist on POWER7 machines. First, we were running off the end
of the current->thread.fpr[] array. Ultimately this was because the
vcpu->arch.vsr[] array is sized to be able to store both the FP
registers and the extra VSX registers (i.e. 64 entries), but PR KVM
only uses it for the extra VSX registers (i.e. 32 entries).
Secondly, calling load_up_vsx() from C code is a really bad idea,
because it jumps to fast_exception_return at the end, rather than
returning with a blr instruction. This was causing it to jump off
to a random location with random register contents, since it was using
the largely uninitialized stack frame created by kvmppc_load_up_vsx.
In fact, it isn't necessary to call either __giveup_vsx or load_up_vsx,
since giveup_fpu and load_up_fpu handle the extra VSX registers as well
as the standard FP registers on machines with VSX. Also, since VSX
instructions can access the VMX registers and the FP registers as well
as the extra VSX registers, we have to load up the FP and VMX registers
before we can turn on the MSR_VSX bit for the guest. Conversely, if
we save away any of the VSX or FP registers, we have to turn off MSR_VSX
for the guest.
To handle all this, it is more convenient for a single call to
kvmppc_giveup_ext() to handle all the state saving that needs to be done,
so we make it take a set of MSR bits rather than just one, and the switch
statement becomes a series of if statements. Similarly kvmppc_handle_ext
needs to be able to load up more than one set of registers.
Signed-off-by: Paul Mackerras <paulus@samba.org>
Signed-off-by: Alexander Graf <agraf@suse.de>
2012-11-04 11:16:46 -07:00
|
|
|
return i * TS_FPRWIDTH;
|
2011-06-28 18:17:58 -06:00
|
|
|
}
|
|
|
|
|
|
|
|
|
|
/* Give up external provider (FPU, Altivec, VSX) */
|
|
|
|
|
void kvmppc_giveup_ext(struct kvm_vcpu *vcpu, ulong msr)
|
|
|
|
|
{
|
|
|
|
|
struct thread_struct *t = ¤t->thread;
|
|
|
|
|
u64 *vcpu_fpr = vcpu->arch.fpr;
|
|
|
|
|
#ifdef CONFIG_VSX
|
|
|
|
|
u64 *vcpu_vsx = vcpu->arch.vsr;
|
|
|
|
|
#endif
|
|
|
|
|
u64 *thread_fpr = (u64*)t->fpr;
|
|
|
|
|
int i;
|
|
|
|
|
|
KVM: PPC: Book3S PR: Fix VSX handling
This fixes various issues in how we were handling the VSX registers
that exist on POWER7 machines. First, we were running off the end
of the current->thread.fpr[] array. Ultimately this was because the
vcpu->arch.vsr[] array is sized to be able to store both the FP
registers and the extra VSX registers (i.e. 64 entries), but PR KVM
only uses it for the extra VSX registers (i.e. 32 entries).
Secondly, calling load_up_vsx() from C code is a really bad idea,
because it jumps to fast_exception_return at the end, rather than
returning with a blr instruction. This was causing it to jump off
to a random location with random register contents, since it was using
the largely uninitialized stack frame created by kvmppc_load_up_vsx.
In fact, it isn't necessary to call either __giveup_vsx or load_up_vsx,
since giveup_fpu and load_up_fpu handle the extra VSX registers as well
as the standard FP registers on machines with VSX. Also, since VSX
instructions can access the VMX registers and the FP registers as well
as the extra VSX registers, we have to load up the FP and VMX registers
before we can turn on the MSR_VSX bit for the guest. Conversely, if
we save away any of the VSX or FP registers, we have to turn off MSR_VSX
for the guest.
To handle all this, it is more convenient for a single call to
kvmppc_giveup_ext() to handle all the state saving that needs to be done,
so we make it take a set of MSR bits rather than just one, and the switch
statement becomes a series of if statements. Similarly kvmppc_handle_ext
needs to be able to load up more than one set of registers.
Signed-off-by: Paul Mackerras <paulus@samba.org>
Signed-off-by: Alexander Graf <agraf@suse.de>
2012-11-04 11:16:46 -07:00
|
|
|
/*
|
|
|
|
|
* VSX instructions can access FP and vector registers, so if
|
|
|
|
|
* we are giving up VSX, make sure we give up FP and VMX as well.
|
|
|
|
|
*/
|
|
|
|
|
if (msr & MSR_VSX)
|
|
|
|
|
msr |= MSR_FP | MSR_VEC;
|
|
|
|
|
|
|
|
|
|
msr &= vcpu->arch.guest_owned_ext;
|
|
|
|
|
if (!msr)
|
2011-06-28 18:17:58 -06:00
|
|
|
return;
|
|
|
|
|
|
|
|
|
|
#ifdef DEBUG_EXT
|
|
|
|
|
printk(KERN_INFO "Giving up ext 0x%lx\n", msr);
|
|
|
|
|
#endif
|
|
|
|
|
|
KVM: PPC: Book3S PR: Fix VSX handling
This fixes various issues in how we were handling the VSX registers
that exist on POWER7 machines. First, we were running off the end
of the current->thread.fpr[] array. Ultimately this was because the
vcpu->arch.vsr[] array is sized to be able to store both the FP
registers and the extra VSX registers (i.e. 64 entries), but PR KVM
only uses it for the extra VSX registers (i.e. 32 entries).
Secondly, calling load_up_vsx() from C code is a really bad idea,
because it jumps to fast_exception_return at the end, rather than
returning with a blr instruction. This was causing it to jump off
to a random location with random register contents, since it was using
the largely uninitialized stack frame created by kvmppc_load_up_vsx.
In fact, it isn't necessary to call either __giveup_vsx or load_up_vsx,
since giveup_fpu and load_up_fpu handle the extra VSX registers as well
as the standard FP registers on machines with VSX. Also, since VSX
instructions can access the VMX registers and the FP registers as well
as the extra VSX registers, we have to load up the FP and VMX registers
before we can turn on the MSR_VSX bit for the guest. Conversely, if
we save away any of the VSX or FP registers, we have to turn off MSR_VSX
for the guest.
To handle all this, it is more convenient for a single call to
kvmppc_giveup_ext() to handle all the state saving that needs to be done,
so we make it take a set of MSR bits rather than just one, and the switch
statement becomes a series of if statements. Similarly kvmppc_handle_ext
needs to be able to load up more than one set of registers.
Signed-off-by: Paul Mackerras <paulus@samba.org>
Signed-off-by: Alexander Graf <agraf@suse.de>
2012-11-04 11:16:46 -07:00
|
|
|
if (msr & MSR_FP) {
|
|
|
|
|
/*
|
|
|
|
|
* Note that on CPUs with VSX, giveup_fpu stores
|
|
|
|
|
* both the traditional FP registers and the added VSX
|
|
|
|
|
* registers into thread.fpr[].
|
|
|
|
|
*/
|
2011-06-28 18:17:58 -06:00
|
|
|
giveup_fpu(current);
|
|
|
|
|
for (i = 0; i < ARRAY_SIZE(vcpu->arch.fpr); i++)
|
|
|
|
|
vcpu_fpr[i] = thread_fpr[get_fpr_index(i)];
|
|
|
|
|
|
|
|
|
|
vcpu->arch.fpscr = t->fpscr.val;
|
KVM: PPC: Book3S PR: Fix VSX handling
This fixes various issues in how we were handling the VSX registers
that exist on POWER7 machines. First, we were running off the end
of the current->thread.fpr[] array. Ultimately this was because the
vcpu->arch.vsr[] array is sized to be able to store both the FP
registers and the extra VSX registers (i.e. 64 entries), but PR KVM
only uses it for the extra VSX registers (i.e. 32 entries).
Secondly, calling load_up_vsx() from C code is a really bad idea,
because it jumps to fast_exception_return at the end, rather than
returning with a blr instruction. This was causing it to jump off
to a random location with random register contents, since it was using
the largely uninitialized stack frame created by kvmppc_load_up_vsx.
In fact, it isn't necessary to call either __giveup_vsx or load_up_vsx,
since giveup_fpu and load_up_fpu handle the extra VSX registers as well
as the standard FP registers on machines with VSX. Also, since VSX
instructions can access the VMX registers and the FP registers as well
as the extra VSX registers, we have to load up the FP and VMX registers
before we can turn on the MSR_VSX bit for the guest. Conversely, if
we save away any of the VSX or FP registers, we have to turn off MSR_VSX
for the guest.
To handle all this, it is more convenient for a single call to
kvmppc_giveup_ext() to handle all the state saving that needs to be done,
so we make it take a set of MSR bits rather than just one, and the switch
statement becomes a series of if statements. Similarly kvmppc_handle_ext
needs to be able to load up more than one set of registers.
Signed-off-by: Paul Mackerras <paulus@samba.org>
Signed-off-by: Alexander Graf <agraf@suse.de>
2012-11-04 11:16:46 -07:00
|
|
|
|
|
|
|
|
#ifdef CONFIG_VSX
|
|
|
|
|
if (cpu_has_feature(CPU_FTR_VSX))
|
|
|
|
|
for (i = 0; i < ARRAY_SIZE(vcpu->arch.vsr) / 2; i++)
|
|
|
|
|
vcpu_vsx[i] = thread_fpr[get_fpr_index(i) + 1];
|
|
|
|
|
#endif
|
|
|
|
|
}
|
|
|
|
|
|
2011-06-28 18:17:58 -06:00
|
|
|
#ifdef CONFIG_ALTIVEC
|
KVM: PPC: Book3S PR: Fix VSX handling
This fixes various issues in how we were handling the VSX registers
that exist on POWER7 machines. First, we were running off the end
of the current->thread.fpr[] array. Ultimately this was because the
vcpu->arch.vsr[] array is sized to be able to store both the FP
registers and the extra VSX registers (i.e. 64 entries), but PR KVM
only uses it for the extra VSX registers (i.e. 32 entries).
Secondly, calling load_up_vsx() from C code is a really bad idea,
because it jumps to fast_exception_return at the end, rather than
returning with a blr instruction. This was causing it to jump off
to a random location with random register contents, since it was using
the largely uninitialized stack frame created by kvmppc_load_up_vsx.
In fact, it isn't necessary to call either __giveup_vsx or load_up_vsx,
since giveup_fpu and load_up_fpu handle the extra VSX registers as well
as the standard FP registers on machines with VSX. Also, since VSX
instructions can access the VMX registers and the FP registers as well
as the extra VSX registers, we have to load up the FP and VMX registers
before we can turn on the MSR_VSX bit for the guest. Conversely, if
we save away any of the VSX or FP registers, we have to turn off MSR_VSX
for the guest.
To handle all this, it is more convenient for a single call to
kvmppc_giveup_ext() to handle all the state saving that needs to be done,
so we make it take a set of MSR bits rather than just one, and the switch
statement becomes a series of if statements. Similarly kvmppc_handle_ext
needs to be able to load up more than one set of registers.
Signed-off-by: Paul Mackerras <paulus@samba.org>
Signed-off-by: Alexander Graf <agraf@suse.de>
2012-11-04 11:16:46 -07:00
|
|
|
if (msr & MSR_VEC) {
|
2011-06-28 18:17:58 -06:00
|
|
|
giveup_altivec(current);
|
|
|
|
|
memcpy(vcpu->arch.vr, t->vr, sizeof(vcpu->arch.vr));
|
|
|
|
|
vcpu->arch.vscr = t->vscr;
|
|
|
|
|
}
|
KVM: PPC: Book3S PR: Fix VSX handling
This fixes various issues in how we were handling the VSX registers
that exist on POWER7 machines. First, we were running off the end
of the current->thread.fpr[] array. Ultimately this was because the
vcpu->arch.vsr[] array is sized to be able to store both the FP
registers and the extra VSX registers (i.e. 64 entries), but PR KVM
only uses it for the extra VSX registers (i.e. 32 entries).
Secondly, calling load_up_vsx() from C code is a really bad idea,
because it jumps to fast_exception_return at the end, rather than
returning with a blr instruction. This was causing it to jump off
to a random location with random register contents, since it was using
the largely uninitialized stack frame created by kvmppc_load_up_vsx.
In fact, it isn't necessary to call either __giveup_vsx or load_up_vsx,
since giveup_fpu and load_up_fpu handle the extra VSX registers as well
as the standard FP registers on machines with VSX. Also, since VSX
instructions can access the VMX registers and the FP registers as well
as the extra VSX registers, we have to load up the FP and VMX registers
before we can turn on the MSR_VSX bit for the guest. Conversely, if
we save away any of the VSX or FP registers, we have to turn off MSR_VSX
for the guest.
To handle all this, it is more convenient for a single call to
kvmppc_giveup_ext() to handle all the state saving that needs to be done,
so we make it take a set of MSR bits rather than just one, and the switch
statement becomes a series of if statements. Similarly kvmppc_handle_ext
needs to be able to load up more than one set of registers.
Signed-off-by: Paul Mackerras <paulus@samba.org>
Signed-off-by: Alexander Graf <agraf@suse.de>
2012-11-04 11:16:46 -07:00
|
|
|
#endif
|
2011-06-28 18:17:58 -06:00
|
|
|
|
KVM: PPC: Book3S PR: Fix VSX handling
This fixes various issues in how we were handling the VSX registers
that exist on POWER7 machines. First, we were running off the end
of the current->thread.fpr[] array. Ultimately this was because the
vcpu->arch.vsr[] array is sized to be able to store both the FP
registers and the extra VSX registers (i.e. 64 entries), but PR KVM
only uses it for the extra VSX registers (i.e. 32 entries).
Secondly, calling load_up_vsx() from C code is a really bad idea,
because it jumps to fast_exception_return at the end, rather than
returning with a blr instruction. This was causing it to jump off
to a random location with random register contents, since it was using
the largely uninitialized stack frame created by kvmppc_load_up_vsx.
In fact, it isn't necessary to call either __giveup_vsx or load_up_vsx,
since giveup_fpu and load_up_fpu handle the extra VSX registers as well
as the standard FP registers on machines with VSX. Also, since VSX
instructions can access the VMX registers and the FP registers as well
as the extra VSX registers, we have to load up the FP and VMX registers
before we can turn on the MSR_VSX bit for the guest. Conversely, if
we save away any of the VSX or FP registers, we have to turn off MSR_VSX
for the guest.
To handle all this, it is more convenient for a single call to
kvmppc_giveup_ext() to handle all the state saving that needs to be done,
so we make it take a set of MSR bits rather than just one, and the switch
statement becomes a series of if statements. Similarly kvmppc_handle_ext
needs to be able to load up more than one set of registers.
Signed-off-by: Paul Mackerras <paulus@samba.org>
Signed-off-by: Alexander Graf <agraf@suse.de>
2012-11-04 11:16:46 -07:00
|
|
|
vcpu->arch.guest_owned_ext &= ~(msr | MSR_VSX);
|
2011-06-28 18:17:58 -06:00
|
|
|
kvmppc_recalc_shadow_msr(vcpu);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static int kvmppc_read_inst(struct kvm_vcpu *vcpu)
|
|
|
|
|
{
|
|
|
|
|
ulong srr0 = kvmppc_get_pc(vcpu);
|
|
|
|
|
u32 last_inst = kvmppc_get_last_inst(vcpu);
|
|
|
|
|
int ret;
|
|
|
|
|
|
|
|
|
|
ret = kvmppc_ld(vcpu, &srr0, sizeof(u32), &last_inst, false);
|
|
|
|
|
if (ret == -ENOENT) {
|
|
|
|
|
ulong msr = vcpu->arch.shared->msr;
|
|
|
|
|
|
|
|
|
|
msr = kvmppc_set_field(msr, 33, 33, 1);
|
|
|
|
|
msr = kvmppc_set_field(msr, 34, 36, 0);
|
|
|
|
|
vcpu->arch.shared->msr = kvmppc_set_field(msr, 42, 47, 0);
|
|
|
|
|
kvmppc_book3s_queue_irqprio(vcpu, BOOK3S_INTERRUPT_INST_STORAGE);
|
|
|
|
|
return EMULATE_AGAIN;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
return EMULATE_DONE;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static int kvmppc_check_ext(struct kvm_vcpu *vcpu, unsigned int exit_nr)
|
|
|
|
|
{
|
|
|
|
|
|
|
|
|
|
/* Need to do paired single emulation? */
|
|
|
|
|
if (!(vcpu->arch.hflags & BOOK3S_HFLAG_PAIRED_SINGLE))
|
|
|
|
|
return EMULATE_DONE;
|
|
|
|
|
|
|
|
|
|
/* Read out the instruction */
|
|
|
|
|
if (kvmppc_read_inst(vcpu) == EMULATE_DONE)
|
|
|
|
|
/* Need to emulate */
|
|
|
|
|
return EMULATE_FAIL;
|
|
|
|
|
|
|
|
|
|
return EMULATE_AGAIN;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
/* Handle external providers (FPU, Altivec, VSX) */
|
|
|
|
|
static int kvmppc_handle_ext(struct kvm_vcpu *vcpu, unsigned int exit_nr,
|
|
|
|
|
ulong msr)
|
|
|
|
|
{
|
|
|
|
|
struct thread_struct *t = ¤t->thread;
|
|
|
|
|
u64 *vcpu_fpr = vcpu->arch.fpr;
|
|
|
|
|
#ifdef CONFIG_VSX
|
|
|
|
|
u64 *vcpu_vsx = vcpu->arch.vsr;
|
|
|
|
|
#endif
|
|
|
|
|
u64 *thread_fpr = (u64*)t->fpr;
|
|
|
|
|
int i;
|
|
|
|
|
|
|
|
|
|
/* When we have paired singles, we emulate in software */
|
|
|
|
|
if (vcpu->arch.hflags & BOOK3S_HFLAG_PAIRED_SINGLE)
|
|
|
|
|
return RESUME_GUEST;
|
|
|
|
|
|
|
|
|
|
if (!(vcpu->arch.shared->msr & msr)) {
|
|
|
|
|
kvmppc_book3s_queue_irqprio(vcpu, exit_nr);
|
|
|
|
|
return RESUME_GUEST;
|
|
|
|
|
}
|
|
|
|
|
|
KVM: PPC: Book3S PR: Fix VSX handling
This fixes various issues in how we were handling the VSX registers
that exist on POWER7 machines. First, we were running off the end
of the current->thread.fpr[] array. Ultimately this was because the
vcpu->arch.vsr[] array is sized to be able to store both the FP
registers and the extra VSX registers (i.e. 64 entries), but PR KVM
only uses it for the extra VSX registers (i.e. 32 entries).
Secondly, calling load_up_vsx() from C code is a really bad idea,
because it jumps to fast_exception_return at the end, rather than
returning with a blr instruction. This was causing it to jump off
to a random location with random register contents, since it was using
the largely uninitialized stack frame created by kvmppc_load_up_vsx.
In fact, it isn't necessary to call either __giveup_vsx or load_up_vsx,
since giveup_fpu and load_up_fpu handle the extra VSX registers as well
as the standard FP registers on machines with VSX. Also, since VSX
instructions can access the VMX registers and the FP registers as well
as the extra VSX registers, we have to load up the FP and VMX registers
before we can turn on the MSR_VSX bit for the guest. Conversely, if
we save away any of the VSX or FP registers, we have to turn off MSR_VSX
for the guest.
To handle all this, it is more convenient for a single call to
kvmppc_giveup_ext() to handle all the state saving that needs to be done,
so we make it take a set of MSR bits rather than just one, and the switch
statement becomes a series of if statements. Similarly kvmppc_handle_ext
needs to be able to load up more than one set of registers.
Signed-off-by: Paul Mackerras <paulus@samba.org>
Signed-off-by: Alexander Graf <agraf@suse.de>
2012-11-04 11:16:46 -07:00
|
|
|
if (msr == MSR_VSX) {
|
|
|
|
|
/* No VSX? Give an illegal instruction interrupt */
|
|
|
|
|
#ifdef CONFIG_VSX
|
|
|
|
|
if (!cpu_has_feature(CPU_FTR_VSX))
|
|
|
|
|
#endif
|
|
|
|
|
{
|
|
|
|
|
kvmppc_core_queue_program(vcpu, SRR1_PROGILL);
|
|
|
|
|
return RESUME_GUEST;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
/*
|
|
|
|
|
* We have to load up all the FP and VMX registers before
|
|
|
|
|
* we can let the guest use VSX instructions.
|
|
|
|
|
*/
|
|
|
|
|
msr = MSR_FP | MSR_VEC | MSR_VSX;
|
2011-06-28 18:17:58 -06:00
|
|
|
}
|
|
|
|
|
|
KVM: PPC: Book3S PR: Fix VSX handling
This fixes various issues in how we were handling the VSX registers
that exist on POWER7 machines. First, we were running off the end
of the current->thread.fpr[] array. Ultimately this was because the
vcpu->arch.vsr[] array is sized to be able to store both the FP
registers and the extra VSX registers (i.e. 64 entries), but PR KVM
only uses it for the extra VSX registers (i.e. 32 entries).
Secondly, calling load_up_vsx() from C code is a really bad idea,
because it jumps to fast_exception_return at the end, rather than
returning with a blr instruction. This was causing it to jump off
to a random location with random register contents, since it was using
the largely uninitialized stack frame created by kvmppc_load_up_vsx.
In fact, it isn't necessary to call either __giveup_vsx or load_up_vsx,
since giveup_fpu and load_up_fpu handle the extra VSX registers as well
as the standard FP registers on machines with VSX. Also, since VSX
instructions can access the VMX registers and the FP registers as well
as the extra VSX registers, we have to load up the FP and VMX registers
before we can turn on the MSR_VSX bit for the guest. Conversely, if
we save away any of the VSX or FP registers, we have to turn off MSR_VSX
for the guest.
To handle all this, it is more convenient for a single call to
kvmppc_giveup_ext() to handle all the state saving that needs to be done,
so we make it take a set of MSR bits rather than just one, and the switch
statement becomes a series of if statements. Similarly kvmppc_handle_ext
needs to be able to load up more than one set of registers.
Signed-off-by: Paul Mackerras <paulus@samba.org>
Signed-off-by: Alexander Graf <agraf@suse.de>
2012-11-04 11:16:46 -07:00
|
|
|
/* See if we already own all the ext(s) needed */
|
|
|
|
|
msr &= ~vcpu->arch.guest_owned_ext;
|
|
|
|
|
if (!msr)
|
|
|
|
|
return RESUME_GUEST;
|
|
|
|
|
|
2011-06-28 18:17:58 -06:00
|
|
|
#ifdef DEBUG_EXT
|
|
|
|
|
printk(KERN_INFO "Loading up ext 0x%lx\n", msr);
|
|
|
|
|
#endif
|
|
|
|
|
|
|
|
|
|
current->thread.regs->msr |= msr;
|
|
|
|
|
|
KVM: PPC: Book3S PR: Fix VSX handling
This fixes various issues in how we were handling the VSX registers
that exist on POWER7 machines. First, we were running off the end
of the current->thread.fpr[] array. Ultimately this was because the
vcpu->arch.vsr[] array is sized to be able to store both the FP
registers and the extra VSX registers (i.e. 64 entries), but PR KVM
only uses it for the extra VSX registers (i.e. 32 entries).
Secondly, calling load_up_vsx() from C code is a really bad idea,
because it jumps to fast_exception_return at the end, rather than
returning with a blr instruction. This was causing it to jump off
to a random location with random register contents, since it was using
the largely uninitialized stack frame created by kvmppc_load_up_vsx.
In fact, it isn't necessary to call either __giveup_vsx or load_up_vsx,
since giveup_fpu and load_up_fpu handle the extra VSX registers as well
as the standard FP registers on machines with VSX. Also, since VSX
instructions can access the VMX registers and the FP registers as well
as the extra VSX registers, we have to load up the FP and VMX registers
before we can turn on the MSR_VSX bit for the guest. Conversely, if
we save away any of the VSX or FP registers, we have to turn off MSR_VSX
for the guest.
To handle all this, it is more convenient for a single call to
kvmppc_giveup_ext() to handle all the state saving that needs to be done,
so we make it take a set of MSR bits rather than just one, and the switch
statement becomes a series of if statements. Similarly kvmppc_handle_ext
needs to be able to load up more than one set of registers.
Signed-off-by: Paul Mackerras <paulus@samba.org>
Signed-off-by: Alexander Graf <agraf@suse.de>
2012-11-04 11:16:46 -07:00
|
|
|
if (msr & MSR_FP) {
|
2011-06-28 18:17:58 -06:00
|
|
|
for (i = 0; i < ARRAY_SIZE(vcpu->arch.fpr); i++)
|
|
|
|
|
thread_fpr[get_fpr_index(i)] = vcpu_fpr[i];
|
KVM: PPC: Book3S PR: Fix VSX handling
This fixes various issues in how we were handling the VSX registers
that exist on POWER7 machines. First, we were running off the end
of the current->thread.fpr[] array. Ultimately this was because the
vcpu->arch.vsr[] array is sized to be able to store both the FP
registers and the extra VSX registers (i.e. 64 entries), but PR KVM
only uses it for the extra VSX registers (i.e. 32 entries).
Secondly, calling load_up_vsx() from C code is a really bad idea,
because it jumps to fast_exception_return at the end, rather than
returning with a blr instruction. This was causing it to jump off
to a random location with random register contents, since it was using
the largely uninitialized stack frame created by kvmppc_load_up_vsx.
In fact, it isn't necessary to call either __giveup_vsx or load_up_vsx,
since giveup_fpu and load_up_fpu handle the extra VSX registers as well
as the standard FP registers on machines with VSX. Also, since VSX
instructions can access the VMX registers and the FP registers as well
as the extra VSX registers, we have to load up the FP and VMX registers
before we can turn on the MSR_VSX bit for the guest. Conversely, if
we save away any of the VSX or FP registers, we have to turn off MSR_VSX
for the guest.
To handle all this, it is more convenient for a single call to
kvmppc_giveup_ext() to handle all the state saving that needs to be done,
so we make it take a set of MSR bits rather than just one, and the switch
statement becomes a series of if statements. Similarly kvmppc_handle_ext
needs to be able to load up more than one set of registers.
Signed-off-by: Paul Mackerras <paulus@samba.org>
Signed-off-by: Alexander Graf <agraf@suse.de>
2012-11-04 11:16:46 -07:00
|
|
|
#ifdef CONFIG_VSX
|
|
|
|
|
for (i = 0; i < ARRAY_SIZE(vcpu->arch.vsr) / 2; i++)
|
|
|
|
|
thread_fpr[get_fpr_index(i) + 1] = vcpu_vsx[i];
|
|
|
|
|
#endif
|
2011-06-28 18:17:58 -06:00
|
|
|
t->fpscr.val = vcpu->arch.fpscr;
|
|
|
|
|
t->fpexc_mode = 0;
|
|
|
|
|
kvmppc_load_up_fpu();
|
KVM: PPC: Book3S PR: Fix VSX handling
This fixes various issues in how we were handling the VSX registers
that exist on POWER7 machines. First, we were running off the end
of the current->thread.fpr[] array. Ultimately this was because the
vcpu->arch.vsr[] array is sized to be able to store both the FP
registers and the extra VSX registers (i.e. 64 entries), but PR KVM
only uses it for the extra VSX registers (i.e. 32 entries).
Secondly, calling load_up_vsx() from C code is a really bad idea,
because it jumps to fast_exception_return at the end, rather than
returning with a blr instruction. This was causing it to jump off
to a random location with random register contents, since it was using
the largely uninitialized stack frame created by kvmppc_load_up_vsx.
In fact, it isn't necessary to call either __giveup_vsx or load_up_vsx,
since giveup_fpu and load_up_fpu handle the extra VSX registers as well
as the standard FP registers on machines with VSX. Also, since VSX
instructions can access the VMX registers and the FP registers as well
as the extra VSX registers, we have to load up the FP and VMX registers
before we can turn on the MSR_VSX bit for the guest. Conversely, if
we save away any of the VSX or FP registers, we have to turn off MSR_VSX
for the guest.
To handle all this, it is more convenient for a single call to
kvmppc_giveup_ext() to handle all the state saving that needs to be done,
so we make it take a set of MSR bits rather than just one, and the switch
statement becomes a series of if statements. Similarly kvmppc_handle_ext
needs to be able to load up more than one set of registers.
Signed-off-by: Paul Mackerras <paulus@samba.org>
Signed-off-by: Alexander Graf <agraf@suse.de>
2012-11-04 11:16:46 -07:00
|
|
|
}
|
|
|
|
|
|
|
|
|
|
if (msr & MSR_VEC) {
|
2011-06-28 18:17:58 -06:00
|
|
|
#ifdef CONFIG_ALTIVEC
|
|
|
|
|
memcpy(t->vr, vcpu->arch.vr, sizeof(vcpu->arch.vr));
|
|
|
|
|
t->vscr = vcpu->arch.vscr;
|
|
|
|
|
t->vrsave = -1;
|
|
|
|
|
kvmppc_load_up_altivec();
|
|
|
|
|
#endif
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
vcpu->arch.guest_owned_ext |= msr;
|
|
|
|
|
kvmppc_recalc_shadow_msr(vcpu);
|
|
|
|
|
|
|
|
|
|
return RESUME_GUEST;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
int kvmppc_handle_exit(struct kvm_run *run, struct kvm_vcpu *vcpu,
|
|
|
|
|
unsigned int exit_nr)
|
|
|
|
|
{
|
|
|
|
|
int r = RESUME_HOST;
|
2012-08-13 04:44:41 -06:00
|
|
|
int s;
|
2011-06-28 18:17:58 -06:00
|
|
|
|
|
|
|
|
vcpu->stat.sum_exits++;
|
|
|
|
|
|
|
|
|
|
run->exit_reason = KVM_EXIT_UNKNOWN;
|
|
|
|
|
run->ready_for_interrupt_injection = 1;
|
|
|
|
|
|
2012-08-12 17:04:19 -06:00
|
|
|
/* We get here with MSR.EE=1 */
|
2012-04-30 02:56:12 -06:00
|
|
|
|
2012-08-02 07:10:00 -06:00
|
|
|
trace_kvm_exit(exit_nr, vcpu);
|
2012-08-12 03:29:09 -06:00
|
|
|
kvm_guest_exit();
|
2012-08-12 03:27:49 -06:00
|
|
|
|
2011-06-28 18:17:58 -06:00
|
|
|
switch (exit_nr) {
|
|
|
|
|
case BOOK3S_INTERRUPT_INST_STORAGE:
|
2011-12-09 06:44:13 -07:00
|
|
|
{
|
|
|
|
|
struct kvmppc_book3s_shadow_vcpu *svcpu = svcpu_get(vcpu);
|
|
|
|
|
ulong shadow_srr1 = svcpu->shadow_srr1;
|
2011-06-28 18:17:58 -06:00
|
|
|
vcpu->stat.pf_instruc++;
|
|
|
|
|
|
|
|
|
|
#ifdef CONFIG_PPC_BOOK3S_32
|
|
|
|
|
/* We set segments as unused segments when invalidating them. So
|
|
|
|
|
* treat the respective fault as segment fault. */
|
2011-12-09 06:44:13 -07:00
|
|
|
if (svcpu->sr[kvmppc_get_pc(vcpu) >> SID_SHIFT] == SR_INVALID) {
|
2011-06-28 18:17:58 -06:00
|
|
|
kvmppc_mmu_map_segment(vcpu, kvmppc_get_pc(vcpu));
|
|
|
|
|
r = RESUME_GUEST;
|
2011-12-09 06:44:13 -07:00
|
|
|
svcpu_put(svcpu);
|
2011-06-28 18:17:58 -06:00
|
|
|
break;
|
|
|
|
|
}
|
|
|
|
|
#endif
|
2011-12-09 06:44:13 -07:00
|
|
|
svcpu_put(svcpu);
|
2011-06-28 18:17:58 -06:00
|
|
|
|
|
|
|
|
/* only care about PTEG not found errors, but leave NX alone */
|
2011-12-09 06:44:13 -07:00
|
|
|
if (shadow_srr1 & 0x40000000) {
|
2011-06-28 18:17:58 -06:00
|
|
|
r = kvmppc_handle_pagefault(run, vcpu, kvmppc_get_pc(vcpu), exit_nr);
|
|
|
|
|
vcpu->stat.sp_instruc++;
|
|
|
|
|
} else if (vcpu->arch.mmu.is_dcbz32(vcpu) &&
|
|
|
|
|
(!(vcpu->arch.hflags & BOOK3S_HFLAG_DCBZ32))) {
|
|
|
|
|
/*
|
|
|
|
|
* XXX If we do the dcbz hack we use the NX bit to flush&patch the page,
|
|
|
|
|
* so we can't use the NX bit inside the guest. Let's cross our fingers,
|
|
|
|
|
* that no guest that needs the dcbz hack does NX.
|
|
|
|
|
*/
|
|
|
|
|
kvmppc_mmu_pte_flush(vcpu, kvmppc_get_pc(vcpu), ~0xFFFUL);
|
|
|
|
|
r = RESUME_GUEST;
|
|
|
|
|
} else {
|
2011-12-09 06:44:13 -07:00
|
|
|
vcpu->arch.shared->msr |= shadow_srr1 & 0x58000000;
|
2011-06-28 18:17:58 -06:00
|
|
|
kvmppc_book3s_queue_irqprio(vcpu, exit_nr);
|
|
|
|
|
r = RESUME_GUEST;
|
|
|
|
|
}
|
|
|
|
|
break;
|
2011-12-09 06:44:13 -07:00
|
|
|
}
|
2011-06-28 18:17:58 -06:00
|
|
|
case BOOK3S_INTERRUPT_DATA_STORAGE:
|
|
|
|
|
{
|
|
|
|
|
ulong dar = kvmppc_get_fault_dar(vcpu);
|
2011-12-09 06:44:13 -07:00
|
|
|
struct kvmppc_book3s_shadow_vcpu *svcpu = svcpu_get(vcpu);
|
|
|
|
|
u32 fault_dsisr = svcpu->fault_dsisr;
|
2011-06-28 18:17:58 -06:00
|
|
|
vcpu->stat.pf_storage++;
|
|
|
|
|
|
|
|
|
|
#ifdef CONFIG_PPC_BOOK3S_32
|
|
|
|
|
/* We set segments as unused segments when invalidating them. So
|
|
|
|
|
* treat the respective fault as segment fault. */
|
2011-12-09 06:44:13 -07:00
|
|
|
if ((svcpu->sr[dar >> SID_SHIFT]) == SR_INVALID) {
|
2011-06-28 18:17:58 -06:00
|
|
|
kvmppc_mmu_map_segment(vcpu, dar);
|
|
|
|
|
r = RESUME_GUEST;
|
2011-12-09 06:44:13 -07:00
|
|
|
svcpu_put(svcpu);
|
2011-06-28 18:17:58 -06:00
|
|
|
break;
|
|
|
|
|
}
|
|
|
|
|
#endif
|
2011-12-09 06:44:13 -07:00
|
|
|
svcpu_put(svcpu);
|
2011-06-28 18:17:58 -06:00
|
|
|
|
|
|
|
|
/* The only case we need to handle is missing shadow PTEs */
|
2011-12-09 06:44:13 -07:00
|
|
|
if (fault_dsisr & DSISR_NOHPTE) {
|
2011-06-28 18:17:58 -06:00
|
|
|
r = kvmppc_handle_pagefault(run, vcpu, dar, exit_nr);
|
|
|
|
|
} else {
|
|
|
|
|
vcpu->arch.shared->dar = dar;
|
2011-12-09 06:44:13 -07:00
|
|
|
vcpu->arch.shared->dsisr = fault_dsisr;
|
2011-06-28 18:17:58 -06:00
|
|
|
kvmppc_book3s_queue_irqprio(vcpu, exit_nr);
|
|
|
|
|
r = RESUME_GUEST;
|
|
|
|
|
}
|
|
|
|
|
break;
|
|
|
|
|
}
|
|
|
|
|
case BOOK3S_INTERRUPT_DATA_SEGMENT:
|
|
|
|
|
if (kvmppc_mmu_map_segment(vcpu, kvmppc_get_fault_dar(vcpu)) < 0) {
|
|
|
|
|
vcpu->arch.shared->dar = kvmppc_get_fault_dar(vcpu);
|
|
|
|
|
kvmppc_book3s_queue_irqprio(vcpu,
|
|
|
|
|
BOOK3S_INTERRUPT_DATA_SEGMENT);
|
|
|
|
|
}
|
|
|
|
|
r = RESUME_GUEST;
|
|
|
|
|
break;
|
|
|
|
|
case BOOK3S_INTERRUPT_INST_SEGMENT:
|
|
|
|
|
if (kvmppc_mmu_map_segment(vcpu, kvmppc_get_pc(vcpu)) < 0) {
|
|
|
|
|
kvmppc_book3s_queue_irqprio(vcpu,
|
|
|
|
|
BOOK3S_INTERRUPT_INST_SEGMENT);
|
|
|
|
|
}
|
|
|
|
|
r = RESUME_GUEST;
|
|
|
|
|
break;
|
|
|
|
|
/* We're good on these - the host merely wanted to get our attention */
|
|
|
|
|
case BOOK3S_INTERRUPT_DECREMENTER:
|
2012-03-13 16:05:16 -06:00
|
|
|
case BOOK3S_INTERRUPT_HV_DECREMENTER:
|
2011-06-28 18:17:58 -06:00
|
|
|
vcpu->stat.dec_exits++;
|
|
|
|
|
r = RESUME_GUEST;
|
|
|
|
|
break;
|
|
|
|
|
case BOOK3S_INTERRUPT_EXTERNAL:
|
2012-03-13 16:05:16 -06:00
|
|
|
case BOOK3S_INTERRUPT_EXTERNAL_LEVEL:
|
|
|
|
|
case BOOK3S_INTERRUPT_EXTERNAL_HV:
|
2011-06-28 18:17:58 -06:00
|
|
|
vcpu->stat.ext_intr_exits++;
|
|
|
|
|
r = RESUME_GUEST;
|
|
|
|
|
break;
|
|
|
|
|
case BOOK3S_INTERRUPT_PERFMON:
|
|
|
|
|
r = RESUME_GUEST;
|
|
|
|
|
break;
|
|
|
|
|
case BOOK3S_INTERRUPT_PROGRAM:
|
2012-03-13 16:05:16 -06:00
|
|
|
case BOOK3S_INTERRUPT_H_EMUL_ASSIST:
|
2011-06-28 18:17:58 -06:00
|
|
|
{
|
|
|
|
|
enum emulation_result er;
|
2011-12-09 06:44:13 -07:00
|
|
|
struct kvmppc_book3s_shadow_vcpu *svcpu;
|
2011-06-28 18:17:58 -06:00
|
|
|
ulong flags;
|
|
|
|
|
|
|
|
|
|
program_interrupt:
|
2011-12-09 06:44:13 -07:00
|
|
|
svcpu = svcpu_get(vcpu);
|
|
|
|
|
flags = svcpu->shadow_srr1 & 0x1f0000ull;
|
|
|
|
|
svcpu_put(svcpu);
|
2011-06-28 18:17:58 -06:00
|
|
|
|
|
|
|
|
if (vcpu->arch.shared->msr & MSR_PR) {
|
|
|
|
|
#ifdef EXIT_DEBUG
|
|
|
|
|
printk(KERN_INFO "Userspace triggered 0x700 exception at 0x%lx (0x%x)\n", kvmppc_get_pc(vcpu), kvmppc_get_last_inst(vcpu));
|
|
|
|
|
#endif
|
|
|
|
|
if ((kvmppc_get_last_inst(vcpu) & 0xff0007ff) !=
|
|
|
|
|
(INS_DCBZ & 0xfffffff7)) {
|
|
|
|
|
kvmppc_core_queue_program(vcpu, flags);
|
|
|
|
|
r = RESUME_GUEST;
|
|
|
|
|
break;
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
vcpu->stat.emulated_inst_exits++;
|
|
|
|
|
er = kvmppc_emulate_instruction(run, vcpu);
|
|
|
|
|
switch (er) {
|
|
|
|
|
case EMULATE_DONE:
|
|
|
|
|
r = RESUME_GUEST_NV;
|
|
|
|
|
break;
|
|
|
|
|
case EMULATE_AGAIN:
|
|
|
|
|
r = RESUME_GUEST;
|
|
|
|
|
break;
|
|
|
|
|
case EMULATE_FAIL:
|
|
|
|
|
printk(KERN_CRIT "%s: emulation at %lx failed (%08x)\n",
|
|
|
|
|
__func__, kvmppc_get_pc(vcpu), kvmppc_get_last_inst(vcpu));
|
|
|
|
|
kvmppc_core_queue_program(vcpu, flags);
|
|
|
|
|
r = RESUME_GUEST;
|
|
|
|
|
break;
|
|
|
|
|
case EMULATE_DO_MMIO:
|
|
|
|
|
run->exit_reason = KVM_EXIT_MMIO;
|
|
|
|
|
r = RESUME_HOST_NV;
|
|
|
|
|
break;
|
|
|
|
|
default:
|
|
|
|
|
BUG();
|
|
|
|
|
}
|
|
|
|
|
break;
|
|
|
|
|
}
|
|
|
|
|
case BOOK3S_INTERRUPT_SYSCALL:
|
2011-08-08 09:26:24 -06:00
|
|
|
if (vcpu->arch.papr_enabled &&
|
|
|
|
|
(kvmppc_get_last_inst(vcpu) == 0x44000022) &&
|
|
|
|
|
!(vcpu->arch.shared->msr & MSR_PR)) {
|
|
|
|
|
/* SC 1 papr hypercalls */
|
|
|
|
|
ulong cmd = kvmppc_get_gpr(vcpu, 3);
|
|
|
|
|
int i;
|
|
|
|
|
|
2011-11-08 00:17:39 -07:00
|
|
|
#ifdef CONFIG_KVM_BOOK3S_64_PR
|
2011-08-08 09:26:24 -06:00
|
|
|
if (kvmppc_h_pr(vcpu, cmd) == EMULATE_DONE) {
|
|
|
|
|
r = RESUME_GUEST;
|
|
|
|
|
break;
|
|
|
|
|
}
|
2011-11-08 00:17:39 -07:00
|
|
|
#endif
|
2011-08-08 09:26:24 -06:00
|
|
|
|
|
|
|
|
run->papr_hcall.nr = cmd;
|
|
|
|
|
for (i = 0; i < 9; ++i) {
|
|
|
|
|
ulong gpr = kvmppc_get_gpr(vcpu, 4 + i);
|
|
|
|
|
run->papr_hcall.args[i] = gpr;
|
|
|
|
|
}
|
|
|
|
|
run->exit_reason = KVM_EXIT_PAPR_HCALL;
|
|
|
|
|
vcpu->arch.hcall_needed = 1;
|
|
|
|
|
r = RESUME_HOST;
|
|
|
|
|
} else if (vcpu->arch.osi_enabled &&
|
2011-06-28 18:17:58 -06:00
|
|
|
(((u32)kvmppc_get_gpr(vcpu, 3)) == OSI_SC_MAGIC_R3) &&
|
|
|
|
|
(((u32)kvmppc_get_gpr(vcpu, 4)) == OSI_SC_MAGIC_R4)) {
|
|
|
|
|
/* MOL hypercalls */
|
|
|
|
|
u64 *gprs = run->osi.gprs;
|
|
|
|
|
int i;
|
|
|
|
|
|
|
|
|
|
run->exit_reason = KVM_EXIT_OSI;
|
|
|
|
|
for (i = 0; i < 32; i++)
|
|
|
|
|
gprs[i] = kvmppc_get_gpr(vcpu, i);
|
|
|
|
|
vcpu->arch.osi_needed = 1;
|
|
|
|
|
r = RESUME_HOST_NV;
|
|
|
|
|
} else if (!(vcpu->arch.shared->msr & MSR_PR) &&
|
|
|
|
|
(((u32)kvmppc_get_gpr(vcpu, 0)) == KVM_SC_MAGIC_R0)) {
|
|
|
|
|
/* KVM PV hypercalls */
|
|
|
|
|
kvmppc_set_gpr(vcpu, 3, kvmppc_kvm_pv(vcpu));
|
|
|
|
|
r = RESUME_GUEST;
|
|
|
|
|
} else {
|
|
|
|
|
/* Guest syscalls */
|
|
|
|
|
vcpu->stat.syscall_exits++;
|
|
|
|
|
kvmppc_book3s_queue_irqprio(vcpu, exit_nr);
|
|
|
|
|
r = RESUME_GUEST;
|
|
|
|
|
}
|
|
|
|
|
break;
|
|
|
|
|
case BOOK3S_INTERRUPT_FP_UNAVAIL:
|
|
|
|
|
case BOOK3S_INTERRUPT_ALTIVEC:
|
|
|
|
|
case BOOK3S_INTERRUPT_VSX:
|
|
|
|
|
{
|
|
|
|
|
int ext_msr = 0;
|
|
|
|
|
|
|
|
|
|
switch (exit_nr) {
|
|
|
|
|
case BOOK3S_INTERRUPT_FP_UNAVAIL: ext_msr = MSR_FP; break;
|
|
|
|
|
case BOOK3S_INTERRUPT_ALTIVEC: ext_msr = MSR_VEC; break;
|
|
|
|
|
case BOOK3S_INTERRUPT_VSX: ext_msr = MSR_VSX; break;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
switch (kvmppc_check_ext(vcpu, exit_nr)) {
|
|
|
|
|
case EMULATE_DONE:
|
|
|
|
|
/* everything ok - let's enable the ext */
|
|
|
|
|
r = kvmppc_handle_ext(vcpu, exit_nr, ext_msr);
|
|
|
|
|
break;
|
|
|
|
|
case EMULATE_FAIL:
|
|
|
|
|
/* we need to emulate this instruction */
|
|
|
|
|
goto program_interrupt;
|
|
|
|
|
break;
|
|
|
|
|
default:
|
|
|
|
|
/* nothing to worry about - go again */
|
|
|
|
|
break;
|
|
|
|
|
}
|
|
|
|
|
break;
|
|
|
|
|
}
|
|
|
|
|
case BOOK3S_INTERRUPT_ALIGNMENT:
|
|
|
|
|
if (kvmppc_read_inst(vcpu) == EMULATE_DONE) {
|
|
|
|
|
vcpu->arch.shared->dsisr = kvmppc_alignment_dsisr(vcpu,
|
|
|
|
|
kvmppc_get_last_inst(vcpu));
|
|
|
|
|
vcpu->arch.shared->dar = kvmppc_alignment_dar(vcpu,
|
|
|
|
|
kvmppc_get_last_inst(vcpu));
|
|
|
|
|
kvmppc_book3s_queue_irqprio(vcpu, exit_nr);
|
|
|
|
|
}
|
|
|
|
|
r = RESUME_GUEST;
|
|
|
|
|
break;
|
|
|
|
|
case BOOK3S_INTERRUPT_MACHINE_CHECK:
|
|
|
|
|
case BOOK3S_INTERRUPT_TRACE:
|
|
|
|
|
kvmppc_book3s_queue_irqprio(vcpu, exit_nr);
|
|
|
|
|
r = RESUME_GUEST;
|
|
|
|
|
break;
|
|
|
|
|
default:
|
2011-12-09 06:44:13 -07:00
|
|
|
{
|
|
|
|
|
struct kvmppc_book3s_shadow_vcpu *svcpu = svcpu_get(vcpu);
|
|
|
|
|
ulong shadow_srr1 = svcpu->shadow_srr1;
|
|
|
|
|
svcpu_put(svcpu);
|
2011-06-28 18:17:58 -06:00
|
|
|
/* Ugh - bork here! What did we get? */
|
|
|
|
|
printk(KERN_EMERG "exit_nr=0x%x | pc=0x%lx | msr=0x%lx\n",
|
2011-12-09 06:44:13 -07:00
|
|
|
exit_nr, kvmppc_get_pc(vcpu), shadow_srr1);
|
2011-06-28 18:17:58 -06:00
|
|
|
r = RESUME_HOST;
|
|
|
|
|
BUG();
|
|
|
|
|
break;
|
|
|
|
|
}
|
2011-12-09 06:44:13 -07:00
|
|
|
}
|
2011-06-28 18:17:58 -06:00
|
|
|
|
|
|
|
|
if (!(r & RESUME_HOST)) {
|
|
|
|
|
/* To avoid clobbering exit_reason, only check for signals if
|
|
|
|
|
* we aren't already exiting to userspace for some other
|
|
|
|
|
* reason. */
|
2011-12-19 05:36:55 -07:00
|
|
|
|
|
|
|
|
/*
|
|
|
|
|
* Interrupts could be timers for the guest which we have to
|
|
|
|
|
* inject again, so let's postpone them until we're in the guest
|
|
|
|
|
* and if we really did time things so badly, then we just exit
|
|
|
|
|
* again due to a host external interrupt.
|
|
|
|
|
*/
|
2012-08-12 17:04:19 -06:00
|
|
|
local_irq_disable();
|
2012-08-13 04:44:41 -06:00
|
|
|
s = kvmppc_prepare_to_enter(vcpu);
|
|
|
|
|
if (s <= 0) {
|
2012-08-12 17:04:19 -06:00
|
|
|
local_irq_enable();
|
2012-08-13 04:44:41 -06:00
|
|
|
r = s;
|
2012-08-12 04:42:30 -06:00
|
|
|
} else {
|
2012-08-12 17:04:19 -06:00
|
|
|
kvmppc_lazy_ee_enable();
|
2011-06-28 18:17:58 -06:00
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
trace_kvm_book3s_reenter(r, vcpu);
|
|
|
|
|
|
|
|
|
|
return r;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
int kvm_arch_vcpu_ioctl_get_sregs(struct kvm_vcpu *vcpu,
|
|
|
|
|
struct kvm_sregs *sregs)
|
|
|
|
|
{
|
|
|
|
|
struct kvmppc_vcpu_book3s *vcpu3s = to_book3s(vcpu);
|
|
|
|
|
int i;
|
|
|
|
|
|
|
|
|
|
sregs->pvr = vcpu->arch.pvr;
|
|
|
|
|
|
|
|
|
|
sregs->u.s.sdr1 = to_book3s(vcpu)->sdr1;
|
|
|
|
|
if (vcpu->arch.hflags & BOOK3S_HFLAG_SLB) {
|
|
|
|
|
for (i = 0; i < 64; i++) {
|
|
|
|
|
sregs->u.s.ppc64.slb[i].slbe = vcpu->arch.slb[i].orige | i;
|
|
|
|
|
sregs->u.s.ppc64.slb[i].slbv = vcpu->arch.slb[i].origv;
|
|
|
|
|
}
|
|
|
|
|
} else {
|
|
|
|
|
for (i = 0; i < 16; i++)
|
|
|
|
|
sregs->u.s.ppc32.sr[i] = vcpu->arch.shared->sr[i];
|
|
|
|
|
|
|
|
|
|
for (i = 0; i < 8; i++) {
|
|
|
|
|
sregs->u.s.ppc32.ibat[i] = vcpu3s->ibat[i].raw;
|
|
|
|
|
sregs->u.s.ppc32.dbat[i] = vcpu3s->dbat[i].raw;
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
int kvm_arch_vcpu_ioctl_set_sregs(struct kvm_vcpu *vcpu,
|
|
|
|
|
struct kvm_sregs *sregs)
|
|
|
|
|
{
|
|
|
|
|
struct kvmppc_vcpu_book3s *vcpu3s = to_book3s(vcpu);
|
|
|
|
|
int i;
|
|
|
|
|
|
|
|
|
|
kvmppc_set_pvr(vcpu, sregs->pvr);
|
|
|
|
|
|
|
|
|
|
vcpu3s->sdr1 = sregs->u.s.sdr1;
|
|
|
|
|
if (vcpu->arch.hflags & BOOK3S_HFLAG_SLB) {
|
|
|
|
|
for (i = 0; i < 64; i++) {
|
|
|
|
|
vcpu->arch.mmu.slbmte(vcpu, sregs->u.s.ppc64.slb[i].slbv,
|
|
|
|
|
sregs->u.s.ppc64.slb[i].slbe);
|
|
|
|
|
}
|
|
|
|
|
} else {
|
|
|
|
|
for (i = 0; i < 16; i++) {
|
|
|
|
|
vcpu->arch.mmu.mtsrin(vcpu, i, sregs->u.s.ppc32.sr[i]);
|
|
|
|
|
}
|
|
|
|
|
for (i = 0; i < 8; i++) {
|
|
|
|
|
kvmppc_set_bat(vcpu, &(vcpu3s->ibat[i]), false,
|
|
|
|
|
(u32)sregs->u.s.ppc32.ibat[i]);
|
|
|
|
|
kvmppc_set_bat(vcpu, &(vcpu3s->ibat[i]), true,
|
|
|
|
|
(u32)(sregs->u.s.ppc32.ibat[i] >> 32));
|
|
|
|
|
kvmppc_set_bat(vcpu, &(vcpu3s->dbat[i]), false,
|
|
|
|
|
(u32)sregs->u.s.ppc32.dbat[i]);
|
|
|
|
|
kvmppc_set_bat(vcpu, &(vcpu3s->dbat[i]), true,
|
|
|
|
|
(u32)(sregs->u.s.ppc32.dbat[i] >> 32));
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
/* Flush the MMU after messing with the segments */
|
|
|
|
|
kvmppc_mmu_pte_flush(vcpu, 0, 0);
|
|
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
|
}
|
|
|
|
|
|
2012-09-25 14:31:56 -06:00
|
|
|
int kvmppc_get_one_reg(struct kvm_vcpu *vcpu, u64 id, union kvmppc_one_reg *val)
|
2011-12-12 05:26:50 -07:00
|
|
|
{
|
2012-09-25 14:31:56 -06:00
|
|
|
int r = 0;
|
2011-12-12 05:26:50 -07:00
|
|
|
|
2012-09-25 14:31:56 -06:00
|
|
|
switch (id) {
|
2011-12-12 05:26:50 -07:00
|
|
|
case KVM_REG_PPC_HIOR:
|
2012-09-25 14:31:56 -06:00
|
|
|
*val = get_reg_val(id, to_book3s(vcpu)->hior);
|
2011-12-12 05:26:50 -07:00
|
|
|
break;
|
2012-09-25 14:32:30 -06:00
|
|
|
#ifdef CONFIG_VSX
|
|
|
|
|
case KVM_REG_PPC_VSR0 ... KVM_REG_PPC_VSR31: {
|
|
|
|
|
long int i = id - KVM_REG_PPC_VSR0;
|
|
|
|
|
|
|
|
|
|
if (!cpu_has_feature(CPU_FTR_VSX)) {
|
|
|
|
|
r = -ENXIO;
|
|
|
|
|
break;
|
|
|
|
|
}
|
|
|
|
|
val->vsxval[0] = vcpu->arch.fpr[i];
|
|
|
|
|
val->vsxval[1] = vcpu->arch.vsr[i];
|
|
|
|
|
break;
|
|
|
|
|
}
|
|
|
|
|
#endif /* CONFIG_VSX */
|
2011-12-12 05:26:50 -07:00
|
|
|
default:
|
2012-09-25 14:31:56 -06:00
|
|
|
r = -EINVAL;
|
2011-12-12 05:26:50 -07:00
|
|
|
break;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
return r;
|
|
|
|
|
}
|
|
|
|
|
|
2012-09-25 14:31:56 -06:00
|
|
|
int kvmppc_set_one_reg(struct kvm_vcpu *vcpu, u64 id, union kvmppc_one_reg *val)
|
2011-12-12 05:26:50 -07:00
|
|
|
{
|
2012-09-25 14:31:56 -06:00
|
|
|
int r = 0;
|
2011-12-12 05:26:50 -07:00
|
|
|
|
2012-09-25 14:31:56 -06:00
|
|
|
switch (id) {
|
2011-12-12 05:26:50 -07:00
|
|
|
case KVM_REG_PPC_HIOR:
|
2012-09-25 14:31:56 -06:00
|
|
|
to_book3s(vcpu)->hior = set_reg_val(id, *val);
|
|
|
|
|
to_book3s(vcpu)->hior_explicit = true;
|
2011-12-12 05:26:50 -07:00
|
|
|
break;
|
2012-09-25 14:32:30 -06:00
|
|
|
#ifdef CONFIG_VSX
|
|
|
|
|
case KVM_REG_PPC_VSR0 ... KVM_REG_PPC_VSR31: {
|
|
|
|
|
long int i = id - KVM_REG_PPC_VSR0;
|
|
|
|
|
|
|
|
|
|
if (!cpu_has_feature(CPU_FTR_VSX)) {
|
|
|
|
|
r = -ENXIO;
|
|
|
|
|
break;
|
|
|
|
|
}
|
|
|
|
|
vcpu->arch.fpr[i] = val->vsxval[0];
|
|
|
|
|
vcpu->arch.vsr[i] = val->vsxval[1];
|
|
|
|
|
break;
|
|
|
|
|
}
|
|
|
|
|
#endif /* CONFIG_VSX */
|
2011-12-12 05:26:50 -07:00
|
|
|
default:
|
2012-09-25 14:31:56 -06:00
|
|
|
r = -EINVAL;
|
2011-12-12 05:26:50 -07:00
|
|
|
break;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
return r;
|
|
|
|
|
}
|
|
|
|
|
|
2011-06-28 18:17:58 -06:00
|
|
|
int kvmppc_core_check_processor_compat(void)
|
|
|
|
|
{
|
|
|
|
|
return 0;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
struct kvm_vcpu *kvmppc_core_vcpu_create(struct kvm *kvm, unsigned int id)
|
|
|
|
|
{
|
|
|
|
|
struct kvmppc_vcpu_book3s *vcpu_book3s;
|
|
|
|
|
struct kvm_vcpu *vcpu;
|
|
|
|
|
int err = -ENOMEM;
|
|
|
|
|
unsigned long p;
|
|
|
|
|
|
|
|
|
|
vcpu_book3s = vzalloc(sizeof(struct kvmppc_vcpu_book3s));
|
|
|
|
|
if (!vcpu_book3s)
|
|
|
|
|
goto out;
|
|
|
|
|
|
|
|
|
|
vcpu_book3s->shadow_vcpu = (struct kvmppc_book3s_shadow_vcpu *)
|
|
|
|
|
kzalloc(sizeof(*vcpu_book3s->shadow_vcpu), GFP_KERNEL);
|
|
|
|
|
if (!vcpu_book3s->shadow_vcpu)
|
|
|
|
|
goto free_vcpu;
|
|
|
|
|
|
|
|
|
|
vcpu = &vcpu_book3s->vcpu;
|
|
|
|
|
err = kvm_vcpu_init(vcpu, kvm, id);
|
|
|
|
|
if (err)
|
|
|
|
|
goto free_shadow_vcpu;
|
|
|
|
|
|
|
|
|
|
p = __get_free_page(GFP_KERNEL|__GFP_ZERO);
|
|
|
|
|
/* the real shared page fills the last 4k of our page */
|
|
|
|
|
vcpu->arch.shared = (void*)(p + PAGE_SIZE - 4096);
|
|
|
|
|
if (!p)
|
|
|
|
|
goto uninit_vcpu;
|
|
|
|
|
|
|
|
|
|
#ifdef CONFIG_PPC_BOOK3S_64
|
|
|
|
|
/* default to book3s_64 (970fx) */
|
|
|
|
|
vcpu->arch.pvr = 0x3C0301;
|
|
|
|
|
#else
|
|
|
|
|
/* default to book3s_32 (750) */
|
|
|
|
|
vcpu->arch.pvr = 0x84202;
|
|
|
|
|
#endif
|
|
|
|
|
kvmppc_set_pvr(vcpu, vcpu->arch.pvr);
|
|
|
|
|
vcpu->arch.slb_nr = 64;
|
|
|
|
|
|
|
|
|
|
vcpu->arch.shadow_msr = MSR_USER64;
|
|
|
|
|
|
|
|
|
|
err = kvmppc_mmu_init(vcpu);
|
|
|
|
|
if (err < 0)
|
|
|
|
|
goto uninit_vcpu;
|
|
|
|
|
|
|
|
|
|
return vcpu;
|
|
|
|
|
|
|
|
|
|
uninit_vcpu:
|
|
|
|
|
kvm_vcpu_uninit(vcpu);
|
|
|
|
|
free_shadow_vcpu:
|
|
|
|
|
kfree(vcpu_book3s->shadow_vcpu);
|
|
|
|
|
free_vcpu:
|
|
|
|
|
vfree(vcpu_book3s);
|
|
|
|
|
out:
|
|
|
|
|
return ERR_PTR(err);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
void kvmppc_core_vcpu_free(struct kvm_vcpu *vcpu)
|
|
|
|
|
{
|
|
|
|
|
struct kvmppc_vcpu_book3s *vcpu_book3s = to_book3s(vcpu);
|
|
|
|
|
|
|
|
|
|
free_page((unsigned long)vcpu->arch.shared & PAGE_MASK);
|
|
|
|
|
kvm_vcpu_uninit(vcpu);
|
|
|
|
|
kfree(vcpu_book3s->shadow_vcpu);
|
|
|
|
|
vfree(vcpu_book3s);
|
|
|
|
|
}
|
|
|
|
|
|
2011-06-28 18:19:50 -06:00
|
|
|
int kvmppc_vcpu_run(struct kvm_run *kvm_run, struct kvm_vcpu *vcpu)
|
2011-06-28 18:17:58 -06:00
|
|
|
{
|
|
|
|
|
int ret;
|
|
|
|
|
double fpr[32][TS_FPRWIDTH];
|
|
|
|
|
unsigned int fpscr;
|
|
|
|
|
int fpexc_mode;
|
|
|
|
|
#ifdef CONFIG_ALTIVEC
|
|
|
|
|
vector128 vr[32];
|
|
|
|
|
vector128 vscr;
|
|
|
|
|
unsigned long uninitialized_var(vrsave);
|
|
|
|
|
int used_vr;
|
|
|
|
|
#endif
|
|
|
|
|
#ifdef CONFIG_VSX
|
|
|
|
|
int used_vsr;
|
|
|
|
|
#endif
|
|
|
|
|
ulong ext_msr;
|
|
|
|
|
|
2011-08-10 05:57:08 -06:00
|
|
|
/* Check if we can run the vcpu at all */
|
|
|
|
|
if (!vcpu->arch.sane) {
|
|
|
|
|
kvm_run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
|
2011-12-09 07:46:21 -07:00
|
|
|
ret = -EINVAL;
|
|
|
|
|
goto out;
|
2011-08-10 05:57:08 -06:00
|
|
|
}
|
|
|
|
|
|
2011-12-19 05:36:55 -07:00
|
|
|
/*
|
|
|
|
|
* Interrupts could be timers for the guest which we have to inject
|
|
|
|
|
* again, so let's postpone them until we're in the guest and if we
|
|
|
|
|
* really did time things so badly, then we just exit again due to
|
|
|
|
|
* a host external interrupt.
|
|
|
|
|
*/
|
2012-08-12 17:04:19 -06:00
|
|
|
local_irq_disable();
|
2012-08-13 04:44:41 -06:00
|
|
|
ret = kvmppc_prepare_to_enter(vcpu);
|
|
|
|
|
if (ret <= 0) {
|
2012-08-12 17:04:19 -06:00
|
|
|
local_irq_enable();
|
2011-12-09 07:46:21 -07:00
|
|
|
goto out;
|
2011-06-28 18:17:58 -06:00
|
|
|
}
|
|
|
|
|
|
|
|
|
|
/* Save FPU state in stack */
|
|
|
|
|
if (current->thread.regs->msr & MSR_FP)
|
|
|
|
|
giveup_fpu(current);
|
|
|
|
|
memcpy(fpr, current->thread.fpr, sizeof(current->thread.fpr));
|
|
|
|
|
fpscr = current->thread.fpscr.val;
|
|
|
|
|
fpexc_mode = current->thread.fpexc_mode;
|
|
|
|
|
|
|
|
|
|
#ifdef CONFIG_ALTIVEC
|
|
|
|
|
/* Save Altivec state in stack */
|
|
|
|
|
used_vr = current->thread.used_vr;
|
|
|
|
|
if (used_vr) {
|
|
|
|
|
if (current->thread.regs->msr & MSR_VEC)
|
|
|
|
|
giveup_altivec(current);
|
|
|
|
|
memcpy(vr, current->thread.vr, sizeof(current->thread.vr));
|
|
|
|
|
vscr = current->thread.vscr;
|
|
|
|
|
vrsave = current->thread.vrsave;
|
|
|
|
|
}
|
|
|
|
|
#endif
|
|
|
|
|
|
|
|
|
|
#ifdef CONFIG_VSX
|
|
|
|
|
/* Save VSX state in stack */
|
|
|
|
|
used_vsr = current->thread.used_vsr;
|
|
|
|
|
if (used_vsr && (current->thread.regs->msr & MSR_VSX))
|
KVM: PPC: Book3S PR: Fix VSX handling
This fixes various issues in how we were handling the VSX registers
that exist on POWER7 machines. First, we were running off the end
of the current->thread.fpr[] array. Ultimately this was because the
vcpu->arch.vsr[] array is sized to be able to store both the FP
registers and the extra VSX registers (i.e. 64 entries), but PR KVM
only uses it for the extra VSX registers (i.e. 32 entries).
Secondly, calling load_up_vsx() from C code is a really bad idea,
because it jumps to fast_exception_return at the end, rather than
returning with a blr instruction. This was causing it to jump off
to a random location with random register contents, since it was using
the largely uninitialized stack frame created by kvmppc_load_up_vsx.
In fact, it isn't necessary to call either __giveup_vsx or load_up_vsx,
since giveup_fpu and load_up_fpu handle the extra VSX registers as well
as the standard FP registers on machines with VSX. Also, since VSX
instructions can access the VMX registers and the FP registers as well
as the extra VSX registers, we have to load up the FP and VMX registers
before we can turn on the MSR_VSX bit for the guest. Conversely, if
we save away any of the VSX or FP registers, we have to turn off MSR_VSX
for the guest.
To handle all this, it is more convenient for a single call to
kvmppc_giveup_ext() to handle all the state saving that needs to be done,
so we make it take a set of MSR bits rather than just one, and the switch
statement becomes a series of if statements. Similarly kvmppc_handle_ext
needs to be able to load up more than one set of registers.
Signed-off-by: Paul Mackerras <paulus@samba.org>
Signed-off-by: Alexander Graf <agraf@suse.de>
2012-11-04 11:16:46 -07:00
|
|
|
__giveup_vsx(current);
|
2011-06-28 18:17:58 -06:00
|
|
|
#endif
|
|
|
|
|
|
|
|
|
|
/* Remember the MSR with disabled extensions */
|
|
|
|
|
ext_msr = current->thread.regs->msr;
|
|
|
|
|
|
|
|
|
|
/* Preload FPU if it's enabled */
|
|
|
|
|
if (vcpu->arch.shared->msr & MSR_FP)
|
|
|
|
|
kvmppc_handle_ext(vcpu, BOOK3S_INTERRUPT_FP_UNAVAIL, MSR_FP);
|
|
|
|
|
|
2012-08-12 17:04:19 -06:00
|
|
|
kvmppc_lazy_ee_enable();
|
2011-06-28 18:19:50 -06:00
|
|
|
|
|
|
|
|
ret = __kvmppc_vcpu_run(kvm_run, vcpu);
|
|
|
|
|
|
2012-08-12 04:42:30 -06:00
|
|
|
/* No need for kvm_guest_exit. It's done in handle_exit.
|
|
|
|
|
We also get here with interrupts enabled. */
|
2011-06-28 18:17:58 -06:00
|
|
|
|
|
|
|
|
/* Make sure we save the guest FPU/Altivec/VSX state */
|
KVM: PPC: Book3S PR: Fix VSX handling
This fixes various issues in how we were handling the VSX registers
that exist on POWER7 machines. First, we were running off the end
of the current->thread.fpr[] array. Ultimately this was because the
vcpu->arch.vsr[] array is sized to be able to store both the FP
registers and the extra VSX registers (i.e. 64 entries), but PR KVM
only uses it for the extra VSX registers (i.e. 32 entries).
Secondly, calling load_up_vsx() from C code is a really bad idea,
because it jumps to fast_exception_return at the end, rather than
returning with a blr instruction. This was causing it to jump off
to a random location with random register contents, since it was using
the largely uninitialized stack frame created by kvmppc_load_up_vsx.
In fact, it isn't necessary to call either __giveup_vsx or load_up_vsx,
since giveup_fpu and load_up_fpu handle the extra VSX registers as well
as the standard FP registers on machines with VSX. Also, since VSX
instructions can access the VMX registers and the FP registers as well
as the extra VSX registers, we have to load up the FP and VMX registers
before we can turn on the MSR_VSX bit for the guest. Conversely, if
we save away any of the VSX or FP registers, we have to turn off MSR_VSX
for the guest.
To handle all this, it is more convenient for a single call to
kvmppc_giveup_ext() to handle all the state saving that needs to be done,
so we make it take a set of MSR bits rather than just one, and the switch
statement becomes a series of if statements. Similarly kvmppc_handle_ext
needs to be able to load up more than one set of registers.
Signed-off-by: Paul Mackerras <paulus@samba.org>
Signed-off-by: Alexander Graf <agraf@suse.de>
2012-11-04 11:16:46 -07:00
|
|
|
kvmppc_giveup_ext(vcpu, MSR_FP | MSR_VEC | MSR_VSX);
|
|
|
|
|
|
|
|
|
|
current->thread.regs->msr = ext_msr;
|
2011-06-28 18:17:58 -06:00
|
|
|
|
KVM: PPC: Book3S PR: Fix VSX handling
This fixes various issues in how we were handling the VSX registers
that exist on POWER7 machines. First, we were running off the end
of the current->thread.fpr[] array. Ultimately this was because the
vcpu->arch.vsr[] array is sized to be able to store both the FP
registers and the extra VSX registers (i.e. 64 entries), but PR KVM
only uses it for the extra VSX registers (i.e. 32 entries).
Secondly, calling load_up_vsx() from C code is a really bad idea,
because it jumps to fast_exception_return at the end, rather than
returning with a blr instruction. This was causing it to jump off
to a random location with random register contents, since it was using
the largely uninitialized stack frame created by kvmppc_load_up_vsx.
In fact, it isn't necessary to call either __giveup_vsx or load_up_vsx,
since giveup_fpu and load_up_fpu handle the extra VSX registers as well
as the standard FP registers on machines with VSX. Also, since VSX
instructions can access the VMX registers and the FP registers as well
as the extra VSX registers, we have to load up the FP and VMX registers
before we can turn on the MSR_VSX bit for the guest. Conversely, if
we save away any of the VSX or FP registers, we have to turn off MSR_VSX
for the guest.
To handle all this, it is more convenient for a single call to
kvmppc_giveup_ext() to handle all the state saving that needs to be done,
so we make it take a set of MSR bits rather than just one, and the switch
statement becomes a series of if statements. Similarly kvmppc_handle_ext
needs to be able to load up more than one set of registers.
Signed-off-by: Paul Mackerras <paulus@samba.org>
Signed-off-by: Alexander Graf <agraf@suse.de>
2012-11-04 11:16:46 -07:00
|
|
|
/* Restore FPU/VSX state from stack */
|
2011-06-28 18:17:58 -06:00
|
|
|
memcpy(current->thread.fpr, fpr, sizeof(current->thread.fpr));
|
|
|
|
|
current->thread.fpscr.val = fpscr;
|
|
|
|
|
current->thread.fpexc_mode = fpexc_mode;
|
|
|
|
|
|
|
|
|
|
#ifdef CONFIG_ALTIVEC
|
|
|
|
|
/* Restore Altivec state from stack */
|
|
|
|
|
if (used_vr && current->thread.used_vr) {
|
|
|
|
|
memcpy(current->thread.vr, vr, sizeof(current->thread.vr));
|
|
|
|
|
current->thread.vscr = vscr;
|
|
|
|
|
current->thread.vrsave = vrsave;
|
|
|
|
|
}
|
|
|
|
|
current->thread.used_vr = used_vr;
|
|
|
|
|
#endif
|
|
|
|
|
|
|
|
|
|
#ifdef CONFIG_VSX
|
|
|
|
|
current->thread.used_vsr = used_vsr;
|
|
|
|
|
#endif
|
|
|
|
|
|
2011-12-09 07:46:21 -07:00
|
|
|
out:
|
2012-08-12 03:34:21 -06:00
|
|
|
vcpu->mode = OUTSIDE_GUEST_MODE;
|
2011-06-28 18:17:58 -06:00
|
|
|
return ret;
|
|
|
|
|
}
|
|
|
|
|
|
2011-12-14 19:03:22 -07:00
|
|
|
/*
|
|
|
|
|
* Get (and clear) the dirty memory log for a memory slot.
|
|
|
|
|
*/
|
|
|
|
|
int kvm_vm_ioctl_get_dirty_log(struct kvm *kvm,
|
|
|
|
|
struct kvm_dirty_log *log)
|
|
|
|
|
{
|
|
|
|
|
struct kvm_memory_slot *memslot;
|
|
|
|
|
struct kvm_vcpu *vcpu;
|
|
|
|
|
ulong ga, ga_end;
|
|
|
|
|
int is_dirty = 0;
|
|
|
|
|
int r;
|
|
|
|
|
unsigned long n;
|
|
|
|
|
|
|
|
|
|
mutex_lock(&kvm->slots_lock);
|
|
|
|
|
|
|
|
|
|
r = kvm_get_dirty_log(kvm, log, &is_dirty);
|
|
|
|
|
if (r)
|
|
|
|
|
goto out;
|
|
|
|
|
|
|
|
|
|
/* If nothing is dirty, don't bother messing with page tables. */
|
|
|
|
|
if (is_dirty) {
|
|
|
|
|
memslot = id_to_memslot(kvm->memslots, log->slot);
|
|
|
|
|
|
|
|
|
|
ga = memslot->base_gfn << PAGE_SHIFT;
|
|
|
|
|
ga_end = ga + (memslot->npages << PAGE_SHIFT);
|
|
|
|
|
|
|
|
|
|
kvm_for_each_vcpu(n, vcpu, kvm)
|
|
|
|
|
kvmppc_mmu_pte_pflush(vcpu, ga, ga_end);
|
|
|
|
|
|
|
|
|
|
n = kvm_dirty_bitmap_bytes(memslot);
|
|
|
|
|
memset(memslot->dirty_bitmap, 0, n);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
r = 0;
|
|
|
|
|
out:
|
|
|
|
|
mutex_unlock(&kvm->slots_lock);
|
|
|
|
|
return r;
|
|
|
|
|
}
|
|
|
|
|
|
2012-04-26 13:43:42 -06:00
|
|
|
#ifdef CONFIG_PPC64
|
|
|
|
|
int kvm_vm_ioctl_get_smmu_info(struct kvm *kvm, struct kvm_ppc_smmu_info *info)
|
|
|
|
|
{
|
|
|
|
|
/* No flags */
|
|
|
|
|
info->flags = 0;
|
|
|
|
|
|
|
|
|
|
/* SLB is always 64 entries */
|
|
|
|
|
info->slb_size = 64;
|
|
|
|
|
|
|
|
|
|
/* Standard 4k base page size segment */
|
|
|
|
|
info->sps[0].page_shift = 12;
|
|
|
|
|
info->sps[0].slb_enc = 0;
|
|
|
|
|
info->sps[0].enc[0].page_shift = 12;
|
|
|
|
|
info->sps[0].enc[0].pte_enc = 0;
|
|
|
|
|
|
|
|
|
|
/* Standard 16M large page size segment */
|
|
|
|
|
info->sps[1].page_shift = 24;
|
|
|
|
|
info->sps[1].slb_enc = SLB_VSID_L;
|
|
|
|
|
info->sps[1].enc[0].page_shift = 24;
|
|
|
|
|
info->sps[1].enc[0].pte_enc = 0;
|
|
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
|
}
|
|
|
|
|
#endif /* CONFIG_PPC64 */
|
|
|
|
|
|
2012-09-11 07:27:46 -06:00
|
|
|
void kvmppc_core_free_memslot(struct kvm_memory_slot *free,
|
|
|
|
|
struct kvm_memory_slot *dont)
|
|
|
|
|
{
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
int kvmppc_core_create_memslot(struct kvm_memory_slot *slot,
|
|
|
|
|
unsigned long npages)
|
|
|
|
|
{
|
|
|
|
|
return 0;
|
|
|
|
|
}
|
|
|
|
|
|
2011-06-28 18:19:22 -06:00
|
|
|
int kvmppc_core_prepare_memory_region(struct kvm *kvm,
|
2012-09-11 07:27:46 -06:00
|
|
|
struct kvm_memory_slot *memslot,
|
2011-06-28 18:19:22 -06:00
|
|
|
struct kvm_userspace_memory_region *mem)
|
|
|
|
|
{
|
|
|
|
|
return 0;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
void kvmppc_core_commit_memory_region(struct kvm *kvm,
|
2012-09-11 07:28:18 -06:00
|
|
|
struct kvm_userspace_memory_region *mem,
|
|
|
|
|
struct kvm_memory_slot old)
|
|
|
|
|
{
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
void kvmppc_core_flush_memslot(struct kvm *kvm, struct kvm_memory_slot *memslot)
|
2011-06-28 18:19:22 -06:00
|
|
|
{
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
int kvmppc_core_init_vm(struct kvm *kvm)
|
|
|
|
|
{
|
2012-03-15 15:58:34 -06:00
|
|
|
#ifdef CONFIG_PPC64
|
|
|
|
|
INIT_LIST_HEAD(&kvm->arch.spapr_tce_tables);
|
|
|
|
|
#endif
|
|
|
|
|
|
2011-06-28 18:19:22 -06:00
|
|
|
return 0;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
void kvmppc_core_destroy_vm(struct kvm *kvm)
|
|
|
|
|
{
|
2012-03-15 15:58:34 -06:00
|
|
|
#ifdef CONFIG_PPC64
|
|
|
|
|
WARN_ON(!list_empty(&kvm->arch.spapr_tce_tables));
|
|
|
|
|
#endif
|
2011-06-28 18:19:22 -06:00
|
|
|
}
|
|
|
|
|
|
2011-06-28 18:17:58 -06:00
|
|
|
static int kvmppc_book3s_init(void)
|
|
|
|
|
{
|
|
|
|
|
int r;
|
|
|
|
|
|
|
|
|
|
r = kvm_init(NULL, sizeof(struct kvmppc_vcpu_book3s), 0,
|
|
|
|
|
THIS_MODULE);
|
|
|
|
|
|
|
|
|
|
if (r)
|
|
|
|
|
return r;
|
|
|
|
|
|
|
|
|
|
r = kvmppc_mmu_hpte_sysinit();
|
|
|
|
|
|
|
|
|
|
return r;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static void kvmppc_book3s_exit(void)
|
|
|
|
|
{
|
|
|
|
|
kvmppc_mmu_hpte_sysexit();
|
|
|
|
|
kvm_exit();
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
module_init(kvmppc_book3s_init);
|
|
|
|
|
module_exit(kvmppc_book3s_exit);
|
