2005-04-16 16:20:36 -06:00
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#ifndef __ASM_APIC_H
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#define __ASM_APIC_H
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#include <linux/pm.h>
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[PATCH] i386: safe_apic_wait_icr_idle - i386
apic_wait_icr_idle looks like this:
static __inline__ void apic_wait_icr_idle(void)
{
while (apic_read(APIC_ICR) & APIC_ICR_BUSY)
cpu_relax();
}
The busy loop in this function would not be problematic if the
corresponding status bit in the ICR were always updated, but that does
not seem to be the case under certain crash scenarios. Kdump uses an IPI
to stop the other CPUs in the event of a crash, but when any of the
other CPUs are locked-up inside the NMI handler the CPU that sends the
IPI will end up looping forever in the ICR check, effectively
hard-locking the whole system.
Quoting from Intel's "MultiProcessor Specification" (Version 1.4), B-3:
"A local APIC unit indicates successful dispatch of an IPI by
resetting the Delivery Status bit in the Interrupt Command
Register (ICR). The operating system polls the delivery status
bit after sending an INIT or STARTUP IPI until the command has
been dispatched.
A period of 20 microseconds should be sufficient for IPI dispatch
to complete under normal operating conditions. If the IPI is not
successfully dispatched, the operating system can abort the
command. Alternatively, the operating system can retry the IPI by
writing the lower 32-bit double word of the ICR. This “time-out”
mechanism can be implemented through an external interrupt, if
interrupts are enabled on the processor, or through execution of
an instruction or time-stamp counter spin loop."
Intel's documentation suggests the implementation of a time-out
mechanism, which, by the way, is already being open-coded in some parts
of the kernel that tinker with ICR.
Create a apic_wait_icr_idle replacement that implements the time-out
mechanism and that can be used to solve the aforementioned problem.
AK: moved both functions out of line
AK: added improved loop from Keith Owens
Signed-off-by: Fernando Luis Vazquez Cao <fernando@oss.ntt.co.jp>
Signed-off-by: Andi Kleen <ak@suse.de>
2007-05-02 11:27:17 -06:00
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#include <linux/delay.h>
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2005-04-16 16:20:36 -06:00
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#include <asm/fixmap.h>
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#include <asm/apicdef.h>
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2005-06-25 15:57:41 -06:00
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#include <asm/processor.h>
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2005-04-16 16:20:36 -06:00
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#include <asm/system.h>
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#define Dprintk(x...)
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/*
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* Debugging macros
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*/
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#define APIC_QUIET 0
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#define APIC_VERBOSE 1
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#define APIC_DEBUG 2
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extern int apic_verbosity;
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/*
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* Define the default level of output to be very little
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* This can be turned up by using apic=verbose for more
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* information and apic=debug for _lots_ of information.
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* apic_verbosity is defined in apic.c
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*/
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#define apic_printk(v, s, a...) do { \
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if ((v) <= apic_verbosity) \
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printk(s, ##a); \
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} while (0)
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2006-09-26 02:52:32 -06:00
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extern void generic_apic_probe(void);
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2005-04-16 16:20:36 -06:00
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#ifdef CONFIG_X86_LOCAL_APIC
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/*
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* Basic functions accessing APICs.
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*/
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2006-12-06 18:14:08 -07:00
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#ifdef CONFIG_PARAVIRT
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#include <asm/paravirt.h>
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#else
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#define apic_write native_apic_write
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#define apic_write_atomic native_apic_write_atomic
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#define apic_read native_apic_read
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2007-02-13 05:26:21 -07:00
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#define setup_boot_clock setup_boot_APIC_clock
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#define setup_secondary_clock setup_secondary_APIC_clock
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2006-12-06 18:14:08 -07:00
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#endif
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2005-04-16 16:20:36 -06:00
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2006-12-06 18:14:08 -07:00
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static __inline fastcall void native_apic_write(unsigned long reg,
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unsigned long v)
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2005-04-16 16:20:36 -06:00
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{
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*((volatile unsigned long *)(APIC_BASE+reg)) = v;
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}
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2006-12-06 18:14:08 -07:00
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static __inline fastcall void native_apic_write_atomic(unsigned long reg,
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unsigned long v)
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2005-04-16 16:20:36 -06:00
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{
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xchg((volatile unsigned long *)(APIC_BASE+reg), v);
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}
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2006-12-06 18:14:08 -07:00
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static __inline fastcall unsigned long native_apic_read(unsigned long reg)
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2005-04-16 16:20:36 -06:00
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{
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return *((volatile unsigned long *)(APIC_BASE+reg));
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}
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[PATCH] i386: safe_apic_wait_icr_idle - i386
apic_wait_icr_idle looks like this:
static __inline__ void apic_wait_icr_idle(void)
{
while (apic_read(APIC_ICR) & APIC_ICR_BUSY)
cpu_relax();
}
The busy loop in this function would not be problematic if the
corresponding status bit in the ICR were always updated, but that does
not seem to be the case under certain crash scenarios. Kdump uses an IPI
to stop the other CPUs in the event of a crash, but when any of the
other CPUs are locked-up inside the NMI handler the CPU that sends the
IPI will end up looping forever in the ICR check, effectively
hard-locking the whole system.
Quoting from Intel's "MultiProcessor Specification" (Version 1.4), B-3:
"A local APIC unit indicates successful dispatch of an IPI by
resetting the Delivery Status bit in the Interrupt Command
Register (ICR). The operating system polls the delivery status
bit after sending an INIT or STARTUP IPI until the command has
been dispatched.
A period of 20 microseconds should be sufficient for IPI dispatch
to complete under normal operating conditions. If the IPI is not
successfully dispatched, the operating system can abort the
command. Alternatively, the operating system can retry the IPI by
writing the lower 32-bit double word of the ICR. This “time-out”
mechanism can be implemented through an external interrupt, if
interrupts are enabled on the processor, or through execution of
an instruction or time-stamp counter spin loop."
Intel's documentation suggests the implementation of a time-out
mechanism, which, by the way, is already being open-coded in some parts
of the kernel that tinker with ICR.
Create a apic_wait_icr_idle replacement that implements the time-out
mechanism and that can be used to solve the aforementioned problem.
AK: moved both functions out of line
AK: added improved loop from Keith Owens
Signed-off-by: Fernando Luis Vazquez Cao <fernando@oss.ntt.co.jp>
Signed-off-by: Andi Kleen <ak@suse.de>
2007-05-02 11:27:17 -06:00
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void apic_wait_icr_idle(void);
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unsigned long safe_apic_wait_icr_idle(void);
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2005-04-16 16:20:36 -06:00
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int get_physical_broadcast(void);
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#ifdef CONFIG_X86_GOOD_APIC
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# define FORCE_READ_AROUND_WRITE 0
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# define apic_read_around(x)
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# define apic_write_around(x,y) apic_write((x),(y))
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#else
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# define FORCE_READ_AROUND_WRITE 1
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# define apic_read_around(x) apic_read(x)
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# define apic_write_around(x,y) apic_write_atomic((x),(y))
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#endif
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static inline void ack_APIC_irq(void)
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{
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/*
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* ack_APIC_irq() actually gets compiled as a single instruction:
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* - a single rmw on Pentium/82489DX
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* - a single write on P6+ cores (CONFIG_X86_GOOD_APIC)
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* ... yummie.
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*/
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/* Docs say use 0 for future compatibility */
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apic_write_around(APIC_EOI, 0);
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}
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2007-02-16 02:27:58 -07:00
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extern int lapic_get_maxlvt(void);
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2005-04-16 16:20:36 -06:00
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extern void clear_local_APIC(void);
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extern void connect_bsp_APIC (void);
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2005-06-25 15:57:44 -06:00
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extern void disconnect_bsp_APIC (int virt_wire_setup);
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2005-04-16 16:20:36 -06:00
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extern void disable_local_APIC (void);
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extern void lapic_shutdown (void);
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extern int verify_local_APIC (void);
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extern void cache_APIC_registers (void);
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extern void sync_Arb_IDs (void);
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extern void init_bsp_APIC (void);
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extern void setup_local_APIC (void);
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extern void init_apic_mappings (void);
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IRQ: Maintain regs pointer globally rather than passing to IRQ handlers
Maintain a per-CPU global "struct pt_regs *" variable which can be used instead
of passing regs around manually through all ~1800 interrupt handlers in the
Linux kernel.
The regs pointer is used in few places, but it potentially costs both stack
space and code to pass it around. On the FRV arch, removing the regs parameter
from all the genirq function results in a 20% speed up of the IRQ exit path
(ie: from leaving timer_interrupt() to leaving do_IRQ()).
Where appropriate, an arch may override the generic storage facility and do
something different with the variable. On FRV, for instance, the address is
maintained in GR28 at all times inside the kernel as part of general exception
handling.
Having looked over the code, it appears that the parameter may be handed down
through up to twenty or so layers of functions. Consider a USB character
device attached to a USB hub, attached to a USB controller that posts its
interrupts through a cascaded auxiliary interrupt controller. A character
device driver may want to pass regs to the sysrq handler through the input
layer which adds another few layers of parameter passing.
I've build this code with allyesconfig for x86_64 and i386. I've runtested the
main part of the code on FRV and i386, though I can't test most of the drivers.
I've also done partial conversion for powerpc and MIPS - these at least compile
with minimal configurations.
This will affect all archs. Mostly the changes should be relatively easy.
Take do_IRQ(), store the regs pointer at the beginning, saving the old one:
struct pt_regs *old_regs = set_irq_regs(regs);
And put the old one back at the end:
set_irq_regs(old_regs);
Don't pass regs through to generic_handle_irq() or __do_IRQ().
In timer_interrupt(), this sort of change will be necessary:
- update_process_times(user_mode(regs));
- profile_tick(CPU_PROFILING, regs);
+ update_process_times(user_mode(get_irq_regs()));
+ profile_tick(CPU_PROFILING);
I'd like to move update_process_times()'s use of get_irq_regs() into itself,
except that i386, alone of the archs, uses something other than user_mode().
Some notes on the interrupt handling in the drivers:
(*) input_dev() is now gone entirely. The regs pointer is no longer stored in
the input_dev struct.
(*) finish_unlinks() in drivers/usb/host/ohci-q.c needs checking. It does
something different depending on whether it's been supplied with a regs
pointer or not.
(*) Various IRQ handler function pointers have been moved to type
irq_handler_t.
Signed-Off-By: David Howells <dhowells@redhat.com>
(cherry picked from 1b16e7ac850969f38b375e511e3fa2f474a33867 commit)
2006-10-05 07:55:46 -06:00
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extern void smp_local_timer_interrupt (void);
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2005-04-16 16:20:36 -06:00
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extern void setup_boot_APIC_clock (void);
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extern void setup_secondary_APIC_clock (void);
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extern int APIC_init_uniprocessor (void);
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extern void enable_NMI_through_LVT0 (void * dummy);
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2006-01-11 14:44:21 -07:00
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#define ARCH_APICTIMER_STOPS_ON_C3 1
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2006-03-08 18:57:25 -07:00
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extern int timer_over_8254;
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2007-03-23 09:08:01 -06:00
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extern int local_apic_timer_c2_ok;
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2006-03-08 18:57:25 -07:00
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2007-08-10 14:31:07 -06:00
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extern int local_apic_timer_disabled;
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2005-04-16 16:20:36 -06:00
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#else /* !CONFIG_X86_LOCAL_APIC */
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static inline void lapic_shutdown(void) { }
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2007-11-26 12:42:19 -07:00
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#define local_apic_timer_c2_ok 1
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2005-04-16 16:20:36 -06:00
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#endif /* !CONFIG_X86_LOCAL_APIC */
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#endif /* __ASM_APIC_H */
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