2005-09-03 16:56:11 -06:00
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/*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*
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* Copyright (C) 2005 by Ralf Baechle (ralf@linux-mips.org)
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*/
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#ifndef __ASM_QEMU_H
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#define __ASM_QEMU_H
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/*
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* Interrupt numbers
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*/
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#define Q_PIC_IRQ_BASE 0
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2007-10-11 16:46:09 -06:00
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#define Q_COUNT_COMPARE_IRQ 23
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2005-09-03 16:56:11 -06:00
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/*
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* Qemu clock rate. Unlike on real MIPS this has no relation to the
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* instruction issue rate, so the choosen value is pure fiction, just needs
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* to match the value in Qemu itself.
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*/
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#define QEMU_C0_COUNTER_CLOCK 100000000
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2006-05-15 11:59:34 -06:00
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/*
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* Magic qemu system control location.
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*/
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#define QEMU_RESTART_REG 0xBFBF0000
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#define QEMU_HALT_REG 0xBFBF0004
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2005-09-03 16:56:11 -06:00
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#endif /* __ASM_QEMU_H */
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