2008-05-23 02:32:46 -06:00
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/*
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2011-01-17 13:25:28 -07:00
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* Copyright (C) 2007-2011 Freescale Semiconductor, Inc.
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2008-05-23 02:32:46 -06:00
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*
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* Author: Tony Li <tony.li@freescale.com>
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* Jason Jin <Jason.jin@freescale.com>
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*
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* The hwirq alloc and free code reuse from sysdev/mpic_msi.c
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; version 2 of the
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* License.
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*
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*/
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#include <linux/irq.h>
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#include <linux/bootmem.h>
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#include <linux/msi.h>
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#include <linux/pci.h>
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include cleanup: Update gfp.h and slab.h includes to prepare for breaking implicit slab.h inclusion from percpu.h
percpu.h is included by sched.h and module.h and thus ends up being
included when building most .c files. percpu.h includes slab.h which
in turn includes gfp.h making everything defined by the two files
universally available and complicating inclusion dependencies.
percpu.h -> slab.h dependency is about to be removed. Prepare for
this change by updating users of gfp and slab facilities include those
headers directly instead of assuming availability. As this conversion
needs to touch large number of source files, the following script is
used as the basis of conversion.
http://userweb.kernel.org/~tj/misc/slabh-sweep.py
The script does the followings.
* Scan files for gfp and slab usages and update includes such that
only the necessary includes are there. ie. if only gfp is used,
gfp.h, if slab is used, slab.h.
* When the script inserts a new include, it looks at the include
blocks and try to put the new include such that its order conforms
to its surrounding. It's put in the include block which contains
core kernel includes, in the same order that the rest are ordered -
alphabetical, Christmas tree, rev-Xmas-tree or at the end if there
doesn't seem to be any matching order.
* If the script can't find a place to put a new include (mostly
because the file doesn't have fitting include block), it prints out
an error message indicating which .h file needs to be added to the
file.
The conversion was done in the following steps.
1. The initial automatic conversion of all .c files updated slightly
over 4000 files, deleting around 700 includes and adding ~480 gfp.h
and ~3000 slab.h inclusions. The script emitted errors for ~400
files.
2. Each error was manually checked. Some didn't need the inclusion,
some needed manual addition while adding it to implementation .h or
embedding .c file was more appropriate for others. This step added
inclusions to around 150 files.
3. The script was run again and the output was compared to the edits
from #2 to make sure no file was left behind.
4. Several build tests were done and a couple of problems were fixed.
e.g. lib/decompress_*.c used malloc/free() wrappers around slab
APIs requiring slab.h to be added manually.
5. The script was run on all .h files but without automatically
editing them as sprinkling gfp.h and slab.h inclusions around .h
files could easily lead to inclusion dependency hell. Most gfp.h
inclusion directives were ignored as stuff from gfp.h was usually
wildly available and often used in preprocessor macros. Each
slab.h inclusion directive was examined and added manually as
necessary.
6. percpu.h was updated not to include slab.h.
7. Build test were done on the following configurations and failures
were fixed. CONFIG_GCOV_KERNEL was turned off for all tests (as my
distributed build env didn't work with gcov compiles) and a few
more options had to be turned off depending on archs to make things
build (like ipr on powerpc/64 which failed due to missing writeq).
* x86 and x86_64 UP and SMP allmodconfig and a custom test config.
* powerpc and powerpc64 SMP allmodconfig
* sparc and sparc64 SMP allmodconfig
* ia64 SMP allmodconfig
* s390 SMP allmodconfig
* alpha SMP allmodconfig
* um on x86_64 SMP allmodconfig
8. percpu.h modifications were reverted so that it could be applied as
a separate patch and serve as bisection point.
Given the fact that I had only a couple of failures from tests on step
6, I'm fairly confident about the coverage of this conversion patch.
If there is a breakage, it's likely to be something in one of the arch
headers which should be easily discoverable easily on most builds of
the specific arch.
Signed-off-by: Tejun Heo <tj@kernel.org>
Guess-its-ok-by: Christoph Lameter <cl@linux-foundation.org>
Cc: Ingo Molnar <mingo@redhat.com>
Cc: Lee Schermerhorn <Lee.Schermerhorn@hp.com>
2010-03-24 02:04:11 -06:00
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#include <linux/slab.h>
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2008-05-23 02:32:46 -06:00
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#include <linux/of_platform.h>
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#include <sysdev/fsl_soc.h>
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#include <asm/prom.h>
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#include <asm/hw_irq.h>
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#include <asm/ppc-pci.h>
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2010-04-22 02:31:35 -06:00
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#include <asm/mpic.h>
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2011-12-13 13:51:59 -07:00
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#include <asm/fsl_hcalls.h>
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2008-05-23 02:32:46 -06:00
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#include "fsl_msi.h"
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2010-08-05 01:45:08 -06:00
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#include "fsl_pci.h"
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2008-05-23 02:32:46 -06:00
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2010-04-22 02:31:36 -06:00
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LIST_HEAD(msi_head);
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2008-05-23 02:32:46 -06:00
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struct fsl_msi_feature {
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u32 fsl_pic_ip;
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2011-09-23 11:41:35 -06:00
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u32 msiir_offset; /* Offset of MSIIR, relative to start of MSIR bank */
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2008-05-23 02:32:46 -06:00
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};
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2010-04-22 02:31:35 -06:00
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struct fsl_msi_cascade_data {
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struct fsl_msi *msi_data;
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int index;
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};
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2008-05-23 02:32:46 -06:00
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static inline u32 fsl_msi_read(u32 __iomem *base, unsigned int reg)
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{
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return in_be32(base + (reg >> 2));
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}
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/*
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* We do not need this actually. The MSIR register has been read once
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* in the cascade interrupt. So, this MSI interrupt has been acked
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*/
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2011-03-07 06:59:54 -07:00
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static void fsl_msi_end_irq(struct irq_data *d)
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2008-05-23 02:32:46 -06:00
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{
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}
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static struct irq_chip fsl_msi_chip = {
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2010-09-28 08:46:51 -06:00
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.irq_mask = mask_msi_irq,
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.irq_unmask = unmask_msi_irq,
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2011-03-07 06:59:54 -07:00
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.irq_ack = fsl_msi_end_irq,
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2010-01-31 13:33:41 -07:00
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.name = "FSL-MSI",
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2008-05-23 02:32:46 -06:00
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};
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2012-02-14 14:06:50 -07:00
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static int fsl_msi_host_map(struct irq_domain *h, unsigned int virq,
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2008-05-23 02:32:46 -06:00
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irq_hw_number_t hw)
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{
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2010-03-15 00:38:33 -06:00
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struct fsl_msi *msi_data = h->host_data;
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2008-05-23 02:32:46 -06:00
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struct irq_chip *chip = &fsl_msi_chip;
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2011-03-25 08:43:57 -06:00
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irq_set_status_flags(virq, IRQ_TYPE_EDGE_FALLING);
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2008-05-23 02:32:46 -06:00
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2011-03-25 09:45:20 -06:00
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irq_set_chip_data(virq, msi_data);
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irq_set_chip_and_handler(virq, chip, handle_edge_irq);
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2008-05-23 02:32:46 -06:00
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return 0;
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}
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2012-01-26 12:24:34 -07:00
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static const struct irq_domain_ops fsl_msi_host_ops = {
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2008-05-23 02:32:46 -06:00
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.map = fsl_msi_host_map,
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};
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static int fsl_msi_init_allocator(struct fsl_msi *msi_data)
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{
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2008-05-23 07:41:02 -06:00
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int rc;
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2008-05-23 02:32:46 -06:00
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2008-08-05 17:10:02 -06:00
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rc = msi_bitmap_alloc(&msi_data->bitmap, NR_MSI_IRQS,
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msi_data->irqhost->of_node);
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if (rc)
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return rc;
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2008-05-23 02:32:46 -06:00
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2008-08-05 17:10:02 -06:00
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rc = msi_bitmap_reserve_dt_hwirqs(&msi_data->bitmap);
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if (rc < 0) {
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msi_bitmap_free(&msi_data->bitmap);
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return rc;
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2008-05-23 02:32:46 -06:00
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}
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return 0;
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}
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static int fsl_msi_check_device(struct pci_dev *pdev, int nvec, int type)
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{
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if (type == PCI_CAP_ID_MSIX)
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pr_debug("fslmsi: MSI-X untested, trying anyway.\n");
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return 0;
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}
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static void fsl_teardown_msi_irqs(struct pci_dev *pdev)
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{
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struct msi_desc *entry;
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2010-03-15 00:38:33 -06:00
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struct fsl_msi *msi_data;
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2008-05-23 02:32:46 -06:00
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list_for_each_entry(entry, &pdev->msi_list, list) {
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if (entry->irq == NO_IRQ)
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continue;
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2011-05-10 13:30:11 -06:00
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msi_data = irq_get_chip_data(entry->irq);
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2011-03-25 09:45:20 -06:00
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irq_set_msi_desc(entry->irq, NULL);
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2008-08-05 17:10:02 -06:00
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msi_bitmap_free_hwirqs(&msi_data->bitmap,
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virq_to_hw(entry->irq), 1);
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2008-05-23 02:32:46 -06:00
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irq_dispose_mapping(entry->irq);
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}
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return;
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}
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static void fsl_compose_msi_msg(struct pci_dev *pdev, int hwirq,
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2010-03-15 00:38:33 -06:00
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struct msi_msg *msg,
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struct fsl_msi *fsl_msi_data)
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2008-05-23 02:32:46 -06:00
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{
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2010-03-15 00:38:33 -06:00
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struct fsl_msi *msi_data = fsl_msi_data;
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2009-05-12 14:51:56 -06:00
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struct pci_controller *hose = pci_bus_to_host(pdev->bus);
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2011-09-23 11:41:35 -06:00
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u64 address; /* Physical address of the MSIIR */
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int len;
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const u64 *reg;
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/* If the msi-address-64 property exists, then use it */
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reg = of_get_property(hose->dn, "msi-address-64", &len);
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if (reg && (len == sizeof(u64)))
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address = be64_to_cpup(reg);
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else
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address = fsl_pci_immrbar_base(hose) + msi_data->msiir_offset;
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2008-05-23 02:32:46 -06:00
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2011-09-23 11:41:35 -06:00
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msg->address_lo = lower_32_bits(address);
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msg->address_hi = upper_32_bits(address);
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2009-05-12 14:51:56 -06:00
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2008-05-23 02:32:46 -06:00
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msg->data = hwirq;
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pr_debug("%s: allocated srs: %d, ibs: %d\n",
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__func__, hwirq / IRQS_PER_MSI_REG, hwirq % IRQS_PER_MSI_REG);
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}
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static int fsl_setup_msi_irqs(struct pci_dev *pdev, int nvec, int type)
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{
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powerpc/fsl_msi: add support for the fsl, msi property in PCI nodes
On Freescale parts with multiple MSI controllers, the controllers are
combined into one "pool" of interrupts. Whenever a device requests an MSI
interrupt, the next available interrupt from the pool is selected,
regardless of which MSI controller the interrupt is from. This works
because each PCI bus has an ATMU to all of CCSR, so any PCI device can
access any MSI interrupt register.
The fsl,msi property is used to specify that a given PCI bus should only
use a specific MSI device. This is necessary, for example, with the
Freescale hypervisor, because the MSI devices are assigned to specific
partitions.
Ideally, we'd like to be able to assign MSI devices to PCI busses within
the MSI or PCI layers. However, there does not appear to be a mechanism
to do that. Whenever the MSI layer wants to allocate an MSI interrupt to
a PCI device, it just calls arch_setup_msi_irqs(). It would be nice if we
could register an MSI device with a specific PCI bus.
So instead we remember the phandles of each MSI device, and we use that to
limit our search for an available interrupt. Whenever we are asked to
allocate a new interrupt for a PCI device, we check the fsl,msi property
of the PCI bus for that device. If it exists, then as we are looping over
all MSI devices, we skip the ones that don't have a matching phandle.
Signed-off-by: Timur Tabi <timur@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-10-31 16:06:35 -06:00
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struct pci_controller *hose = pci_bus_to_host(pdev->bus);
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struct device_node *np;
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phandle phandle = 0;
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2010-04-22 02:31:36 -06:00
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int rc, hwirq = -ENOMEM;
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2008-05-23 02:32:46 -06:00
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unsigned int virq;
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struct msi_desc *entry;
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struct msi_msg msg;
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2010-03-15 00:38:33 -06:00
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struct fsl_msi *msi_data;
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2008-05-23 02:32:46 -06:00
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powerpc/fsl_msi: add support for the fsl, msi property in PCI nodes
On Freescale parts with multiple MSI controllers, the controllers are
combined into one "pool" of interrupts. Whenever a device requests an MSI
interrupt, the next available interrupt from the pool is selected,
regardless of which MSI controller the interrupt is from. This works
because each PCI bus has an ATMU to all of CCSR, so any PCI device can
access any MSI interrupt register.
The fsl,msi property is used to specify that a given PCI bus should only
use a specific MSI device. This is necessary, for example, with the
Freescale hypervisor, because the MSI devices are assigned to specific
partitions.
Ideally, we'd like to be able to assign MSI devices to PCI busses within
the MSI or PCI layers. However, there does not appear to be a mechanism
to do that. Whenever the MSI layer wants to allocate an MSI interrupt to
a PCI device, it just calls arch_setup_msi_irqs(). It would be nice if we
could register an MSI device with a specific PCI bus.
So instead we remember the phandles of each MSI device, and we use that to
limit our search for an available interrupt. Whenever we are asked to
allocate a new interrupt for a PCI device, we check the fsl,msi property
of the PCI bus for that device. If it exists, then as we are looping over
all MSI devices, we skip the ones that don't have a matching phandle.
Signed-off-by: Timur Tabi <timur@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-10-31 16:06:35 -06:00
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/*
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* If the PCI node has an fsl,msi property, then we need to use it
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* to find the specific MSI.
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*/
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np = of_parse_phandle(hose->dn, "fsl,msi", 0);
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if (np) {
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2011-12-13 13:51:59 -07:00
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if (of_device_is_compatible(np, "fsl,mpic-msi") ||
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of_device_is_compatible(np, "fsl,vmpic-msi"))
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powerpc/fsl_msi: add support for the fsl, msi property in PCI nodes
On Freescale parts with multiple MSI controllers, the controllers are
combined into one "pool" of interrupts. Whenever a device requests an MSI
interrupt, the next available interrupt from the pool is selected,
regardless of which MSI controller the interrupt is from. This works
because each PCI bus has an ATMU to all of CCSR, so any PCI device can
access any MSI interrupt register.
The fsl,msi property is used to specify that a given PCI bus should only
use a specific MSI device. This is necessary, for example, with the
Freescale hypervisor, because the MSI devices are assigned to specific
partitions.
Ideally, we'd like to be able to assign MSI devices to PCI busses within
the MSI or PCI layers. However, there does not appear to be a mechanism
to do that. Whenever the MSI layer wants to allocate an MSI interrupt to
a PCI device, it just calls arch_setup_msi_irqs(). It would be nice if we
could register an MSI device with a specific PCI bus.
So instead we remember the phandles of each MSI device, and we use that to
limit our search for an available interrupt. Whenever we are asked to
allocate a new interrupt for a PCI device, we check the fsl,msi property
of the PCI bus for that device. If it exists, then as we are looping over
all MSI devices, we skip the ones that don't have a matching phandle.
Signed-off-by: Timur Tabi <timur@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-10-31 16:06:35 -06:00
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phandle = np->phandle;
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else {
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2011-12-13 13:51:59 -07:00
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dev_err(&pdev->dev,
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"node %s has an invalid fsl,msi phandle %u\n",
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hose->dn->full_name, np->phandle);
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powerpc/fsl_msi: add support for the fsl, msi property in PCI nodes
On Freescale parts with multiple MSI controllers, the controllers are
combined into one "pool" of interrupts. Whenever a device requests an MSI
interrupt, the next available interrupt from the pool is selected,
regardless of which MSI controller the interrupt is from. This works
because each PCI bus has an ATMU to all of CCSR, so any PCI device can
access any MSI interrupt register.
The fsl,msi property is used to specify that a given PCI bus should only
use a specific MSI device. This is necessary, for example, with the
Freescale hypervisor, because the MSI devices are assigned to specific
partitions.
Ideally, we'd like to be able to assign MSI devices to PCI busses within
the MSI or PCI layers. However, there does not appear to be a mechanism
to do that. Whenever the MSI layer wants to allocate an MSI interrupt to
a PCI device, it just calls arch_setup_msi_irqs(). It would be nice if we
could register an MSI device with a specific PCI bus.
So instead we remember the phandles of each MSI device, and we use that to
limit our search for an available interrupt. Whenever we are asked to
allocate a new interrupt for a PCI device, we check the fsl,msi property
of the PCI bus for that device. If it exists, then as we are looping over
all MSI devices, we skip the ones that don't have a matching phandle.
Signed-off-by: Timur Tabi <timur@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-10-31 16:06:35 -06:00
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return -EINVAL;
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}
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}
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|
2008-05-23 02:32:46 -06:00
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|
list_for_each_entry(entry, &pdev->msi_list, list) {
|
powerpc/fsl_msi: add support for the fsl, msi property in PCI nodes
On Freescale parts with multiple MSI controllers, the controllers are
combined into one "pool" of interrupts. Whenever a device requests an MSI
interrupt, the next available interrupt from the pool is selected,
regardless of which MSI controller the interrupt is from. This works
because each PCI bus has an ATMU to all of CCSR, so any PCI device can
access any MSI interrupt register.
The fsl,msi property is used to specify that a given PCI bus should only
use a specific MSI device. This is necessary, for example, with the
Freescale hypervisor, because the MSI devices are assigned to specific
partitions.
Ideally, we'd like to be able to assign MSI devices to PCI busses within
the MSI or PCI layers. However, there does not appear to be a mechanism
to do that. Whenever the MSI layer wants to allocate an MSI interrupt to
a PCI device, it just calls arch_setup_msi_irqs(). It would be nice if we
could register an MSI device with a specific PCI bus.
So instead we remember the phandles of each MSI device, and we use that to
limit our search for an available interrupt. Whenever we are asked to
allocate a new interrupt for a PCI device, we check the fsl,msi property
of the PCI bus for that device. If it exists, then as we are looping over
all MSI devices, we skip the ones that don't have a matching phandle.
Signed-off-by: Timur Tabi <timur@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-10-31 16:06:35 -06:00
|
|
|
/*
|
|
|
|
* Loop over all the MSI devices until we find one that has an
|
|
|
|
* available interrupt.
|
|
|
|
*/
|
2010-04-22 02:31:36 -06:00
|
|
|
list_for_each_entry(msi_data, &msi_head, list) {
|
powerpc/fsl_msi: add support for the fsl, msi property in PCI nodes
On Freescale parts with multiple MSI controllers, the controllers are
combined into one "pool" of interrupts. Whenever a device requests an MSI
interrupt, the next available interrupt from the pool is selected,
regardless of which MSI controller the interrupt is from. This works
because each PCI bus has an ATMU to all of CCSR, so any PCI device can
access any MSI interrupt register.
The fsl,msi property is used to specify that a given PCI bus should only
use a specific MSI device. This is necessary, for example, with the
Freescale hypervisor, because the MSI devices are assigned to specific
partitions.
Ideally, we'd like to be able to assign MSI devices to PCI busses within
the MSI or PCI layers. However, there does not appear to be a mechanism
to do that. Whenever the MSI layer wants to allocate an MSI interrupt to
a PCI device, it just calls arch_setup_msi_irqs(). It would be nice if we
could register an MSI device with a specific PCI bus.
So instead we remember the phandles of each MSI device, and we use that to
limit our search for an available interrupt. Whenever we are asked to
allocate a new interrupt for a PCI device, we check the fsl,msi property
of the PCI bus for that device. If it exists, then as we are looping over
all MSI devices, we skip the ones that don't have a matching phandle.
Signed-off-by: Timur Tabi <timur@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-10-31 16:06:35 -06:00
|
|
|
/*
|
|
|
|
* If the PCI node has an fsl,msi property, then we
|
|
|
|
* restrict our search to the corresponding MSI node.
|
|
|
|
* The simplest way is to skip over MSI nodes with the
|
|
|
|
* wrong phandle. Under the Freescale hypervisor, this
|
|
|
|
* has the additional benefit of skipping over MSI
|
|
|
|
* nodes that are not mapped in the PAMU.
|
|
|
|
*/
|
|
|
|
if (phandle && (phandle != msi_data->phandle))
|
|
|
|
continue;
|
|
|
|
|
2010-04-22 02:31:36 -06:00
|
|
|
hwirq = msi_bitmap_alloc_hwirqs(&msi_data->bitmap, 1);
|
|
|
|
if (hwirq >= 0)
|
|
|
|
break;
|
|
|
|
}
|
2010-03-15 00:38:33 -06:00
|
|
|
|
2008-05-23 02:32:46 -06:00
|
|
|
if (hwirq < 0) {
|
|
|
|
rc = hwirq;
|
2011-12-13 13:51:59 -07:00
|
|
|
dev_err(&pdev->dev, "could not allocate MSI interrupt\n");
|
2008-05-23 02:32:46 -06:00
|
|
|
goto out_free;
|
|
|
|
}
|
|
|
|
|
|
|
|
virq = irq_create_mapping(msi_data->irqhost, hwirq);
|
|
|
|
|
|
|
|
if (virq == NO_IRQ) {
|
2011-12-13 13:51:59 -07:00
|
|
|
dev_err(&pdev->dev, "fail mapping hwirq %i\n", hwirq);
|
2008-08-05 17:10:02 -06:00
|
|
|
msi_bitmap_free_hwirqs(&msi_data->bitmap, hwirq, 1);
|
2008-05-23 02:32:46 -06:00
|
|
|
rc = -ENOSPC;
|
|
|
|
goto out_free;
|
|
|
|
}
|
2011-05-10 13:30:11 -06:00
|
|
|
/* chip_data is msi_data via host->hostdata in host->map() */
|
2011-03-25 09:45:20 -06:00
|
|
|
irq_set_msi_desc(virq, entry);
|
2008-05-23 02:32:46 -06:00
|
|
|
|
2010-03-15 00:38:33 -06:00
|
|
|
fsl_compose_msi_msg(pdev, hwirq, &msg, msi_data);
|
2008-05-23 02:32:46 -06:00
|
|
|
write_msi_msg(virq, &msg);
|
|
|
|
}
|
|
|
|
return 0;
|
|
|
|
|
|
|
|
out_free:
|
2010-04-22 02:31:36 -06:00
|
|
|
/* free by the caller of this function */
|
2008-05-23 02:32:46 -06:00
|
|
|
return rc;
|
|
|
|
}
|
|
|
|
|
2008-05-23 07:41:02 -06:00
|
|
|
static void fsl_msi_cascade(unsigned int irq, struct irq_desc *desc)
|
2008-05-23 02:32:46 -06:00
|
|
|
{
|
2011-03-28 08:46:02 -06:00
|
|
|
struct irq_chip *chip = irq_desc_get_chip(desc);
|
|
|
|
struct irq_data *idata = irq_desc_get_irq_data(desc);
|
2008-05-23 02:32:46 -06:00
|
|
|
unsigned int cascade_irq;
|
2010-04-22 02:31:35 -06:00
|
|
|
struct fsl_msi *msi_data;
|
2008-05-23 02:32:46 -06:00
|
|
|
int msir_index = -1;
|
|
|
|
u32 msir_value = 0;
|
|
|
|
u32 intr_index;
|
|
|
|
u32 have_shift = 0;
|
2010-04-22 02:31:35 -06:00
|
|
|
struct fsl_msi_cascade_data *cascade_data;
|
2011-12-13 13:51:59 -07:00
|
|
|
unsigned int ret;
|
2010-04-22 02:31:35 -06:00
|
|
|
|
2011-05-10 13:30:11 -06:00
|
|
|
cascade_data = irq_get_handler_data(irq);
|
2010-04-22 02:31:35 -06:00
|
|
|
msi_data = cascade_data->msi_data;
|
2008-05-23 02:32:46 -06:00
|
|
|
|
2009-11-17 08:46:45 -07:00
|
|
|
raw_spin_lock(&desc->lock);
|
2008-05-23 02:32:46 -06:00
|
|
|
if ((msi_data->feature & FSL_PIC_IP_MASK) == FSL_PIC_IP_IPIC) {
|
2011-03-07 06:59:54 -07:00
|
|
|
if (chip->irq_mask_ack)
|
2011-03-28 08:46:02 -06:00
|
|
|
chip->irq_mask_ack(idata);
|
2008-05-23 02:32:46 -06:00
|
|
|
else {
|
2011-03-28 08:46:02 -06:00
|
|
|
chip->irq_mask(idata);
|
|
|
|
chip->irq_ack(idata);
|
2008-05-23 02:32:46 -06:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2011-03-28 08:46:02 -06:00
|
|
|
if (unlikely(irqd_irq_inprogress(idata)))
|
2008-05-23 02:32:46 -06:00
|
|
|
goto unlock;
|
|
|
|
|
2010-04-22 02:31:35 -06:00
|
|
|
msir_index = cascade_data->index;
|
2008-05-23 02:32:46 -06:00
|
|
|
|
|
|
|
if (msir_index >= NR_MSI_REG)
|
|
|
|
cascade_irq = NO_IRQ;
|
|
|
|
|
2011-03-28 08:46:02 -06:00
|
|
|
irqd_set_chained_irq_inprogress(idata);
|
2010-03-15 00:38:33 -06:00
|
|
|
switch (msi_data->feature & FSL_PIC_IP_MASK) {
|
2008-05-23 02:32:46 -06:00
|
|
|
case FSL_PIC_IP_MPIC:
|
|
|
|
msir_value = fsl_msi_read(msi_data->msi_regs,
|
|
|
|
msir_index * 0x10);
|
|
|
|
break;
|
|
|
|
case FSL_PIC_IP_IPIC:
|
|
|
|
msir_value = fsl_msi_read(msi_data->msi_regs, msir_index * 0x4);
|
|
|
|
break;
|
2011-12-13 13:51:59 -07:00
|
|
|
case FSL_PIC_IP_VMPIC:
|
|
|
|
ret = fh_vmpic_get_msir(virq_to_hw(irq), &msir_value);
|
|
|
|
if (ret) {
|
|
|
|
pr_err("fsl-msi: fh_vmpic_get_msir() failed for "
|
|
|
|
"irq %u (ret=%u)\n", irq, ret);
|
|
|
|
msir_value = 0;
|
|
|
|
}
|
|
|
|
break;
|
2008-05-23 02:32:46 -06:00
|
|
|
}
|
|
|
|
|
|
|
|
while (msir_value) {
|
|
|
|
intr_index = ffs(msir_value) - 1;
|
|
|
|
|
|
|
|
cascade_irq = irq_linear_revmap(msi_data->irqhost,
|
2008-05-23 07:41:02 -06:00
|
|
|
msir_index * IRQS_PER_MSI_REG +
|
|
|
|
intr_index + have_shift);
|
2008-05-23 02:32:46 -06:00
|
|
|
if (cascade_irq != NO_IRQ)
|
|
|
|
generic_handle_irq(cascade_irq);
|
2008-05-23 07:41:02 -06:00
|
|
|
have_shift += intr_index + 1;
|
|
|
|
msir_value = msir_value >> (intr_index + 1);
|
2008-05-23 02:32:46 -06:00
|
|
|
}
|
2011-03-28 08:46:02 -06:00
|
|
|
irqd_clr_chained_irq_inprogress(idata);
|
2008-05-23 02:32:46 -06:00
|
|
|
|
|
|
|
switch (msi_data->feature & FSL_PIC_IP_MASK) {
|
|
|
|
case FSL_PIC_IP_MPIC:
|
2011-12-13 13:51:59 -07:00
|
|
|
case FSL_PIC_IP_VMPIC:
|
2011-03-28 08:46:02 -06:00
|
|
|
chip->irq_eoi(idata);
|
2008-05-23 02:32:46 -06:00
|
|
|
break;
|
|
|
|
case FSL_PIC_IP_IPIC:
|
2011-03-28 08:46:02 -06:00
|
|
|
if (!irqd_irq_disabled(idata) && chip->irq_unmask)
|
|
|
|
chip->irq_unmask(idata);
|
2008-05-23 02:32:46 -06:00
|
|
|
break;
|
|
|
|
}
|
|
|
|
unlock:
|
2009-11-17 08:46:45 -07:00
|
|
|
raw_spin_unlock(&desc->lock);
|
2008-05-23 02:32:46 -06:00
|
|
|
}
|
|
|
|
|
2010-07-22 15:52:34 -06:00
|
|
|
static int fsl_of_msi_remove(struct platform_device *ofdev)
|
2010-04-22 02:31:39 -06:00
|
|
|
{
|
2011-05-10 13:30:07 -06:00
|
|
|
struct fsl_msi *msi = platform_get_drvdata(ofdev);
|
2010-04-22 02:31:39 -06:00
|
|
|
int virq, i;
|
|
|
|
struct fsl_msi_cascade_data *cascade_data;
|
|
|
|
|
|
|
|
if (msi->list.prev != NULL)
|
|
|
|
list_del(&msi->list);
|
|
|
|
for (i = 0; i < NR_MSI_REG; i++) {
|
|
|
|
virq = msi->msi_virqs[i];
|
|
|
|
if (virq != NO_IRQ) {
|
2011-03-25 09:45:20 -06:00
|
|
|
cascade_data = irq_get_handler_data(virq);
|
2010-04-22 02:31:39 -06:00
|
|
|
kfree(cascade_data);
|
|
|
|
irq_dispose_mapping(virq);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
if (msi->bitmap.bitmap)
|
|
|
|
msi_bitmap_free(&msi->bitmap);
|
2011-12-13 13:51:59 -07:00
|
|
|
if ((msi->feature & FSL_PIC_IP_MASK) != FSL_PIC_IP_VMPIC)
|
|
|
|
iounmap(msi->msi_regs);
|
2010-04-22 02:31:39 -06:00
|
|
|
kfree(msi);
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2011-01-17 13:25:28 -07:00
|
|
|
static int __devinit fsl_msi_setup_hwirq(struct fsl_msi *msi,
|
|
|
|
struct platform_device *dev,
|
|
|
|
int offset, int irq_index)
|
|
|
|
{
|
|
|
|
struct fsl_msi_cascade_data *cascade_data = NULL;
|
|
|
|
int virt_msir;
|
|
|
|
|
|
|
|
virt_msir = irq_of_parse_and_map(dev->dev.of_node, irq_index);
|
|
|
|
if (virt_msir == NO_IRQ) {
|
|
|
|
dev_err(&dev->dev, "%s: Cannot translate IRQ index %d\n",
|
|
|
|
__func__, irq_index);
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
cascade_data = kzalloc(sizeof(struct fsl_msi_cascade_data), GFP_KERNEL);
|
|
|
|
if (!cascade_data) {
|
|
|
|
dev_err(&dev->dev, "No memory for MSI cascade data\n");
|
|
|
|
return -ENOMEM;
|
|
|
|
}
|
|
|
|
|
|
|
|
msi->msi_virqs[irq_index] = virt_msir;
|
2011-09-13 15:17:00 -06:00
|
|
|
cascade_data->index = offset;
|
2011-01-17 13:25:28 -07:00
|
|
|
cascade_data->msi_data = msi;
|
2011-03-25 09:45:20 -06:00
|
|
|
irq_set_handler_data(virt_msir, cascade_data);
|
|
|
|
irq_set_chained_handler(virt_msir, fsl_msi_cascade);
|
2011-01-17 13:25:28 -07:00
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2011-05-18 11:19:24 -06:00
|
|
|
static const struct of_device_id fsl_of_msi_ids[];
|
2011-02-22 19:59:54 -07:00
|
|
|
static int __devinit fsl_of_msi_probe(struct platform_device *dev)
|
2008-05-23 02:32:46 -06:00
|
|
|
{
|
2011-05-18 11:19:24 -06:00
|
|
|
const struct of_device_id *match;
|
2008-05-23 02:32:46 -06:00
|
|
|
struct fsl_msi *msi;
|
|
|
|
struct resource res;
|
2011-01-17 13:25:28 -07:00
|
|
|
int err, i, j, irq_index, count;
|
2008-05-23 02:32:46 -06:00
|
|
|
int rc;
|
|
|
|
const u32 *p;
|
2012-05-21 13:57:39 -06:00
|
|
|
const struct fsl_msi_feature *features;
|
2010-04-22 02:31:37 -06:00
|
|
|
int len;
|
|
|
|
u32 offset;
|
2011-01-17 13:25:28 -07:00
|
|
|
static const u32 all_avail[] = { 0, NR_MSI_IRQS };
|
2008-05-23 02:32:46 -06:00
|
|
|
|
2011-05-18 11:19:24 -06:00
|
|
|
match = of_match_device(fsl_of_msi_ids, &dev->dev);
|
|
|
|
if (!match)
|
2011-02-22 19:59:54 -07:00
|
|
|
return -EINVAL;
|
2011-05-18 11:19:24 -06:00
|
|
|
features = match->data;
|
2011-02-22 19:59:54 -07:00
|
|
|
|
2008-05-23 02:32:46 -06:00
|
|
|
printk(KERN_DEBUG "Setting up Freescale MSI support\n");
|
|
|
|
|
|
|
|
msi = kzalloc(sizeof(struct fsl_msi), GFP_KERNEL);
|
|
|
|
if (!msi) {
|
|
|
|
dev_err(&dev->dev, "No memory for MSI structure\n");
|
2010-04-22 02:31:39 -06:00
|
|
|
return -ENOMEM;
|
2008-05-23 02:32:46 -06:00
|
|
|
}
|
2011-05-10 13:30:07 -06:00
|
|
|
platform_set_drvdata(dev, msi);
|
2008-05-23 02:32:46 -06:00
|
|
|
|
2012-02-14 14:06:54 -07:00
|
|
|
msi->irqhost = irq_domain_add_linear(dev->dev.of_node,
|
|
|
|
NR_MSI_IRQS, &fsl_msi_host_ops, msi);
|
2008-05-23 02:32:46 -06:00
|
|
|
|
|
|
|
if (msi->irqhost == NULL) {
|
|
|
|
dev_err(&dev->dev, "No memory for MSI irqhost\n");
|
|
|
|
err = -ENOMEM;
|
|
|
|
goto error_out;
|
|
|
|
}
|
|
|
|
|
2011-12-13 13:51:59 -07:00
|
|
|
/*
|
|
|
|
* Under the Freescale hypervisor, the msi nodes don't have a 'reg'
|
|
|
|
* property. Instead, we use hypercalls to access the MSI.
|
|
|
|
*/
|
|
|
|
if ((features->fsl_pic_ip & FSL_PIC_IP_MASK) != FSL_PIC_IP_VMPIC) {
|
|
|
|
err = of_address_to_resource(dev->dev.of_node, 0, &res);
|
|
|
|
if (err) {
|
|
|
|
dev_err(&dev->dev, "invalid resource for node %s\n",
|
2010-04-13 17:12:29 -06:00
|
|
|
dev->dev.of_node->full_name);
|
2011-12-13 13:51:59 -07:00
|
|
|
goto error_out;
|
|
|
|
}
|
2008-05-23 02:32:46 -06:00
|
|
|
|
2011-12-13 13:51:59 -07:00
|
|
|
msi->msi_regs = ioremap(res.start, resource_size(&res));
|
|
|
|
if (!msi->msi_regs) {
|
2012-03-08 15:47:37 -07:00
|
|
|
err = -ENOMEM;
|
2011-12-13 13:51:59 -07:00
|
|
|
dev_err(&dev->dev, "could not map node %s\n",
|
|
|
|
dev->dev.of_node->full_name);
|
|
|
|
goto error_out;
|
|
|
|
}
|
|
|
|
msi->msiir_offset =
|
|
|
|
features->msiir_offset + (res.start & 0xfffff);
|
2008-05-23 02:32:46 -06:00
|
|
|
}
|
|
|
|
|
2008-05-23 07:41:02 -06:00
|
|
|
msi->feature = features->fsl_pic_ip;
|
2008-05-23 02:32:46 -06:00
|
|
|
|
powerpc/fsl_msi: add support for the fsl, msi property in PCI nodes
On Freescale parts with multiple MSI controllers, the controllers are
combined into one "pool" of interrupts. Whenever a device requests an MSI
interrupt, the next available interrupt from the pool is selected,
regardless of which MSI controller the interrupt is from. This works
because each PCI bus has an ATMU to all of CCSR, so any PCI device can
access any MSI interrupt register.
The fsl,msi property is used to specify that a given PCI bus should only
use a specific MSI device. This is necessary, for example, with the
Freescale hypervisor, because the MSI devices are assigned to specific
partitions.
Ideally, we'd like to be able to assign MSI devices to PCI busses within
the MSI or PCI layers. However, there does not appear to be a mechanism
to do that. Whenever the MSI layer wants to allocate an MSI interrupt to
a PCI device, it just calls arch_setup_msi_irqs(). It would be nice if we
could register an MSI device with a specific PCI bus.
So instead we remember the phandles of each MSI device, and we use that to
limit our search for an available interrupt. Whenever we are asked to
allocate a new interrupt for a PCI device, we check the fsl,msi property
of the PCI bus for that device. If it exists, then as we are looping over
all MSI devices, we skip the ones that don't have a matching phandle.
Signed-off-by: Timur Tabi <timur@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
2011-10-31 16:06:35 -06:00
|
|
|
/*
|
|
|
|
* Remember the phandle, so that we can match with any PCI nodes
|
|
|
|
* that have an "fsl,msi" property.
|
|
|
|
*/
|
|
|
|
msi->phandle = dev->dev.of_node->phandle;
|
|
|
|
|
2008-05-23 02:32:46 -06:00
|
|
|
rc = fsl_msi_init_allocator(msi);
|
|
|
|
if (rc) {
|
|
|
|
dev_err(&dev->dev, "Error allocating MSI bitmap\n");
|
|
|
|
goto error_out;
|
|
|
|
}
|
|
|
|
|
2011-01-17 13:25:28 -07:00
|
|
|
p = of_get_property(dev->dev.of_node, "msi-available-ranges", &len);
|
|
|
|
if (p && len % (2 * sizeof(u32)) != 0) {
|
|
|
|
dev_err(&dev->dev, "%s: Malformed msi-available-ranges property\n",
|
|
|
|
__func__);
|
2008-05-23 02:32:46 -06:00
|
|
|
err = -EINVAL;
|
|
|
|
goto error_out;
|
|
|
|
}
|
2011-01-17 13:25:28 -07:00
|
|
|
|
2011-09-13 15:17:00 -06:00
|
|
|
if (!p) {
|
2011-01-17 13:25:28 -07:00
|
|
|
p = all_avail;
|
2011-09-13 15:17:00 -06:00
|
|
|
len = sizeof(all_avail);
|
|
|
|
}
|
2011-01-17 13:25:28 -07:00
|
|
|
|
|
|
|
for (irq_index = 0, i = 0; i < len / (2 * sizeof(u32)); i++) {
|
|
|
|
if (p[i * 2] % IRQS_PER_MSI_REG ||
|
|
|
|
p[i * 2 + 1] % IRQS_PER_MSI_REG) {
|
|
|
|
printk(KERN_WARNING "%s: %s: msi available range of %u at %u is not IRQ-aligned\n",
|
|
|
|
__func__, dev->dev.of_node->full_name,
|
|
|
|
p[i * 2 + 1], p[i * 2]);
|
|
|
|
err = -EINVAL;
|
|
|
|
goto error_out;
|
|
|
|
}
|
|
|
|
|
|
|
|
offset = p[i * 2] / IRQS_PER_MSI_REG;
|
|
|
|
count = p[i * 2 + 1] / IRQS_PER_MSI_REG;
|
|
|
|
|
|
|
|
for (j = 0; j < count; j++, irq_index++) {
|
2011-09-13 15:17:00 -06:00
|
|
|
err = fsl_msi_setup_hwirq(msi, dev, offset + j, irq_index);
|
2011-01-17 13:25:28 -07:00
|
|
|
if (err)
|
2010-04-22 02:31:35 -06:00
|
|
|
goto error_out;
|
2008-05-23 02:32:46 -06:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2010-04-22 02:31:36 -06:00
|
|
|
list_add_tail(&msi->list, &msi_head);
|
2008-05-23 02:32:46 -06:00
|
|
|
|
2010-03-15 00:38:33 -06:00
|
|
|
/* The multiple setting ppc_md.setup_msi_irqs will not harm things */
|
|
|
|
if (!ppc_md.setup_msi_irqs) {
|
|
|
|
ppc_md.setup_msi_irqs = fsl_setup_msi_irqs;
|
|
|
|
ppc_md.teardown_msi_irqs = fsl_teardown_msi_irqs;
|
|
|
|
ppc_md.msi_check_device = fsl_msi_check_device;
|
|
|
|
} else if (ppc_md.setup_msi_irqs != fsl_setup_msi_irqs) {
|
|
|
|
dev_err(&dev->dev, "Different MSI driver already installed!\n");
|
|
|
|
err = -ENODEV;
|
|
|
|
goto error_out;
|
|
|
|
}
|
2008-05-23 02:32:46 -06:00
|
|
|
return 0;
|
|
|
|
error_out:
|
2010-04-22 02:31:39 -06:00
|
|
|
fsl_of_msi_remove(dev);
|
2008-05-23 02:32:46 -06:00
|
|
|
return err;
|
|
|
|
}
|
|
|
|
|
|
|
|
static const struct fsl_msi_feature mpic_msi_feature = {
|
|
|
|
.fsl_pic_ip = FSL_PIC_IP_MPIC,
|
|
|
|
.msiir_offset = 0x140,
|
|
|
|
};
|
|
|
|
|
|
|
|
static const struct fsl_msi_feature ipic_msi_feature = {
|
|
|
|
.fsl_pic_ip = FSL_PIC_IP_IPIC,
|
|
|
|
.msiir_offset = 0x38,
|
|
|
|
};
|
|
|
|
|
2011-12-13 13:51:59 -07:00
|
|
|
static const struct fsl_msi_feature vmpic_msi_feature = {
|
|
|
|
.fsl_pic_ip = FSL_PIC_IP_VMPIC,
|
|
|
|
.msiir_offset = 0,
|
|
|
|
};
|
|
|
|
|
2008-05-23 02:32:46 -06:00
|
|
|
static const struct of_device_id fsl_of_msi_ids[] = {
|
|
|
|
{
|
|
|
|
.compatible = "fsl,mpic-msi",
|
2012-07-13 10:24:26 -06:00
|
|
|
.data = &mpic_msi_feature,
|
2008-05-23 02:32:46 -06:00
|
|
|
},
|
|
|
|
{
|
|
|
|
.compatible = "fsl,ipic-msi",
|
2012-07-13 10:24:26 -06:00
|
|
|
.data = &ipic_msi_feature,
|
2008-05-23 02:32:46 -06:00
|
|
|
},
|
2011-12-13 13:51:59 -07:00
|
|
|
{
|
|
|
|
.compatible = "fsl,vmpic-msi",
|
2012-07-13 10:24:26 -06:00
|
|
|
.data = &vmpic_msi_feature,
|
2011-12-13 13:51:59 -07:00
|
|
|
},
|
2008-05-23 02:32:46 -06:00
|
|
|
{}
|
|
|
|
};
|
|
|
|
|
2011-02-22 19:59:54 -07:00
|
|
|
static struct platform_driver fsl_of_msi_driver = {
|
2010-04-13 17:13:02 -06:00
|
|
|
.driver = {
|
|
|
|
.name = "fsl-msi",
|
|
|
|
.owner = THIS_MODULE,
|
|
|
|
.of_match_table = fsl_of_msi_ids,
|
|
|
|
},
|
2008-05-23 02:32:46 -06:00
|
|
|
.probe = fsl_of_msi_probe,
|
2010-04-22 02:31:39 -06:00
|
|
|
.remove = fsl_of_msi_remove,
|
2008-05-23 02:32:46 -06:00
|
|
|
};
|
|
|
|
|
|
|
|
static __init int fsl_of_msi_init(void)
|
|
|
|
{
|
2011-02-22 19:59:54 -07:00
|
|
|
return platform_driver_register(&fsl_of_msi_driver);
|
2008-05-23 02:32:46 -06:00
|
|
|
}
|
|
|
|
|
|
|
|
subsys_initcall(fsl_of_msi_init);
|