kernel-fxtec-pro1x/arch/mips/include/asm/sparsemem.h

#ifndef _MIPS_SPARSEMEM_H
#define _MIPS_SPARSEMEM_H
#ifdef CONFIG_SPARSEMEM

/*
 * SECTION_SIZE_BITS		2^N: how big each section will be
 * MAX_PHYSMEM_BITS		2^N: how much memory we can have in that space
 */
#if defined(CONFIG_MIPS_HUGE_TLB_SUPPORT) && defined(CONFIG_PAGE_SIZE_64KB)
# define SECTION_SIZE_BITS	29
#else
# define SECTION_SIZE_BITS	28
#endif
#define MAX_PHYSMEM_BITS	48

#endif /* CONFIG_SPARSEMEM */
#endif /* _MIPS_SPARSEMEM_H */
[MIPS] Fix sparsemem support. Move memory_present() in arch/mips/kernel/setup.c. When using sparsemem extreme, this function does an allocate for bootmem. This would always fail since init_bootmem hasn't been called yet. Move memory_present after free_bootmem. This only marks actual memory ranges as present instead of the entire address space. Signed-off-by: Chad Reese <creese@caviumnetworks.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org> 2006-05-30 18:16:49 -06:00			`#ifndef _MIPS_SPARSEMEM_H`
			`#define _MIPS_SPARSEMEM_H`
			`#ifdef CONFIG_SPARSEMEM`

			`/*`
			`* SECTION_SIZE_BITS 2^N: how big each section will be`
			`* MAX_PHYSMEM_BITS 2^N: how much memory we can have in that space`
			`*/`
MIPS: Control huge tlb support via Kconfig symbol MIPS_HUGE_TLB_SUPPORT We need Huge TLBs for HUGETLB_PAGE, or the soon to follow TRANSPARENT_HUGEPAGE. collect this information under a single Kconfig symbol. Signed-off-by: David Daney <david.daney@cavium.com> 2012-10-16 16:48:10 -06:00			`#if defined(CONFIG_MIPS_HUGE_TLB_SUPPORT) && defined(CONFIG_PAGE_SIZE_64KB)`
MIPS: Handle huge pages with 64KB base page size. When using sparsemem, we need to adjust some constants as the resulting huge pages are 512MB in size. Signed-off-by: David Daney <david.daney@cavium.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/3745/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org> 2012-05-04 12:09:35 -06:00			`# define SECTION_SIZE_BITS 29`
			`#else`
			`# define SECTION_SIZE_BITS 28`
			`#endif`
MIPS: Add NUMA support for Loongson-3 Multiple Loongson-3A chips can be interconnected with HT0-bus. This is a CC-NUMA system that every chip (node) has its own local memory and cache coherency is maintained by hardware. The 64-bit physical memory address format is as follows: 0x-0000-YZZZ-ZZZZ-ZZZZ The high 16 bits should be 0, which means the real physical address supported by Loongson-3 is 48-bit. The "Y" bits is the base address of each node, which can be also considered as the node-id. The "Z" bits is the address offset within a node, which means every node has a 44 bits address space. Macros XPHYSADDR and MAX_PHYSMEM_BITS are modified unconditionally, because many other MIPS CPUs have also extended their address spaces. Signed-off-by: Huacai Chen <chenhc@lemote.com> Cc: John Crispin <john@phrozen.org> Cc: Steven J. Hill <Steven.Hill@imgtec.com> Cc: Aurelien Jarno <aurelien@aurel32.net> Cc: linux-mips@linux-mips.org Cc: Fuxin Zhang <zhangfx@lemote.com> Cc: Zhangjin Wu <wuzhangjin@gmail.com> Patchwork: https://patchwork.linux-mips.org/patch/7187/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org> 2014-06-25 21:41:28 -06:00			`#define MAX_PHYSMEM_BITS 48`
[MIPS] Fix sparsemem support. Move memory_present() in arch/mips/kernel/setup.c. When using sparsemem extreme, this function does an allocate for bootmem. This would always fail since init_bootmem hasn't been called yet. Move memory_present after free_bootmem. This only marks actual memory ranges as present instead of the entire address space. Signed-off-by: Chad Reese <creese@caviumnetworks.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org> 2006-05-30 18:16:49 -06:00
			`#endif /* CONFIG_SPARSEMEM */`
			`#endif /* _MIPS_SPARSEMEM_H */`