2005-11-07 01:58:22 -07:00
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/*
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* arch/sh/drivers/superhyway/ops-sh4-202.c
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*
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* SuperHyway bus support for SH4-202
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*
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* Copyright (C) 2005 Paul Mundt
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*
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* This file is subject to the terms and conditions of the GNU
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* General Public License. See the file "COPYING" in the main
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* directory of this archive for more details.
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*/
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#include <linux/kernel.h>
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#include <linux/init.h>
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#include <linux/superhyway.h>
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#include <linux/string.h>
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#include <asm/addrspace.h>
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#include <asm/io.h>
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#define PHYS_EMI_CBLOCK P4SEGADDR(0x1ec00000)
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#define PHYS_EMI_DBLOCK P4SEGADDR(0x08000000)
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#define PHYS_FEMI_CBLOCK P4SEGADDR(0x1f800000)
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#define PHYS_FEMI_DBLOCK P4SEGADDR(0x00000000)
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#define PHYS_EPBR_BLOCK P4SEGADDR(0x1de00000)
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#define PHYS_DMAC_BLOCK P4SEGADDR(0x1fa00000)
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#define PHYS_PBR_BLOCK P4SEGADDR(0x1fc00000)
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static struct resource emi_resources[] = {
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[0] = {
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.start = PHYS_EMI_CBLOCK,
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.end = PHYS_EMI_CBLOCK + 0x00300000 - 1,
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.flags = IORESOURCE_MEM,
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},
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[1] = {
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.start = PHYS_EMI_DBLOCK,
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.end = PHYS_EMI_DBLOCK + 0x08000000 - 1,
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.flags = IORESOURCE_MEM,
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},
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};
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static struct superhyway_device emi_device = {
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.name = "emi",
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.num_resources = ARRAY_SIZE(emi_resources),
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.resource = emi_resources,
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};
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static struct resource femi_resources[] = {
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[0] = {
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.start = PHYS_FEMI_CBLOCK,
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.end = PHYS_FEMI_CBLOCK + 0x00100000 - 1,
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.flags = IORESOURCE_MEM,
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},
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[1] = {
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.start = PHYS_FEMI_DBLOCK,
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.end = PHYS_FEMI_DBLOCK + 0x08000000 - 1,
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.flags = IORESOURCE_MEM,
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},
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};
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static struct superhyway_device femi_device = {
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.name = "femi",
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.num_resources = ARRAY_SIZE(femi_resources),
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.resource = femi_resources,
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};
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static struct resource epbr_resources[] = {
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[0] = {
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.start = P4SEGADDR(0x1e7ffff8),
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.end = P4SEGADDR(0x1e7ffff8 + (sizeof(u32) * 2) - 1),
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.flags = IORESOURCE_MEM,
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},
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[1] = {
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.start = PHYS_EPBR_BLOCK,
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.end = PHYS_EPBR_BLOCK + 0x00a00000 - 1,
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.flags = IORESOURCE_MEM,
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},
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};
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static struct superhyway_device epbr_device = {
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.name = "epbr",
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.num_resources = ARRAY_SIZE(epbr_resources),
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.resource = epbr_resources,
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};
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static struct resource dmac_resource = {
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.start = PHYS_DMAC_BLOCK,
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.end = PHYS_DMAC_BLOCK + 0x00100000 - 1,
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.flags = IORESOURCE_MEM,
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};
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static struct superhyway_device dmac_device = {
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.name = "dmac",
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.num_resources = 1,
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.resource = &dmac_resource,
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};
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static struct resource pbr_resources[] = {
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[0] = {
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.start = P4SEGADDR(0x1ffffff8),
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.end = P4SEGADDR(0x1ffffff8 + (sizeof(u32) * 2) - 1),
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.flags = IORESOURCE_MEM,
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},
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[1] = {
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.start = PHYS_PBR_BLOCK,
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.end = PHYS_PBR_BLOCK + 0x00400000 - (sizeof(u32) * 2) - 1,
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.flags = IORESOURCE_MEM,
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},
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};
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static struct superhyway_device pbr_device = {
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.name = "pbr",
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.num_resources = ARRAY_SIZE(pbr_resources),
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.resource = pbr_resources,
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};
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static struct superhyway_device *sh4202_devices[] __initdata = {
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&emi_device, &femi_device, &epbr_device, &dmac_device, &pbr_device,
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};
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static int sh4202_read_vcr(unsigned long base, struct superhyway_vcr_info *vcr)
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{
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u32 vcrh, vcrl;
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u64 tmp;
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/*
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* XXX: Even though the SH4-202 Evaluation Device documentation
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* indicates that VCRL is mapped first with VCRH at a + 0x04
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* offset, the opposite seems to be true.
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*
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* Some modules (PBR and ePBR for instance) also appear to have
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* VCRL/VCRH flipped in the documentation, but on the SH4-202
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* itself it appears that these are all consistently mapped with
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2007-05-13 17:15:10 -06:00
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* VCRH preceding VCRL.
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2005-11-07 01:58:22 -07:00
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*
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* Do not trust the documentation, for it is evil.
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*/
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vcrh = ctrl_inl(base);
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vcrl = ctrl_inl(base + sizeof(u32));
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tmp = ((u64)vcrh << 32) | vcrl;
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memcpy(vcr, &tmp, sizeof(u64));
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return 0;
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}
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static int sh4202_write_vcr(unsigned long base, struct superhyway_vcr_info vcr)
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{
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u64 tmp = *(u64 *)&vcr;
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ctrl_outl((tmp >> 32) & 0xffffffff, base);
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ctrl_outl(tmp & 0xffffffff, base + sizeof(u32));
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return 0;
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}
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static struct superhyway_ops sh4202_superhyway_ops = {
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.read_vcr = sh4202_read_vcr,
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.write_vcr = sh4202_write_vcr,
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};
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struct superhyway_bus superhyway_channels[] = {
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{ &sh4202_superhyway_ops, },
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{ 0, },
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};
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int __init superhyway_scan_bus(struct superhyway_bus *bus)
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{
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return superhyway_add_devices(bus, sh4202_devices,
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ARRAY_SIZE(sh4202_devices));
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}
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