kernel-fxtec-pro1x/arch/mips/include/asm/mach-au1x00/au1550_spi.h

/*
 * au1550_spi.h - Au1550 PSC SPI controller driver - platform data structure
 */

#ifndef _AU1550_SPI_H_
#define _AU1550_SPI_H_

struct au1550_spi_info {
	u32 mainclk_hz;		/* main input clock frequency of PSC */
	u16 num_chipselect;	/* number of chipselects supported */
	void (*activate_cs)(struct au1550_spi_info *spi, int cs, int polarity);
	void (*deactivate_cs)(struct au1550_spi_info *spi, int cs, int polarity);
};

#endif
au1550 SPI controller driver Here is a driver for the Alchemy au1550 PSC (Programmable Serial Controller) in SPI master mode. It supports dma transfers using the Alchemy descriptor based dma controller for 4-8 bits per word SPI transfers. For 9-24 bits per word transfers, pio irq based mode is used to avoid setup of dma channels from scratch on each number of bits per word change. Tested with au1550; this may also work on other MIPS Alchemy cpus, like au1200/au1210/au1250. Used extensively with SD card connected via SPI; this handles 8.1MHz SPI clock transfers using dma without any problem (the highest SPI clock freq possible with au1550 running on 324MHz). The driver supports sharing of SPI bus by multiple devices. All features of Alchemy SPI mode are supported (all SPI modes, msb/lsb first, bits per word in 4-24 range). As the SPI clock of the controller depends on main input clock that shall be configured externally, platform data structure for au1550 SPI controller driver contains mainclk_hz attribute to define the input clock rate. From this value, dividers of the controller for SPI clock are set up for required frequency. Signed-off-by: Jan Nikitenko <jan.nikitenko@gmail.com> Whitespace and section fixups. Remove partial workaround for platform setup bug in dma_mask setup; it couldn't work with multiple controllers. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org> 2007-05-08 01:32:25 -06:00			`/*`
[MIPS] Alchemy common headers style cleanup Fix several errors and warnings given by checkpatch.pl: - space after opening and before closing parentheses; - opening brace following 'struct' not on the same line; - leading spaces instead of tabs; - use of C99 // comments; - macros with complex values not enclosed in parentheses; - missing space between the type and asterisk in a variable declaration; - space between asterisk and function name; - including <asm/io.h> instead of <linux/io.h> and <asm/irq.h> instead of <linux/irq.h>; - use of '__inline__' instead of 'inline'; - space between function name and opening parenthesis; - line over 80 characters. In addition to these changes, also do the following: - remove needless parentheses; - insert spaces between operator and its operands; - replace spaces after the macro name with tabs in the #define directives and after the type in the structure field declarations; - remove excess tabs after the macro name in the #define directives and in the 'extern' variable declarations; - remove excess spaces between # and define for the SSI_*_MASK macros to align with other such macros; - put '\|\|' operator on the same line with its first operand; - properly indent multi-line function prototypes; - make the multi-line comment style consistent with the kernel style elsewhere by adding empty first line and/or adding space/asterisk on their left side; - make two-line comments that only have one line of text one-line; - convert the large multi-line comment in au1xxx_ide.h into several one-liners, replace spaces with tabs there; - fix typos/errors, capitalize acronyms, etc. in the comments; - insert missing and remove excess new lines; - update MontaVista copyright; - remove Pete Popov's and Steve Longerbeam's old email addresses... Signed-off-by: Sergei Shtylyov <sshtylyov@ru.mvista.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org> 2008-04-30 13:18:35 -06:00			`* au1550_spi.h - Au1550 PSC SPI controller driver - platform data structure`
au1550 SPI controller driver Here is a driver for the Alchemy au1550 PSC (Programmable Serial Controller) in SPI master mode. It supports dma transfers using the Alchemy descriptor based dma controller for 4-8 bits per word SPI transfers. For 9-24 bits per word transfers, pio irq based mode is used to avoid setup of dma channels from scratch on each number of bits per word change. Tested with au1550; this may also work on other MIPS Alchemy cpus, like au1200/au1210/au1250. Used extensively with SD card connected via SPI; this handles 8.1MHz SPI clock transfers using dma without any problem (the highest SPI clock freq possible with au1550 running on 324MHz). The driver supports sharing of SPI bus by multiple devices. All features of Alchemy SPI mode are supported (all SPI modes, msb/lsb first, bits per word in 4-24 range). As the SPI clock of the controller depends on main input clock that shall be configured externally, platform data structure for au1550 SPI controller driver contains mainclk_hz attribute to define the input clock rate. From this value, dividers of the controller for SPI clock are set up for required frequency. Signed-off-by: Jan Nikitenko <jan.nikitenko@gmail.com> Whitespace and section fixups. Remove partial workaround for platform setup bug in dma_mask setup; it couldn't work with multiple controllers. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org> 2007-05-08 01:32:25 -06:00			`*/`

			`#ifndef _AU1550_SPI_H_`
			`#define _AU1550_SPI_H_`

			`struct au1550_spi_info {`
			`u32 mainclk_hz; /* main input clock frequency of PSC */`
			`u16 num_chipselect; /* number of chipselects supported */`
			`void (activate_cs)(struct au1550_spi_info spi, int cs, int polarity);`
			`void (deactivate_cs)(struct au1550_spi_info spi, int cs, int polarity);`
			`};`

			`#endif`