2009-11-04 15:34:18 -07:00
|
|
|
/*
|
|
|
|
* MPC52xx SPI bus driver.
|
|
|
|
*
|
|
|
|
* Copyright (C) 2008 Secret Lab Technologies Ltd.
|
|
|
|
*
|
|
|
|
* This file is released under the GPLv2
|
|
|
|
*
|
|
|
|
* This is the driver for the MPC5200's dedicated SPI controller.
|
|
|
|
*
|
|
|
|
* Note: this driver does not support the MPC5200 PSC in SPI mode. For
|
|
|
|
* that driver see drivers/spi/mpc52xx_psc_spi.c
|
|
|
|
*/
|
|
|
|
|
|
|
|
#include <linux/module.h>
|
|
|
|
#include <linux/errno.h>
|
|
|
|
#include <linux/of_platform.h>
|
|
|
|
#include <linux/interrupt.h>
|
|
|
|
#include <linux/delay.h>
|
|
|
|
#include <linux/spi/spi.h>
|
|
|
|
#include <linux/io.h>
|
2009-11-13 02:41:17 -07:00
|
|
|
#include <linux/of_gpio.h>
|
include cleanup: Update gfp.h and slab.h includes to prepare for breaking implicit slab.h inclusion from percpu.h
percpu.h is included by sched.h and module.h and thus ends up being
included when building most .c files. percpu.h includes slab.h which
in turn includes gfp.h making everything defined by the two files
universally available and complicating inclusion dependencies.
percpu.h -> slab.h dependency is about to be removed. Prepare for
this change by updating users of gfp and slab facilities include those
headers directly instead of assuming availability. As this conversion
needs to touch large number of source files, the following script is
used as the basis of conversion.
http://userweb.kernel.org/~tj/misc/slabh-sweep.py
The script does the followings.
* Scan files for gfp and slab usages and update includes such that
only the necessary includes are there. ie. if only gfp is used,
gfp.h, if slab is used, slab.h.
* When the script inserts a new include, it looks at the include
blocks and try to put the new include such that its order conforms
to its surrounding. It's put in the include block which contains
core kernel includes, in the same order that the rest are ordered -
alphabetical, Christmas tree, rev-Xmas-tree or at the end if there
doesn't seem to be any matching order.
* If the script can't find a place to put a new include (mostly
because the file doesn't have fitting include block), it prints out
an error message indicating which .h file needs to be added to the
file.
The conversion was done in the following steps.
1. The initial automatic conversion of all .c files updated slightly
over 4000 files, deleting around 700 includes and adding ~480 gfp.h
and ~3000 slab.h inclusions. The script emitted errors for ~400
files.
2. Each error was manually checked. Some didn't need the inclusion,
some needed manual addition while adding it to implementation .h or
embedding .c file was more appropriate for others. This step added
inclusions to around 150 files.
3. The script was run again and the output was compared to the edits
from #2 to make sure no file was left behind.
4. Several build tests were done and a couple of problems were fixed.
e.g. lib/decompress_*.c used malloc/free() wrappers around slab
APIs requiring slab.h to be added manually.
5. The script was run on all .h files but without automatically
editing them as sprinkling gfp.h and slab.h inclusions around .h
files could easily lead to inclusion dependency hell. Most gfp.h
inclusion directives were ignored as stuff from gfp.h was usually
wildly available and often used in preprocessor macros. Each
slab.h inclusion directive was examined and added manually as
necessary.
6. percpu.h was updated not to include slab.h.
7. Build test were done on the following configurations and failures
were fixed. CONFIG_GCOV_KERNEL was turned off for all tests (as my
distributed build env didn't work with gcov compiles) and a few
more options had to be turned off depending on archs to make things
build (like ipr on powerpc/64 which failed due to missing writeq).
* x86 and x86_64 UP and SMP allmodconfig and a custom test config.
* powerpc and powerpc64 SMP allmodconfig
* sparc and sparc64 SMP allmodconfig
* ia64 SMP allmodconfig
* s390 SMP allmodconfig
* alpha SMP allmodconfig
* um on x86_64 SMP allmodconfig
8. percpu.h modifications were reverted so that it could be applied as
a separate patch and serve as bisection point.
Given the fact that I had only a couple of failures from tests on step
6, I'm fairly confident about the coverage of this conversion patch.
If there is a breakage, it's likely to be something in one of the arch
headers which should be easily discoverable easily on most builds of
the specific arch.
Signed-off-by: Tejun Heo <tj@kernel.org>
Guess-its-ok-by: Christoph Lameter <cl@linux-foundation.org>
Cc: Ingo Molnar <mingo@redhat.com>
Cc: Lee Schermerhorn <Lee.Schermerhorn@hp.com>
2010-03-24 02:04:11 -06:00
|
|
|
#include <linux/slab.h>
|
2009-11-04 15:34:18 -07:00
|
|
|
#include <asm/time.h>
|
|
|
|
#include <asm/mpc52xx.h>
|
|
|
|
|
|
|
|
MODULE_AUTHOR("Grant Likely <grant.likely@secretlab.ca>");
|
|
|
|
MODULE_DESCRIPTION("MPC52xx SPI (non-PSC) Driver");
|
|
|
|
MODULE_LICENSE("GPL");
|
|
|
|
|
|
|
|
/* Register offsets */
|
|
|
|
#define SPI_CTRL1 0x00
|
|
|
|
#define SPI_CTRL1_SPIE (1 << 7)
|
|
|
|
#define SPI_CTRL1_SPE (1 << 6)
|
|
|
|
#define SPI_CTRL1_MSTR (1 << 4)
|
|
|
|
#define SPI_CTRL1_CPOL (1 << 3)
|
|
|
|
#define SPI_CTRL1_CPHA (1 << 2)
|
|
|
|
#define SPI_CTRL1_SSOE (1 << 1)
|
|
|
|
#define SPI_CTRL1_LSBFE (1 << 0)
|
|
|
|
|
|
|
|
#define SPI_CTRL2 0x01
|
|
|
|
#define SPI_BRR 0x04
|
|
|
|
|
|
|
|
#define SPI_STATUS 0x05
|
|
|
|
#define SPI_STATUS_SPIF (1 << 7)
|
|
|
|
#define SPI_STATUS_WCOL (1 << 6)
|
|
|
|
#define SPI_STATUS_MODF (1 << 4)
|
|
|
|
|
|
|
|
#define SPI_DATA 0x09
|
|
|
|
#define SPI_PORTDATA 0x0d
|
|
|
|
#define SPI_DATADIR 0x10
|
|
|
|
|
|
|
|
/* FSM state return values */
|
|
|
|
#define FSM_STOP 0 /* Nothing more for the state machine to */
|
|
|
|
/* do. If something interesting happens */
|
2009-11-24 17:18:31 -07:00
|
|
|
/* then an IRQ will be received */
|
2009-11-04 15:34:18 -07:00
|
|
|
#define FSM_POLL 1 /* need to poll for completion, an IRQ is */
|
|
|
|
/* not expected */
|
|
|
|
#define FSM_CONTINUE 2 /* Keep iterating the state machine */
|
|
|
|
|
|
|
|
/* Driver internal data */
|
|
|
|
struct mpc52xx_spi {
|
|
|
|
struct spi_master *master;
|
|
|
|
void __iomem *regs;
|
|
|
|
int irq0; /* MODF irq */
|
|
|
|
int irq1; /* SPIF irq */
|
2009-11-24 17:18:31 -07:00
|
|
|
unsigned int ipb_freq;
|
2009-11-04 15:34:18 -07:00
|
|
|
|
2009-11-24 17:18:31 -07:00
|
|
|
/* Statistics; not used now, but will be reintroduced for debugfs */
|
2009-11-04 15:34:18 -07:00
|
|
|
int msg_count;
|
|
|
|
int wcol_count;
|
|
|
|
int wcol_ticks;
|
|
|
|
u32 wcol_tx_timestamp;
|
|
|
|
int modf_count;
|
|
|
|
int byte_count;
|
|
|
|
|
|
|
|
struct list_head queue; /* queue of pending messages */
|
|
|
|
spinlock_t lock;
|
|
|
|
struct work_struct work;
|
|
|
|
|
|
|
|
/* Details of current transfer (length, and buffer pointers) */
|
|
|
|
struct spi_message *message; /* current message */
|
|
|
|
struct spi_transfer *transfer; /* current transfer */
|
|
|
|
int (*state)(int irq, struct mpc52xx_spi *ms, u8 status, u8 data);
|
|
|
|
int len;
|
|
|
|
int timestamp;
|
|
|
|
u8 *rx_buf;
|
|
|
|
const u8 *tx_buf;
|
|
|
|
int cs_change;
|
2009-11-13 02:41:17 -07:00
|
|
|
int gpio_cs_count;
|
|
|
|
unsigned int *gpio_cs;
|
2009-11-04 15:34:18 -07:00
|
|
|
};
|
|
|
|
|
|
|
|
/*
|
|
|
|
* CS control function
|
|
|
|
*/
|
|
|
|
static void mpc52xx_spi_chipsel(struct mpc52xx_spi *ms, int value)
|
|
|
|
{
|
2009-11-13 02:41:17 -07:00
|
|
|
int cs;
|
|
|
|
|
|
|
|
if (ms->gpio_cs_count > 0) {
|
|
|
|
cs = ms->message->spi->chip_select;
|
|
|
|
gpio_set_value(ms->gpio_cs[cs], value ? 0 : 1);
|
|
|
|
} else
|
|
|
|
out_8(ms->regs + SPI_PORTDATA, value ? 0 : 0x08);
|
2009-11-04 15:34:18 -07:00
|
|
|
}
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Start a new transfer. This is called both by the idle state
|
|
|
|
* for the first transfer in a message, and by the wait state when the
|
|
|
|
* previous transfer in a message is complete.
|
|
|
|
*/
|
|
|
|
static void mpc52xx_spi_start_transfer(struct mpc52xx_spi *ms)
|
|
|
|
{
|
|
|
|
ms->rx_buf = ms->transfer->rx_buf;
|
|
|
|
ms->tx_buf = ms->transfer->tx_buf;
|
|
|
|
ms->len = ms->transfer->len;
|
|
|
|
|
|
|
|
/* Activate the chip select */
|
|
|
|
if (ms->cs_change)
|
|
|
|
mpc52xx_spi_chipsel(ms, 1);
|
|
|
|
ms->cs_change = ms->transfer->cs_change;
|
|
|
|
|
|
|
|
/* Write out the first byte */
|
|
|
|
ms->wcol_tx_timestamp = get_tbl();
|
|
|
|
if (ms->tx_buf)
|
|
|
|
out_8(ms->regs + SPI_DATA, *ms->tx_buf++);
|
|
|
|
else
|
|
|
|
out_8(ms->regs + SPI_DATA, 0);
|
|
|
|
}
|
|
|
|
|
|
|
|
/* Forward declaration of state handlers */
|
|
|
|
static int mpc52xx_spi_fsmstate_transfer(int irq, struct mpc52xx_spi *ms,
|
|
|
|
u8 status, u8 data);
|
|
|
|
static int mpc52xx_spi_fsmstate_wait(int irq, struct mpc52xx_spi *ms,
|
|
|
|
u8 status, u8 data);
|
|
|
|
|
|
|
|
/*
|
|
|
|
* IDLE state
|
|
|
|
*
|
|
|
|
* No transfers are in progress; if another transfer is pending then retrieve
|
|
|
|
* it and kick it off. Otherwise, stop processing the state machine
|
|
|
|
*/
|
|
|
|
static int
|
|
|
|
mpc52xx_spi_fsmstate_idle(int irq, struct mpc52xx_spi *ms, u8 status, u8 data)
|
|
|
|
{
|
|
|
|
struct spi_device *spi;
|
|
|
|
int spr, sppr;
|
|
|
|
u8 ctrl1;
|
|
|
|
|
|
|
|
if (status && (irq != NO_IRQ))
|
|
|
|
dev_err(&ms->master->dev, "spurious irq, status=0x%.2x\n",
|
|
|
|
status);
|
|
|
|
|
|
|
|
/* Check if there is another transfer waiting. */
|
|
|
|
if (list_empty(&ms->queue))
|
|
|
|
return FSM_STOP;
|
|
|
|
|
|
|
|
/* get the head of the queue */
|
|
|
|
ms->message = list_first_entry(&ms->queue, struct spi_message, queue);
|
|
|
|
list_del_init(&ms->message->queue);
|
|
|
|
|
|
|
|
/* Setup the controller parameters */
|
|
|
|
ctrl1 = SPI_CTRL1_SPIE | SPI_CTRL1_SPE | SPI_CTRL1_MSTR;
|
|
|
|
spi = ms->message->spi;
|
|
|
|
if (spi->mode & SPI_CPHA)
|
|
|
|
ctrl1 |= SPI_CTRL1_CPHA;
|
|
|
|
if (spi->mode & SPI_CPOL)
|
|
|
|
ctrl1 |= SPI_CTRL1_CPOL;
|
|
|
|
if (spi->mode & SPI_LSB_FIRST)
|
|
|
|
ctrl1 |= SPI_CTRL1_LSBFE;
|
|
|
|
out_8(ms->regs + SPI_CTRL1, ctrl1);
|
|
|
|
|
|
|
|
/* Setup the controller speed */
|
|
|
|
/* minimum divider is '2'. Also, add '1' to force rounding the
|
|
|
|
* divider up. */
|
|
|
|
sppr = ((ms->ipb_freq / ms->message->spi->max_speed_hz) + 1) >> 1;
|
|
|
|
spr = 0;
|
|
|
|
if (sppr < 1)
|
|
|
|
sppr = 1;
|
|
|
|
while (((sppr - 1) & ~0x7) != 0) {
|
|
|
|
sppr = (sppr + 1) >> 1; /* add '1' to force rounding up */
|
|
|
|
spr++;
|
|
|
|
}
|
|
|
|
sppr--; /* sppr quantity in register is offset by 1 */
|
|
|
|
if (spr > 7) {
|
|
|
|
/* Don't overrun limits of SPI baudrate register */
|
|
|
|
spr = 7;
|
|
|
|
sppr = 7;
|
|
|
|
}
|
|
|
|
out_8(ms->regs + SPI_BRR, sppr << 4 | spr); /* Set speed */
|
|
|
|
|
|
|
|
ms->cs_change = 1;
|
|
|
|
ms->transfer = container_of(ms->message->transfers.next,
|
|
|
|
struct spi_transfer, transfer_list);
|
|
|
|
|
|
|
|
mpc52xx_spi_start_transfer(ms);
|
|
|
|
ms->state = mpc52xx_spi_fsmstate_transfer;
|
|
|
|
|
|
|
|
return FSM_CONTINUE;
|
|
|
|
}
|
|
|
|
|
|
|
|
/*
|
|
|
|
* TRANSFER state
|
|
|
|
*
|
|
|
|
* In the middle of a transfer. If the SPI core has completed processing
|
|
|
|
* a byte, then read out the received data and write out the next byte
|
|
|
|
* (unless this transfer is finished; in which case go on to the wait
|
|
|
|
* state)
|
|
|
|
*/
|
|
|
|
static int mpc52xx_spi_fsmstate_transfer(int irq, struct mpc52xx_spi *ms,
|
|
|
|
u8 status, u8 data)
|
|
|
|
{
|
|
|
|
if (!status)
|
|
|
|
return ms->irq0 ? FSM_STOP : FSM_POLL;
|
|
|
|
|
|
|
|
if (status & SPI_STATUS_WCOL) {
|
|
|
|
/* The SPI controller is stoopid. At slower speeds, it may
|
|
|
|
* raise the SPIF flag before the state machine is actually
|
|
|
|
* finished, which causes a collision (internal to the state
|
|
|
|
* machine only). The manual recommends inserting a delay
|
|
|
|
* between receiving the interrupt and sending the next byte,
|
|
|
|
* but it can also be worked around simply by retrying the
|
|
|
|
* transfer which is what we do here. */
|
|
|
|
ms->wcol_count++;
|
|
|
|
ms->wcol_ticks += get_tbl() - ms->wcol_tx_timestamp;
|
|
|
|
ms->wcol_tx_timestamp = get_tbl();
|
|
|
|
data = 0;
|
|
|
|
if (ms->tx_buf)
|
2009-11-24 17:18:31 -07:00
|
|
|
data = *(ms->tx_buf - 1);
|
2009-11-04 15:34:18 -07:00
|
|
|
out_8(ms->regs + SPI_DATA, data); /* try again */
|
|
|
|
return FSM_CONTINUE;
|
|
|
|
} else if (status & SPI_STATUS_MODF) {
|
|
|
|
ms->modf_count++;
|
|
|
|
dev_err(&ms->master->dev, "mode fault\n");
|
|
|
|
mpc52xx_spi_chipsel(ms, 0);
|
|
|
|
ms->message->status = -EIO;
|
2014-04-02 08:21:04 -06:00
|
|
|
if (ms->message->complete)
|
|
|
|
ms->message->complete(ms->message->context);
|
2009-11-04 15:34:18 -07:00
|
|
|
ms->state = mpc52xx_spi_fsmstate_idle;
|
|
|
|
return FSM_CONTINUE;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* Read data out of the spi device */
|
|
|
|
ms->byte_count++;
|
|
|
|
if (ms->rx_buf)
|
|
|
|
*ms->rx_buf++ = data;
|
|
|
|
|
|
|
|
/* Is the transfer complete? */
|
|
|
|
ms->len--;
|
|
|
|
if (ms->len == 0) {
|
|
|
|
ms->timestamp = get_tbl();
|
|
|
|
ms->timestamp += ms->transfer->delay_usecs * tb_ticks_per_usec;
|
|
|
|
ms->state = mpc52xx_spi_fsmstate_wait;
|
|
|
|
return FSM_CONTINUE;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* Write out the next byte */
|
|
|
|
ms->wcol_tx_timestamp = get_tbl();
|
|
|
|
if (ms->tx_buf)
|
|
|
|
out_8(ms->regs + SPI_DATA, *ms->tx_buf++);
|
|
|
|
else
|
|
|
|
out_8(ms->regs + SPI_DATA, 0);
|
|
|
|
|
|
|
|
return FSM_CONTINUE;
|
|
|
|
}
|
|
|
|
|
|
|
|
/*
|
|
|
|
* WAIT state
|
|
|
|
*
|
|
|
|
* A transfer has completed; need to wait for the delay period to complete
|
|
|
|
* before starting the next transfer
|
|
|
|
*/
|
|
|
|
static int
|
|
|
|
mpc52xx_spi_fsmstate_wait(int irq, struct mpc52xx_spi *ms, u8 status, u8 data)
|
|
|
|
{
|
|
|
|
if (status && irq)
|
|
|
|
dev_err(&ms->master->dev, "spurious irq, status=0x%.2x\n",
|
|
|
|
status);
|
|
|
|
|
|
|
|
if (((int)get_tbl()) - ms->timestamp < 0)
|
|
|
|
return FSM_POLL;
|
|
|
|
|
|
|
|
ms->message->actual_length += ms->transfer->len;
|
|
|
|
|
|
|
|
/* Check if there is another transfer in this message. If there
|
|
|
|
* aren't then deactivate CS, notify sender, and drop back to idle
|
|
|
|
* to start the next message. */
|
|
|
|
if (ms->transfer->transfer_list.next == &ms->message->transfers) {
|
|
|
|
ms->msg_count++;
|
|
|
|
mpc52xx_spi_chipsel(ms, 0);
|
|
|
|
ms->message->status = 0;
|
2014-04-02 08:21:04 -06:00
|
|
|
if (ms->message->complete)
|
|
|
|
ms->message->complete(ms->message->context);
|
2009-11-04 15:34:18 -07:00
|
|
|
ms->state = mpc52xx_spi_fsmstate_idle;
|
|
|
|
return FSM_CONTINUE;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* There is another transfer; kick it off */
|
|
|
|
|
|
|
|
if (ms->cs_change)
|
|
|
|
mpc52xx_spi_chipsel(ms, 0);
|
|
|
|
|
|
|
|
ms->transfer = container_of(ms->transfer->transfer_list.next,
|
|
|
|
struct spi_transfer, transfer_list);
|
|
|
|
mpc52xx_spi_start_transfer(ms);
|
|
|
|
ms->state = mpc52xx_spi_fsmstate_transfer;
|
|
|
|
return FSM_CONTINUE;
|
|
|
|
}
|
|
|
|
|
|
|
|
/**
|
|
|
|
* mpc52xx_spi_fsm_process - Finite State Machine iteration function
|
|
|
|
* @irq: irq number that triggered the FSM or 0 for polling
|
|
|
|
* @ms: pointer to mpc52xx_spi driver data
|
|
|
|
*/
|
|
|
|
static void mpc52xx_spi_fsm_process(int irq, struct mpc52xx_spi *ms)
|
|
|
|
{
|
|
|
|
int rc = FSM_CONTINUE;
|
|
|
|
u8 status, data;
|
|
|
|
|
|
|
|
while (rc == FSM_CONTINUE) {
|
|
|
|
/* Interrupt cleared by read of STATUS followed by
|
|
|
|
* read of DATA registers */
|
|
|
|
status = in_8(ms->regs + SPI_STATUS);
|
|
|
|
data = in_8(ms->regs + SPI_DATA);
|
|
|
|
rc = ms->state(irq, ms, status, data);
|
|
|
|
}
|
|
|
|
|
|
|
|
if (rc == FSM_POLL)
|
|
|
|
schedule_work(&ms->work);
|
|
|
|
}
|
|
|
|
|
|
|
|
/**
|
|
|
|
* mpc52xx_spi_irq - IRQ handler
|
|
|
|
*/
|
|
|
|
static irqreturn_t mpc52xx_spi_irq(int irq, void *_ms)
|
|
|
|
{
|
|
|
|
struct mpc52xx_spi *ms = _ms;
|
|
|
|
spin_lock(&ms->lock);
|
|
|
|
mpc52xx_spi_fsm_process(irq, ms);
|
|
|
|
spin_unlock(&ms->lock);
|
|
|
|
return IRQ_HANDLED;
|
|
|
|
}
|
|
|
|
|
|
|
|
/**
|
|
|
|
* mpc52xx_spi_wq - Workqueue function for polling the state machine
|
|
|
|
*/
|
|
|
|
static void mpc52xx_spi_wq(struct work_struct *work)
|
|
|
|
{
|
|
|
|
struct mpc52xx_spi *ms = container_of(work, struct mpc52xx_spi, work);
|
|
|
|
unsigned long flags;
|
|
|
|
|
|
|
|
spin_lock_irqsave(&ms->lock, flags);
|
|
|
|
mpc52xx_spi_fsm_process(0, ms);
|
|
|
|
spin_unlock_irqrestore(&ms->lock, flags);
|
|
|
|
}
|
|
|
|
|
|
|
|
/*
|
|
|
|
* spi_master ops
|
|
|
|
*/
|
|
|
|
|
|
|
|
static int mpc52xx_spi_transfer(struct spi_device *spi, struct spi_message *m)
|
|
|
|
{
|
|
|
|
struct mpc52xx_spi *ms = spi_master_get_devdata(spi->master);
|
|
|
|
unsigned long flags;
|
|
|
|
|
|
|
|
m->actual_length = 0;
|
|
|
|
m->status = -EINPROGRESS;
|
|
|
|
|
|
|
|
spin_lock_irqsave(&ms->lock, flags);
|
|
|
|
list_add_tail(&m->queue, &ms->queue);
|
|
|
|
spin_unlock_irqrestore(&ms->lock, flags);
|
|
|
|
schedule_work(&ms->work);
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
/*
|
|
|
|
* OF Platform Bus Binding
|
|
|
|
*/
|
2012-12-07 09:57:14 -07:00
|
|
|
static int mpc52xx_spi_probe(struct platform_device *op)
|
2009-11-04 15:34:18 -07:00
|
|
|
{
|
|
|
|
struct spi_master *master;
|
|
|
|
struct mpc52xx_spi *ms;
|
|
|
|
void __iomem *regs;
|
2009-11-13 02:41:15 -07:00
|
|
|
u8 ctrl1;
|
2009-11-13 02:41:17 -07:00
|
|
|
int rc, i = 0;
|
|
|
|
int gpio_cs;
|
2009-11-04 15:34:18 -07:00
|
|
|
|
|
|
|
/* MMIO registers */
|
|
|
|
dev_dbg(&op->dev, "probing mpc5200 SPI device\n");
|
2010-04-13 17:12:29 -06:00
|
|
|
regs = of_iomap(op->dev.of_node, 0);
|
2009-11-04 15:34:18 -07:00
|
|
|
if (!regs)
|
|
|
|
return -ENODEV;
|
|
|
|
|
|
|
|
/* initialize the device */
|
2009-11-13 02:41:15 -07:00
|
|
|
ctrl1 = SPI_CTRL1_SPIE | SPI_CTRL1_SPE | SPI_CTRL1_MSTR;
|
|
|
|
out_8(regs + SPI_CTRL1, ctrl1);
|
2009-11-04 15:34:18 -07:00
|
|
|
out_8(regs + SPI_CTRL2, 0x0);
|
|
|
|
out_8(regs + SPI_DATADIR, 0xe); /* Set output pins */
|
|
|
|
out_8(regs + SPI_PORTDATA, 0x8); /* Deassert /SS signal */
|
|
|
|
|
|
|
|
/* Clear the status register and re-read it to check for a MODF
|
|
|
|
* failure. This driver cannot currently handle multiple masters
|
|
|
|
* on the SPI bus. This fault will also occur if the SPI signals
|
|
|
|
* are not connected to any pins (port_config setting) */
|
|
|
|
in_8(regs + SPI_STATUS);
|
2009-11-13 02:41:15 -07:00
|
|
|
out_8(regs + SPI_CTRL1, ctrl1);
|
|
|
|
|
2009-11-04 15:34:18 -07:00
|
|
|
in_8(regs + SPI_DATA);
|
|
|
|
if (in_8(regs + SPI_STATUS) & SPI_STATUS_MODF) {
|
|
|
|
dev_err(&op->dev, "mode fault; is port_config correct?\n");
|
|
|
|
rc = -EIO;
|
|
|
|
goto err_init;
|
|
|
|
}
|
|
|
|
|
|
|
|
dev_dbg(&op->dev, "allocating spi_master struct\n");
|
|
|
|
master = spi_alloc_master(&op->dev, sizeof *ms);
|
|
|
|
if (!master) {
|
|
|
|
rc = -ENOMEM;
|
|
|
|
goto err_alloc;
|
|
|
|
}
|
2009-11-13 02:41:17 -07:00
|
|
|
|
2009-11-04 15:34:18 -07:00
|
|
|
master->transfer = mpc52xx_spi_transfer;
|
2009-11-13 02:41:16 -07:00
|
|
|
master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_LSB_FIRST;
|
2014-03-28 09:37:54 -06:00
|
|
|
master->bits_per_word_mask = SPI_BPW_MASK(8);
|
2010-07-27 14:35:58 -06:00
|
|
|
master->dev.of_node = op->dev.of_node;
|
2009-11-13 02:41:16 -07:00
|
|
|
|
2013-05-23 04:20:40 -06:00
|
|
|
platform_set_drvdata(op, master);
|
2009-11-04 15:34:18 -07:00
|
|
|
|
|
|
|
ms = spi_master_get_devdata(master);
|
|
|
|
ms->master = master;
|
|
|
|
ms->regs = regs;
|
2010-04-13 17:12:29 -06:00
|
|
|
ms->irq0 = irq_of_parse_and_map(op->dev.of_node, 0);
|
|
|
|
ms->irq1 = irq_of_parse_and_map(op->dev.of_node, 1);
|
2009-11-04 15:34:18 -07:00
|
|
|
ms->state = mpc52xx_spi_fsmstate_idle;
|
2010-04-13 17:12:29 -06:00
|
|
|
ms->ipb_freq = mpc5xxx_get_bus_frequency(op->dev.of_node);
|
|
|
|
ms->gpio_cs_count = of_gpio_count(op->dev.of_node);
|
2009-11-13 02:41:17 -07:00
|
|
|
if (ms->gpio_cs_count > 0) {
|
|
|
|
master->num_chipselect = ms->gpio_cs_count;
|
|
|
|
ms->gpio_cs = kmalloc(ms->gpio_cs_count * sizeof(unsigned int),
|
|
|
|
GFP_KERNEL);
|
|
|
|
if (!ms->gpio_cs) {
|
|
|
|
rc = -ENOMEM;
|
2012-08-18 10:29:21 -06:00
|
|
|
goto err_alloc_gpio;
|
2009-11-13 02:41:17 -07:00
|
|
|
}
|
|
|
|
|
|
|
|
for (i = 0; i < ms->gpio_cs_count; i++) {
|
2010-04-13 17:12:29 -06:00
|
|
|
gpio_cs = of_get_gpio(op->dev.of_node, i);
|
2009-11-13 02:41:17 -07:00
|
|
|
if (gpio_cs < 0) {
|
|
|
|
dev_err(&op->dev,
|
|
|
|
"could not parse the gpio field "
|
|
|
|
"in oftree\n");
|
|
|
|
rc = -ENODEV;
|
|
|
|
goto err_gpio;
|
|
|
|
}
|
|
|
|
|
|
|
|
rc = gpio_request(gpio_cs, dev_name(&op->dev));
|
|
|
|
if (rc) {
|
|
|
|
dev_err(&op->dev,
|
|
|
|
"can't request spi cs gpio #%d "
|
|
|
|
"on gpio line %d\n", i, gpio_cs);
|
|
|
|
goto err_gpio;
|
|
|
|
}
|
|
|
|
|
|
|
|
gpio_direction_output(gpio_cs, 1);
|
|
|
|
ms->gpio_cs[i] = gpio_cs;
|
|
|
|
}
|
2009-11-24 17:18:31 -07:00
|
|
|
}
|
2009-11-13 02:41:17 -07:00
|
|
|
|
2009-11-04 15:34:18 -07:00
|
|
|
spin_lock_init(&ms->lock);
|
|
|
|
INIT_LIST_HEAD(&ms->queue);
|
|
|
|
INIT_WORK(&ms->work, mpc52xx_spi_wq);
|
|
|
|
|
|
|
|
/* Decide if interrupts can be used */
|
|
|
|
if (ms->irq0 && ms->irq1) {
|
2009-11-24 17:18:31 -07:00
|
|
|
rc = request_irq(ms->irq0, mpc52xx_spi_irq, 0,
|
2009-11-04 15:34:18 -07:00
|
|
|
"mpc5200-spi-modf", ms);
|
2009-11-24 17:18:31 -07:00
|
|
|
rc |= request_irq(ms->irq1, mpc52xx_spi_irq, 0,
|
|
|
|
"mpc5200-spi-spif", ms);
|
2009-11-04 15:34:18 -07:00
|
|
|
if (rc) {
|
|
|
|
free_irq(ms->irq0, ms);
|
|
|
|
free_irq(ms->irq1, ms);
|
|
|
|
ms->irq0 = ms->irq1 = 0;
|
|
|
|
}
|
|
|
|
} else {
|
|
|
|
/* operate in polled mode */
|
|
|
|
ms->irq0 = ms->irq1 = 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
if (!ms->irq0)
|
|
|
|
dev_info(&op->dev, "using polled mode\n");
|
|
|
|
|
|
|
|
dev_dbg(&op->dev, "registering spi_master struct\n");
|
|
|
|
rc = spi_register_master(master);
|
|
|
|
if (rc)
|
|
|
|
goto err_register;
|
|
|
|
|
|
|
|
dev_info(&ms->master->dev, "registered MPC5200 SPI bus\n");
|
|
|
|
|
|
|
|
return rc;
|
|
|
|
|
|
|
|
err_register:
|
|
|
|
dev_err(&ms->master->dev, "initialization failed\n");
|
2009-11-13 02:41:17 -07:00
|
|
|
err_gpio:
|
|
|
|
while (i-- > 0)
|
|
|
|
gpio_free(ms->gpio_cs[i]);
|
|
|
|
|
2009-11-24 17:18:31 -07:00
|
|
|
kfree(ms->gpio_cs);
|
2012-08-18 10:29:21 -06:00
|
|
|
err_alloc_gpio:
|
|
|
|
spi_master_put(master);
|
2009-11-04 15:34:18 -07:00
|
|
|
err_alloc:
|
|
|
|
err_init:
|
|
|
|
iounmap(regs);
|
|
|
|
return rc;
|
|
|
|
}
|
|
|
|
|
2012-12-07 09:57:14 -07:00
|
|
|
static int mpc52xx_spi_remove(struct platform_device *op)
|
2009-11-04 15:34:18 -07:00
|
|
|
{
|
2013-05-23 04:20:40 -06:00
|
|
|
struct spi_master *master = spi_master_get(platform_get_drvdata(op));
|
2009-11-04 15:34:18 -07:00
|
|
|
struct mpc52xx_spi *ms = spi_master_get_devdata(master);
|
2009-11-13 02:41:17 -07:00
|
|
|
int i;
|
2009-11-04 15:34:18 -07:00
|
|
|
|
|
|
|
free_irq(ms->irq0, ms);
|
|
|
|
free_irq(ms->irq1, ms);
|
|
|
|
|
2009-11-13 02:41:17 -07:00
|
|
|
for (i = 0; i < ms->gpio_cs_count; i++)
|
|
|
|
gpio_free(ms->gpio_cs[i]);
|
|
|
|
|
2009-11-24 17:18:31 -07:00
|
|
|
kfree(ms->gpio_cs);
|
2009-11-04 15:34:18 -07:00
|
|
|
spi_unregister_master(master);
|
|
|
|
iounmap(ms->regs);
|
2012-08-18 10:29:22 -06:00
|
|
|
spi_master_put(master);
|
2009-11-04 15:34:18 -07:00
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2012-12-07 09:57:14 -07:00
|
|
|
static const struct of_device_id mpc52xx_spi_match[] = {
|
2009-11-04 15:34:18 -07:00
|
|
|
{ .compatible = "fsl,mpc5200-spi", },
|
|
|
|
{}
|
|
|
|
};
|
|
|
|
MODULE_DEVICE_TABLE(of, mpc52xx_spi_match);
|
|
|
|
|
2011-02-22 21:02:43 -07:00
|
|
|
static struct platform_driver mpc52xx_spi_of_driver = {
|
2010-04-13 17:13:02 -06:00
|
|
|
.driver = {
|
|
|
|
.name = "mpc52xx-spi",
|
|
|
|
.owner = THIS_MODULE,
|
|
|
|
.of_match_table = mpc52xx_spi_match,
|
|
|
|
},
|
2009-11-04 15:34:18 -07:00
|
|
|
.probe = mpc52xx_spi_probe,
|
2012-12-07 09:57:14 -07:00
|
|
|
.remove = mpc52xx_spi_remove,
|
2009-11-04 15:34:18 -07:00
|
|
|
};
|
2011-10-05 11:29:49 -06:00
|
|
|
module_platform_driver(mpc52xx_spi_of_driver);
|