2005-04-16 16:20:36 -06:00
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/* linux/include/asm-arm/arch-s3c2410/irqs.h
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*
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* Copyright (c) 2003-2005 Simtec Electronics
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* Ben Dooks <ben@simtec.co.uk>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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2006-09-09 12:44:52 -06:00
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*/
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2005-04-16 16:20:36 -06:00
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#ifndef __ASM_ARCH_IRQS_H
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#define __ASM_ARCH_IRQS_H __FILE__
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/* we keep the first set of CPU IRQs out of the range of
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* the ISA space, so that the PC104 has them to itself
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* and we don't end up having to do horrible things to the
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* standard ISA drivers....
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*/
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#define S3C2410_CPUIRQ_OFFSET (16)
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#define S3C2410_IRQ(x) ((x) + S3C2410_CPUIRQ_OFFSET)
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/* main cpu interrupts */
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#define IRQ_EINT0 S3C2410_IRQ(0) /* 16 */
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#define IRQ_EINT1 S3C2410_IRQ(1)
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#define IRQ_EINT2 S3C2410_IRQ(2)
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#define IRQ_EINT3 S3C2410_IRQ(3)
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#define IRQ_EINT4t7 S3C2410_IRQ(4) /* 20 */
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#define IRQ_EINT8t23 S3C2410_IRQ(5)
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#define IRQ_RESERVED6 S3C2410_IRQ(6) /* for s3c2410 */
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#define IRQ_CAM S3C2410_IRQ(6) /* for s3c2440 */
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#define IRQ_BATT_FLT S3C2410_IRQ(7)
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#define IRQ_TICK S3C2410_IRQ(8) /* 24 */
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#define IRQ_WDT S3C2410_IRQ(9)
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#define IRQ_TIMER0 S3C2410_IRQ(10)
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#define IRQ_TIMER1 S3C2410_IRQ(11)
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#define IRQ_TIMER2 S3C2410_IRQ(12)
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#define IRQ_TIMER3 S3C2410_IRQ(13)
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#define IRQ_TIMER4 S3C2410_IRQ(14)
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#define IRQ_UART2 S3C2410_IRQ(15)
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#define IRQ_LCD S3C2410_IRQ(16) /* 32 */
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#define IRQ_DMA0 S3C2410_IRQ(17)
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#define IRQ_DMA1 S3C2410_IRQ(18)
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#define IRQ_DMA2 S3C2410_IRQ(19)
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#define IRQ_DMA3 S3C2410_IRQ(20)
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#define IRQ_SDI S3C2410_IRQ(21)
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#define IRQ_SPI0 S3C2410_IRQ(22)
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#define IRQ_UART1 S3C2410_IRQ(23)
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#define IRQ_RESERVED24 S3C2410_IRQ(24) /* 40 */
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#define IRQ_NFCON S3C2410_IRQ(24) /* for s3c2440 */
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#define IRQ_USBD S3C2410_IRQ(25)
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#define IRQ_USBH S3C2410_IRQ(26)
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#define IRQ_IIC S3C2410_IRQ(27)
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#define IRQ_UART0 S3C2410_IRQ(28) /* 44 */
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#define IRQ_SPI1 S3C2410_IRQ(29)
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#define IRQ_RTC S3C2410_IRQ(30)
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#define IRQ_ADCPARENT S3C2410_IRQ(31)
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/* interrupts generated from the external interrupts sources */
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#define IRQ_EINT4 S3C2410_IRQ(32) /* 48 */
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#define IRQ_EINT5 S3C2410_IRQ(33)
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#define IRQ_EINT6 S3C2410_IRQ(34)
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#define IRQ_EINT7 S3C2410_IRQ(35)
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#define IRQ_EINT8 S3C2410_IRQ(36)
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#define IRQ_EINT9 S3C2410_IRQ(37)
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#define IRQ_EINT10 S3C2410_IRQ(38)
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#define IRQ_EINT11 S3C2410_IRQ(39)
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#define IRQ_EINT12 S3C2410_IRQ(40)
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#define IRQ_EINT13 S3C2410_IRQ(41)
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#define IRQ_EINT14 S3C2410_IRQ(42)
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#define IRQ_EINT15 S3C2410_IRQ(43)
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#define IRQ_EINT16 S3C2410_IRQ(44)
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#define IRQ_EINT17 S3C2410_IRQ(45)
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#define IRQ_EINT18 S3C2410_IRQ(46)
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#define IRQ_EINT19 S3C2410_IRQ(47)
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#define IRQ_EINT20 S3C2410_IRQ(48) /* 64 */
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#define IRQ_EINT21 S3C2410_IRQ(49)
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#define IRQ_EINT22 S3C2410_IRQ(50)
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#define IRQ_EINT23 S3C2410_IRQ(51)
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#define IRQ_EINT(x) S3C2410_IRQ((x >= 4) ? (IRQ_EINT4 + (x) - 4) : (S3C2410_IRQ(0) + (x)))
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#define IRQ_LCD_FIFO S3C2410_IRQ(52)
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#define IRQ_LCD_FRAME S3C2410_IRQ(53)
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/* IRQs for the interal UARTs, and ADC
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* these need to be ordered in number of appearance in the
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* SUBSRC mask register
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*/
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#define IRQ_S3CUART_RX0 S3C2410_IRQ(54) /* 70 */
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#define IRQ_S3CUART_TX0 S3C2410_IRQ(55) /* 71 */
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#define IRQ_S3CUART_ERR0 S3C2410_IRQ(56)
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#define IRQ_S3CUART_RX1 S3C2410_IRQ(57)
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#define IRQ_S3CUART_TX1 S3C2410_IRQ(58)
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#define IRQ_S3CUART_ERR1 S3C2410_IRQ(59)
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#define IRQ_S3CUART_RX2 S3C2410_IRQ(60)
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#define IRQ_S3CUART_TX2 S3C2410_IRQ(61)
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#define IRQ_S3CUART_ERR2 S3C2410_IRQ(62)
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#define IRQ_TC S3C2410_IRQ(63)
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#define IRQ_ADC S3C2410_IRQ(64)
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/* extra irqs for s3c2440 */
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#define IRQ_S3C2440_CAM_C S3C2410_IRQ(65)
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#define IRQ_S3C2440_CAM_P S3C2410_IRQ(66)
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#define IRQ_S3C2440_WDT S3C2410_IRQ(67)
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#define IRQ_S3C2440_AC97 S3C2410_IRQ(68)
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#define NR_IRQS (IRQ_S3C2440_AC97+1)
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#endif /* __ASM_ARCH_IRQ_H */
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