2006-01-31 19:29:18 -07:00
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/* arch/sparc64/mm/tsb.c
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*
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* Copyright (C) 2006 David S. Miller <davem@davemloft.net>
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*/
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#include <linux/kernel.h>
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#include <asm/system.h>
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#include <asm/page.h>
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#include <asm/tlbflush.h>
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#include <asm/tlb.h>
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2006-01-31 19:31:06 -07:00
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#include <asm/mmu_context.h>
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2006-01-31 19:31:20 -07:00
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#include <asm/pgtable.h>
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2006-01-31 19:31:38 -07:00
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#include <asm/tsb.h>
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2006-01-31 19:29:18 -07:00
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extern struct tsb swapper_tsb[KERNEL_TSB_NENTRIES];
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2006-01-31 19:31:20 -07:00
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static inline unsigned long tsb_hash(unsigned long vaddr, unsigned long nentries)
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2006-01-31 19:29:18 -07:00
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{
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vaddr >>= PAGE_SHIFT;
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2006-01-31 19:31:20 -07:00
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return vaddr & (nentries - 1);
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2006-01-31 19:29:18 -07:00
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}
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static inline int tag_compare(struct tsb *entry, unsigned long vaddr, unsigned long context)
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{
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if (context == ~0UL)
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return 1;
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return (entry->tag == ((vaddr >> 22) | (context << 48)));
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}
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/* TSB flushes need only occur on the processor initiating the address
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* space modification, not on each cpu the address space has run on.
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* Only the TLB flush needs that treatment.
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*/
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void flush_tsb_kernel_range(unsigned long start, unsigned long end)
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{
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unsigned long v;
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for (v = start; v < end; v += PAGE_SIZE) {
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2006-01-31 19:31:20 -07:00
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unsigned long hash = tsb_hash(v, KERNEL_TSB_NENTRIES);
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struct tsb *ent = &swapper_tsb[hash];
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2006-01-31 19:29:18 -07:00
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if (tag_compare(ent, v, 0)) {
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ent->tag = 0UL;
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membar_storeload_storestore();
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}
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}
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}
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void flush_tsb_user(struct mmu_gather *mp)
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{
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struct mm_struct *mm = mp->mm;
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2006-01-31 19:31:20 -07:00
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struct tsb *tsb = mm->context.tsb;
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2006-01-31 19:29:18 -07:00
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unsigned long ctx = ~0UL;
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2006-01-31 19:31:20 -07:00
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unsigned long nentries = mm->context.tsb_nentries;
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2006-01-31 19:29:18 -07:00
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int i;
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if (CTX_VALID(mm->context))
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ctx = CTX_HWBITS(mm->context);
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for (i = 0; i < mp->tlb_nr; i++) {
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unsigned long v = mp->vaddrs[i];
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struct tsb *ent;
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v &= ~0x1UL;
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2006-01-31 19:31:20 -07:00
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ent = &tsb[tsb_hash(v, nentries)];
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2006-01-31 19:29:18 -07:00
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if (tag_compare(ent, v, ctx)) {
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ent->tag = 0UL;
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membar_storeload_storestore();
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}
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}
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}
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2006-01-31 19:31:06 -07:00
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2006-01-31 19:31:20 -07:00
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static void setup_tsb_params(struct mm_struct *mm, unsigned long tsb_bytes)
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{
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unsigned long tsb_reg, base, tsb_paddr;
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unsigned long page_sz, tte;
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mm->context.tsb_nentries = tsb_bytes / sizeof(struct tsb);
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base = TSBMAP_BASE;
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tte = (_PAGE_VALID | _PAGE_L | _PAGE_CP |
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_PAGE_CV | _PAGE_P | _PAGE_W);
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tsb_paddr = __pa(mm->context.tsb);
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/* Use the smallest page size that can map the whole TSB
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* in one TLB entry.
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*/
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switch (tsb_bytes) {
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case 8192 << 0:
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tsb_reg = 0x0UL;
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#ifdef DCACHE_ALIASING_POSSIBLE
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base += (tsb_paddr & 8192);
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#endif
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tte |= _PAGE_SZ8K;
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page_sz = 8192;
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break;
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case 8192 << 1:
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tsb_reg = 0x1UL;
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tte |= _PAGE_SZ64K;
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page_sz = 64 * 1024;
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break;
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case 8192 << 2:
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tsb_reg = 0x2UL;
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tte |= _PAGE_SZ64K;
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page_sz = 64 * 1024;
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break;
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case 8192 << 3:
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tsb_reg = 0x3UL;
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tte |= _PAGE_SZ64K;
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page_sz = 64 * 1024;
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break;
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case 8192 << 4:
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tsb_reg = 0x4UL;
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tte |= _PAGE_SZ512K;
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page_sz = 512 * 1024;
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break;
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case 8192 << 5:
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tsb_reg = 0x5UL;
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tte |= _PAGE_SZ512K;
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page_sz = 512 * 1024;
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break;
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case 8192 << 6:
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tsb_reg = 0x6UL;
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tte |= _PAGE_SZ512K;
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page_sz = 512 * 1024;
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break;
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case 8192 << 7:
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tsb_reg = 0x7UL;
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tte |= _PAGE_SZ4MB;
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page_sz = 4 * 1024 * 1024;
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break;
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2006-01-31 19:31:38 -07:00
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default:
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BUG();
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2006-01-31 19:31:20 -07:00
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};
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tsb_reg |= base;
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tsb_reg |= (tsb_paddr & (page_sz - 1UL));
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tte |= (tsb_paddr & ~(page_sz - 1UL));
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mm->context.tsb_reg_val = tsb_reg;
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mm->context.tsb_map_vaddr = base;
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mm->context.tsb_map_pte = tte;
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}
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2006-01-31 19:31:38 -07:00
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/* The page tables are locked against modifications while this
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* runs.
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*
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* XXX do some prefetching...
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*/
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static void copy_tsb(struct tsb *old_tsb, unsigned long old_size,
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struct tsb *new_tsb, unsigned long new_size)
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{
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unsigned long old_nentries = old_size / sizeof(struct tsb);
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unsigned long new_nentries = new_size / sizeof(struct tsb);
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unsigned long i;
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for (i = 0; i < old_nentries; i++) {
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register unsigned long tag asm("o4");
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register unsigned long pte asm("o5");
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unsigned long v;
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unsigned int hash;
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__asm__ __volatile__(
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"ldda [%2] %3, %0"
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: "=r" (tag), "=r" (pte)
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: "r" (&old_tsb[i]), "i" (ASI_NUCLEUS_QUAD_LDD));
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2006-01-31 19:32:44 -07:00
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if (!tag || (tag & (1UL << TSB_TAG_LOCK_BIT)))
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2006-01-31 19:31:38 -07:00
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continue;
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/* We only put base page size PTEs into the TSB,
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* but that might change in the future. This code
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* would need to be changed if we start putting larger
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* page size PTEs into there.
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*/
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WARN_ON((pte & _PAGE_ALL_SZ_BITS) != _PAGE_SZBITS);
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/* The tag holds bits 22 to 63 of the virtual address
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* and the context. Clear out the context, and shift
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* up to make a virtual address.
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*/
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v = (tag & ((1UL << 42UL) - 1UL)) << 22UL;
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/* The implied bits of the tag (bits 13 to 21) are
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* determined by the TSB entry index, so fill that in.
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*/
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v |= (i & (512UL - 1UL)) << 13UL;
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hash = tsb_hash(v, new_nentries);
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new_tsb[hash].tag = tag;
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new_tsb[hash].pte = pte;
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}
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}
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/* When the RSS of an address space exceeds mm->context.tsb_rss_limit,
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* update_mmu_cache() invokes this routine to try and grow the TSB.
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* When we reach the maximum TSB size supported, we stick ~0UL into
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* mm->context.tsb_rss_limit so the grow checks in update_mmu_cache()
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* will not trigger any longer.
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*
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* The TSB can be anywhere from 8K to 1MB in size, in increasing powers
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* of two. The TSB must be aligned to it's size, so f.e. a 512K TSB
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* must be 512K aligned.
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*
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* The idea here is to grow the TSB when the RSS of the process approaches
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* the number of entries that the current TSB can hold at once. Currently,
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* we trigger when the RSS hits 3/4 of the TSB capacity.
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*/
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void tsb_grow(struct mm_struct *mm, unsigned long rss, gfp_t gfp_flags)
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{
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unsigned long max_tsb_size = 1 * 1024 * 1024;
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unsigned long size, old_size;
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struct page *page;
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struct tsb *old_tsb;
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if (max_tsb_size > (PAGE_SIZE << MAX_ORDER))
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max_tsb_size = (PAGE_SIZE << MAX_ORDER);
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for (size = PAGE_SIZE; size < max_tsb_size; size <<= 1UL) {
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unsigned long n_entries = size / sizeof(struct tsb);
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n_entries = (n_entries * 3) / 4;
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if (n_entries > rss)
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break;
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}
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page = alloc_pages(gfp_flags | __GFP_ZERO, get_order(size));
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if (unlikely(!page))
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return;
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if (size == max_tsb_size)
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mm->context.tsb_rss_limit = ~0UL;
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else
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mm->context.tsb_rss_limit =
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((size / sizeof(struct tsb)) * 3) / 4;
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old_tsb = mm->context.tsb;
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old_size = mm->context.tsb_nentries * sizeof(struct tsb);
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if (old_tsb)
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copy_tsb(old_tsb, old_size, page_address(page), size);
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mm->context.tsb = page_address(page);
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setup_tsb_params(mm, size);
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/* If old_tsb is NULL, we're being invoked for the first time
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* from init_new_context().
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*/
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if (old_tsb) {
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/* Now force all other processors to reload the new
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* TSB state.
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*/
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smp_tsb_sync(mm);
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/* Finally reload it on the local cpu. No further
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* references will remain to the old TSB and we can
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* thus free it up.
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*/
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tsb_context_switch(mm);
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free_pages((unsigned long) old_tsb, get_order(old_size));
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}
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}
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2006-01-31 19:31:06 -07:00
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int init_new_context(struct task_struct *tsk, struct mm_struct *mm)
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{
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2006-01-31 19:31:38 -07:00
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unsigned long initial_rss;
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2006-01-31 19:31:06 -07:00
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mm->context.sparc64_ctx_val = 0UL;
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2006-01-31 19:31:38 -07:00
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/* copy_mm() copies over the parent's mm_struct before calling
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* us, so we need to zero out the TSB pointer or else tsb_grow()
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* will be confused and think there is an older TSB to free up.
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*/
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mm->context.tsb = NULL;
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/* If this is fork, inherit the parent's TSB size. We would
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* grow it to that size on the first page fault anyways.
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*/
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initial_rss = mm->context.tsb_nentries;
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if (initial_rss)
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initial_rss -= 1;
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tsb_grow(mm, initial_rss, GFP_KERNEL);
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if (unlikely(!mm->context.tsb))
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return -ENOMEM;
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2006-01-31 19:31:06 -07:00
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return 0;
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}
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void destroy_context(struct mm_struct *mm)
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{
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2006-01-31 19:31:38 -07:00
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unsigned long size = mm->context.tsb_nentries * sizeof(struct tsb);
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free_pages((unsigned long) mm->context.tsb, get_order(size));
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2006-01-31 19:31:20 -07:00
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/* We can remove these later, but for now it's useful
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* to catch any bogus post-destroy_context() references
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* to the TSB.
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*/
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mm->context.tsb = NULL;
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mm->context.tsb_reg_val = 0UL;
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2006-01-31 19:31:06 -07:00
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spin_lock(&ctx_alloc_lock);
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if (CTX_VALID(mm->context)) {
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unsigned long nr = CTX_NRBITS(mm->context);
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mmu_context_bmap[nr>>6] &= ~(1UL << (nr & 63));
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}
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spin_unlock(&ctx_alloc_lock);
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}
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